diff options
Diffstat (limited to 'board/freescale')
56 files changed, 492 insertions, 3316 deletions
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 1b1fd69cb2..17db755951 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -21,18 +21,37 @@ config CMD_ESBC_VALIDATE esbc_validate - validate signature using RSA verification esbc_halt - put the core in spin loop (Secure Boot Only) +config VID + depends on DM_I2C + bool "Enable Freescale VID" + help + This option enables setting core voltage based on individual + values saved in SoC fuses. + config VOL_MONITOR_LTC3882_READ depends on VID bool "Enable the LTC3882 voltage monitor read" - default n help This option enables LTC3882 voltage monitor read - functionality. It is used by common VID driver. + functionality. It is used by the common VID driver. config VOL_MONITOR_LTC3882_SET depends on VID bool "Enable the LTC3882 voltage monitor set" - default n help This option enables LTC3882 voltage monitor set - functionality. It is used by common VID driver. + functionality. It is used by the common VID driver. + +config VOL_MONITOR_ISL68233_READ + depends on VID + bool "Enable the ISL68233 voltage monitor read" + help + This option enables ISL68233 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_ISL68233_SET + depends on VID + bool "Enable the ISL68233 voltage monitor set" + help + This option enables ISL68233 voltage monitor set + functionality. It is used by the common VID driver. diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index ae66039857..596cd0018c 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -63,20 +63,7 @@ int pib_init(void) #endif #if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_TARGET_MPC8569MDS) - val8 = 0; - i2c_write(0x20, 0x6, 1, &val8, 1); - i2c_write(0x20, 0x7, 1, &val8, 1); - - val8 = 0xdf; - i2c_write(0x20, 0x2, 1, &val8, 1); - val8 = 0xf7; - i2c_write(0x20, 0x3, 1, &val8, 1); - - eieio(); - - printf("QOC3 ATM card on PMC0\n"); -#elif defined(CONFIG_TARGET_MPC832XEMDS) +#if defined(CONFIG_TARGET_MPC832XEMDS) val8 = 0; i2c_write(0x26, 0x7, 1, &val8, 1); val8 = 0xf7; diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 20f5421da0..6e8296293b 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -2,6 +2,7 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. * Copyright 2020 NXP + * Copyright 2020 Stephen Carlson <stcarlso@linux.microsoft.com> */ #include <common.h> @@ -21,14 +22,22 @@ #include <linux/delay.h> #include "vid.h" +/* Voltages are generally handled in mV to keep them as integers */ +#define MV_PER_V 1000 + +/* + * Select the channel on the I2C mux (on some NXP boards) that contains + * the voltage regulator to use for VID. Return 0 for success or nonzero + * for failure. + */ int __weak i2c_multiplexer_select_vid_channel(u8 channel) { return 0; } /* - * Compensate for a board specific voltage drop between regulator and SoC - * return a value in mV + * Compensate for a board specific voltage drop between regulator and SoC. + * Returns the voltage offset in mV. */ int __weak board_vdd_drop_compensation(void) { @@ -36,13 +45,94 @@ int __weak board_vdd_drop_compensation(void) } /* - * Board specific settings for specific voltage value + * Performs any board specific adjustments after the VID voltage has been + * set. Return 0 for success or nonzero for failure. */ int __weak board_adjust_vdd(int vdd) { return 0; } +/* + * Processor specific method of converting the fuse value read from VID + * registers into the core voltage to supply. Return the voltage in mV. + */ +u16 __weak soc_get_fuse_vid(int vid_index) +{ + /* Default VDD for Layerscape Chassis 1 devices */ + static const u16 vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + return vdd[vid_index]; +} + +#ifndef I2C_VOL_MONITOR_ADDR +#define I2C_VOL_MONITOR_ADDR 0 +#endif + +#if CONFIG_IS_ENABLED(DM_I2C) +#define DEVICE_HANDLE_T struct udevice * + +#ifndef I2C_VOL_MONITOR_BUS +#define I2C_VOL_MONITOR_BUS 0 +#endif + +/* If DM is in use, retrieve the udevice chip for the specified bus number */ +static int vid_get_device(int address, DEVICE_HANDLE_T *dev) +{ + int ret = i2c_get_chip_for_busnum(I2C_VOL_MONITOR_BUS, address, 1, dev); + + if (ret) + printf("VID: Bus %d has no device with address 0x%02X\n", + I2C_VOL_MONITOR_BUS, address); + return ret; +} + +#define I2C_READ(dev, register, data, length) \ + dm_i2c_read(dev, register, data, length) +#define I2C_WRITE(dev, register, data, length) \ + dm_i2c_write(dev, register, data, length) +#else +#define DEVICE_HANDLE_T int + +/* If DM is not in use, I2C addresses are passed directly */ +static int vid_get_device(int address, DEVICE_HANDLE_T *dev) +{ + *dev = address; + return 0; +} + +#define I2C_READ(dev, register, data, length) \ + i2c_read(dev, register, 1, data, length) +#define I2C_WRITE(dev, register, data, length) \ + i2c_write(dev, register, 1, data, length) +#endif + #if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ defined(CONFIG_VOL_MONITOR_IR36021_READ) /* @@ -60,30 +150,22 @@ int __weak board_adjust_vdd(int vdd) */ static int find_ir_chip_on_i2c(void) { - int i2caddress; - int ret; - u8 byte; - int i; + int i2caddress, ret, i; + u8 mfrID; const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; -#endif + DEVICE_HANDLE_T dev; /* Check all the address */ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { i2caddress = ir_i2c_addr[i]; -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(i2caddress, - IR36021_MFR_ID_OFFSET, 1, (void *)&byte, - sizeof(byte)); -#else - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET, - (void *)&byte, sizeof(byte)); -#endif - if ((ret >= 0) && (byte == IR36021_MFR_ID)) - return i2caddress; + ret = vid_get_device(i2caddress, &dev); + if (!ret) { + ret = I2C_READ(dev, IR36021_MFR_ID_OFFSET, + (void *)&mfrID, sizeof(mfrID)); + /* If manufacturer ID matches the IR36021 */ + if (!ret && mfrID == IR36021_MFR_ID) + return i2caddress; + } } return -1; } @@ -117,35 +199,33 @@ static int read_voltage_from_INA220(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf[2]; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; -#endif + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; for (i = 0; i < NUM_READINGS; i++) { -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - I2C_VOL_MONITOR_BUS_V_OFFSET, 1, - (void *)&buf, 2); -#else - ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, - (void *)&buf, 2); -#endif + ret = I2C_READ(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&buf[0], sizeof(buf)); if (ret) { printf("VID: failed to read core voltage\n"); return ret; } + vol_mon = (buf[0] << 8) | buf[1]; if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { printf("VID: Core voltage sensor error\n"); return -1; } + debug("VID: bus voltage reads 0x%04x\n", vol_mon); /* LSB = 4mv */ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; udelay(WAIT_FOR_ADC); } + /* calculate the average */ voltage_read /= NUM_READINGS; @@ -153,30 +233,25 @@ static int read_voltage_from_INA220(int i2caddress) } #endif -/* read voltage from IR */ #ifdef CONFIG_VOL_MONITOR_IR36021_READ +/* read voltage from IR */ static int read_voltage_from_IR(int i2caddress) { int i, ret, voltage_read = 0; u16 vol_mon; u8 buf; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; -#endif + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; for (i = 0; i < NUM_READINGS; i++) { -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(i2caddress, - IR36021_LOOP1_VOUT_OFFSET, - 1, (void *)&buf, 1); -#else - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET, - (void *)&buf, 1); -#endif + ret = I2C_READ(dev, IR36021_LOOP1_VOUT_OFFSET, (void *)&buf, + sizeof(buf)); if (ret) { - printf("VID: failed to read vcpu\n"); + printf("VID: failed to read core voltage\n"); return ret; } vol_mon = buf; @@ -188,7 +263,7 @@ static int read_voltage_from_IR(int i2caddress) /* Resolution is 1/128V. We scale up here to get 1/128mV * and divide at the end */ - voltage_read += vol_mon * 1000; + voltage_read += vol_mon * MV_PER_V; udelay(WAIT_FOR_ADC); } /* Scale down to the real mV as IR resolution is 1/128V, rounding up */ @@ -206,49 +281,94 @@ static int read_voltage_from_IR(int i2caddress) } #endif -#ifdef CONFIG_VOL_MONITOR_LTC3882_READ -/* read the current value of the LTC Regulator Voltage */ -static int read_voltage_from_LTC(int i2caddress) -{ - int ret, vcode = 0; - u8 chan = PWM_CHANNEL0; +#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \ + defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) -#if !CONFIG_IS_ENABLED(DM_I2C) - /* select the PAGE 0 using PMBus commands PAGE for VDD*/ - ret = i2c_write(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_PAGE, 1, &chan, 1); -#else - struct udevice *dev; +/* + * The message displayed if the VOUT exponent causes a resolution + * worse than 1.0 V (if exponent is >= 0). + */ +#define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n" - ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1); -#endif +/* Checks the PMBus voltage monitor for the format used for voltage values */ +static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) +{ + u8 mode; + int exponent, multiplier, ret; + + ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode)); if (ret) { - printf("VID: failed to select VDD Page 0\n"); + printf("VID: unable to determine voltage multiplier\n"); + return 1; + } + + /* Upper 3 bits is mode, lower 5 bits is exponent */ + exponent = (int)mode & 0x1F; + mode >>= 5; + switch (mode) { + case 0: + /* Linear, 5 bit twos component exponent */ + if (exponent & 0x10) { + multiplier = 1 << (16 - (exponent & 0xF)); + } else { + /* If exponent is >= 0, then resolution is 1 V! */ + printf(VOUT_WARNING); + multiplier = 1; + } + break; + case 1: + /* VID code identifier */ + printf("VID: custom VID codes are not supported\n"); + multiplier = MV_PER_V; + break; + default: + /* Direct, in mV */ + multiplier = MV_PER_V; + break; + } + + debug("VID: calculated multiplier is %d\n", multiplier); + return multiplier; +} +#endif + +#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) +static int read_voltage_from_pmbus(int i2caddress) +{ + int ret, multiplier, vout; + u8 channel = PWM_CHANNEL0; + u16 vcode; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) return ret; - } -#if !CONFIG_IS_ENABLED(DM_I2C) - /*read the output voltage using PMBus command READ_VOUT*/ - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); -#else - ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + /* Select the right page */ + ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel)); if (ret) { - printf("VID: failed to read the volatge\n"); + printf("VID: failed to select VDD page %d\n", channel); return ret; } -#endif + + /* VOUT is little endian */ + ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode)); if (ret) { - printf("VID: failed to read the volatge\n"); + printf("VID: failed to read core voltage\n"); return ret; } - /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */ - vcode = DIV_ROUND_UP(vcode * 1000, 4096); - - return vcode; + /* Scale down to the real mV */ + multiplier = get_pmbus_multiplier(dev); + vout = (int)vcode; + /* Multiplier 1000 (direct mode) requires no change to convert */ + if (multiplier != MV_PER_V) + vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier); + return vout - board_vdd_drop_compensation(); } #endif @@ -256,13 +376,14 @@ static int read_voltage(int i2caddress) { int voltage_read; #ifdef CONFIG_VOL_MONITOR_INA220 - voltage_read = read_voltage_from_INA220(i2caddress); + voltage_read = read_voltage_from_INA220(I2C_VOL_MONITOR_ADDR); #elif defined CONFIG_VOL_MONITOR_IR36021_READ voltage_read = read_voltage_from_IR(i2caddress); -#elif defined CONFIG_VOL_MONITOR_LTC3882_READ - voltage_read = read_voltage_from_LTC(i2caddress); +#elif defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) + voltage_read = read_voltage_from_pmbus(i2caddress); #else - return -1; + voltage_read = -1; #endif return voltage_read; } @@ -300,7 +421,7 @@ static int wait_for_new_voltage(int vdd, int i2caddress) } /* - * this function keeps reading the voltage until it is stable or until the + * Blocks and reads the VID voltage until it stabilizes, or the * timeout expires */ static int wait_for_voltage_stable(int i2caddress) @@ -310,9 +431,9 @@ static int wait_for_voltage_stable(int i2caddress) vdd = read_voltage(i2caddress); udelay(NUM_READINGS * WAIT_FOR_ADC); - /* wait until voltage is stable */ vdd_current = read_voltage(i2caddress); - /* The maximum timeout is + /* + * The maximum timeout is * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC */ for (timeout = MAX_LOOP_WAIT_VOL_STABLE; @@ -327,12 +448,18 @@ static int wait_for_voltage_stable(int i2caddress) return vdd_current; } -/* Set the voltage to the IR chip */ +/* Sets the VID voltage using the IR36021 */ static int set_voltage_to_IR(int i2caddress, int vdd) { int wait, vdd_last; int ret; u8 vid; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; /* Compensate for a board specific voltage drop between regulator and * SoC before converting into an IR VID value @@ -344,20 +471,10 @@ static int set_voltage_to_IR(int i2caddress, int vdd) vid = DIV_ROUND_UP(vdd - 245, 5); #endif -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, - 1, (void *)&vid, sizeof(vid)); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, - (void *)&vid, sizeof(vid)); - -#endif + ret = I2C_WRITE(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, (void *)&vid, + sizeof(vid)); if (ret) { - printf("VID: failed to write VID\n"); + printf("VID: failed to write new voltage\n"); return -1; } wait = wait_for_new_voltage(vdd, i2caddress); @@ -371,81 +488,59 @@ static int set_voltage_to_IR(int i2caddress, int vdd) debug("VID: Current voltage is %d mV\n", vdd_last); return vdd_last; } - #endif -#ifdef CONFIG_VOL_MONITOR_LTC3882_SET -/* this function sets the VDD and returns the value set */ -static int set_voltage_to_LTC(int i2caddress, int vdd) +#if defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) +static int set_voltage_to_pmbus(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; - int count = 100, temp = 0; + int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier; unsigned char value; - /* Scale up to the LTC resolution is 1/4096V */ - vdd = (vdd * 4096) / 1000; + /* The data to be sent with the PMBus command PAGE_PLUS_WRITE */ + u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 }; + DEVICE_HANDLE_T dev; - /* 5-byte buffer which needs to be sent following the - * PMBus command PAGE_PLUS_WRITE. - */ - u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, - vdd & 0xFF, (vdd & 0xFF00) >> 8}; + /* Open device handle */ + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; + + /* Scale up to the proper value for the VOUT command, little endian */ + multiplier = get_pmbus_multiplier(dev); + vdd += board_vdd_drop_compensation(); + if (multiplier != MV_PER_V) + vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V); + buffer[3] = vdd & 0xFF; + buffer[4] = (vdd & 0xFF00) >> 8; - /* Write the desired voltage code to the regulator */ -#if !CONFIG_IS_ENABLED(DM_I2C) /* Check write protect state */ - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_WRITE_PROTECT, 1, - (void *)&value, sizeof(value)); + ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, + sizeof(value)); if (ret) goto exit; if (value != EN_WRITE_ALL_CMD) { value = EN_WRITE_ALL_CMD; - ret = i2c_write(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_WRITE_PROTECT, 1, + ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, sizeof(value)); if (ret) goto exit; } - ret = i2c_write(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_PAGE_PLUS_WRITE, 1, - (void *)&buff, sizeof(buff)); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); - if (!ret) { - /* Check write protect state */ - ret = dm_i2c_read(dev, - PMBUS_CMD_WRITE_PROTECT, - (void *)&value, sizeof(value)); - if (ret) - goto exit; - - if (value != EN_WRITE_ALL_CMD) { - value = EN_WRITE_ALL_CMD; - ret = dm_i2c_write(dev, - PMBUS_CMD_WRITE_PROTECT, - (void *)&value, sizeof(value)); - if (ret) - goto exit; - } - - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, - (void *)&buff, sizeof(buff)); - } -#endif -exit: + /* Write the desired voltage code to the regulator */ + ret = I2C_WRITE(dev, PMBUS_CMD_PAGE_PLUS_WRITE, (void *)&buffer[0], + sizeof(buffer)); if (ret) { - printf("VID: I2C failed to write to the volatge regulator\n"); + printf("VID: I2C failed to write to the voltage regulator\n"); return -1; } - /* Wait for the volatge to get to the desired value */ +exit: + /* Wait for the voltage to get to the desired value */ do { - vdd_last = read_voltage_from_LTC(i2caddress); + vdd_last = read_voltage_from_pmbus(i2caddress); if (vdd_last < 0) { printf("VID: Couldn't read sensor abort VID adjust\n"); return -1; @@ -464,325 +559,80 @@ static int set_voltage(int i2caddress, int vdd) #ifdef CONFIG_VOL_MONITOR_IR36021_SET vdd_last = set_voltage_to_IR(i2caddress, vdd); -#elif defined CONFIG_VOL_MONITOR_LTC3882_SET - vdd_last = set_voltage_to_LTC(i2caddress, vdd); +#elif defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) + vdd_last = set_voltage_to_pmbus(i2caddress, vdd); #else #error Specific voltage monitor must be defined #endif return vdd_last; } -#ifdef CONFIG_FSL_LSCH3 int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 fusesr; -#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ - defined(CONFIG_VOL_MONITOR_IR36021_READ) - u8 vid, buf; #else - u8 vid; + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif - int vdd_target, vdd_current, vdd_last; - int ret, i2caddress = 0; + u8 vid; + u32 fusesr; + int vdd_current, vdd_last, vdd_target; + int ret, i2caddress = I2C_VOL_MONITOR_ADDR; unsigned long vdd_string_override; char *vdd_string; -#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) - static const u16 vdd[32] = { - 8250, - 7875, - 7750, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 8000, - 8125, - 8250, - 0, /* reserved */ - 8500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; -#else -#ifdef CONFIG_ARCH_LS1088A - static const uint16_t vdd[32] = { - 10250, - 9875, - 9750, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 9000, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 10000, /* 1.0000V */ - 10125, - 10250, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; -#else - static const uint16_t vdd[32] = { - 10500, - 0, /* reserved */ - 9750, - 0, /* reserved */ - 9500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 9000, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 10000, /* 1.0000V */ - 0, /* reserved */ - 10250, - 0, /* reserved */ - 10500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; -#endif -#endif - struct vdd_drive { - u8 vid; - unsigned voltage; - }; - - ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); - if (ret) { - debug("VID: I2C failed to switch channel\n"); - ret = -1; - goto exit; - } #if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ defined(CONFIG_VOL_MONITOR_IR36021_READ) - ret = find_ir_chip_on_i2c(); - if (ret < 0) { - printf("VID: Could not find voltage regulator on I2C.\n"); - ret = -1; - goto exit; - } else { - i2caddress = ret; - debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); - } - - /* check IR chip work on Intel mode*/ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(i2caddress, - IR36021_INTEL_MODE_OOFSET, - 1, (void *)&buf, 1); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, - (void *)&buf, 1); -#endif - if (ret) { - printf("VID: failed to read IR chip mode.\n"); - ret = -1; - goto exit; - } - - if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { - printf("VID: IR Chip is not used in Intel mode.\n"); - ret = -1; - goto exit; - } + u8 buf; + DEVICE_HANDLE_T dev; #endif - /* get the voltage ID from fuse status register */ + /* + * VID is used according to the table below + * --------------------------------------- + * | DA_V | + * |-------------------------------------| + * | 5b00000 | 5b00001-5b11110 | 5b11111 | + * ---------------+---------+-----------------+---------| + * | D | 5b00000 | NO VID | VID = DA_V | NO VID | + * | A |----------+---------+-----------------+---------| + * | _ | 5b00001 |VID = | VID = |VID = | + * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| + * | _ | 5b11110 | | | | + * | A |----------+---------+-----------------+---------| + * | L | 5b11111 | No VID | VID = DA_V | NO VID | + * | T | | | | | + * ------------------------------------------------------ + */ +#if defined(CONFIG_FSL_LSCH3) fusesr = in_le32(&gur->dcfg_fusesr); vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; - if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK) { vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; - } - vdd_target = vdd[vid]; - - /* check override variable for overriding VDD */ - vdd_string = env_get(CONFIG_VID_FLS_ENV); - if (vdd_override == 0 && vdd_string && - !strict_strtoul(vdd_string, 10, &vdd_string_override)) - vdd_override = vdd_string_override; - - if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { - vdd_target = vdd_override * 10; /* convert to 1/10 mV */ - debug("VDD override is %lu\n", vdd_override); - } else if (vdd_override != 0) { - printf("Invalid value.\n"); + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; } - - /* divide and round up by 10 to get a value in mV */ - vdd_target = DIV_ROUND_UP(vdd_target, 10); - if (vdd_target == 0) { - debug("VID: VID not used\n"); - ret = 0; - goto exit; - } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) { - /* Check vdd_target is in valid range */ - printf("VID: Target VID %d mV is not in range.\n", - vdd_target); - ret = -1; - goto exit; - } else { - debug("VID: vid = %d mV\n", vdd_target); - } - - /* - * Read voltage monitor to check real voltage. - */ - vdd_last = read_voltage(i2caddress); - if (vdd_last < 0) { - printf("VID: Couldn't read sensor abort VID adjustment\n"); - ret = -1; - goto exit; +#elif defined(CONFIG_FSL_LSCH2) + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK) { + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; } - vdd_current = vdd_last; - debug("VID: Core voltage is currently at %d mV\n", vdd_last); - -#ifdef CONFIG_VOL_MONITOR_LTC3882_SET - /* Set the target voltage */ - vdd_last = vdd_current = set_voltage(i2caddress, vdd_target); #else - /* - * Adjust voltage to at or one step above target. - * As measurements are less precise than setting the values - * we may run through dummy steps that cancel each other - * when stepping up and then down. - */ - while (vdd_last > 0 && - vdd_last < vdd_target) { - vdd_current += IR_VDD_STEP_UP; - vdd_last = set_voltage(i2caddress, vdd_current); - } - while (vdd_last > 0 && - vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { - vdd_current -= IR_VDD_STEP_DOWN; - vdd_last = set_voltage(i2caddress, vdd_current); + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; } - #endif - if (board_adjust_vdd(vdd_target) < 0) { - ret = -1; - goto exit; - } - - if (vdd_last > 0) - printf("VID: Core voltage after adjustment is at %d mV\n", - vdd_last); - else - ret = -1; -exit: - if (re_enable) - enable_interrupts(); - i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); - return ret; -} -#else /* !CONFIG_FSL_LSCH3 */ -int adjust_vdd(ulong vdd_override) -{ - int re_enable = disable_interrupts(); -#if defined(CONFIG_FSL_LSCH2) - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#else - ccsr_gur_t __iomem *gur = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif - u32 fusesr; - u8 vid, buf; - int vdd_target, vdd_current, vdd_last; - int ret, i2caddress; - unsigned long vdd_string_override; - char *vdd_string; - static const uint16_t vdd[32] = { - 0, /* unused */ - 9875, /* 0.9875V */ - 9750, - 9625, - 9500, - 9375, - 9250, - 9125, - 9000, - 8875, - 8750, - 8625, - 8500, - 8375, - 8250, - 8125, - 10000, /* 1.0000V */ - 10125, - 10250, - 10375, - 10500, - 10625, - 10750, - 10875, - 11000, - 0, /* reserved */ - }; - struct vdd_drive { - u8 vid; - unsigned voltage; - }; + vdd_target = soc_get_fuse_vid((int)vid); ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); if (ret) { @@ -790,6 +640,7 @@ int adjust_vdd(ulong vdd_override) ret = -1; goto exit; } + #if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ defined(CONFIG_VOL_MONITOR_IR36021_READ) ret = find_ir_chip_on_i2c(); @@ -802,19 +653,13 @@ int adjust_vdd(ulong vdd_override) debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); } - /* check IR chip work on Intel mode*/ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(i2caddress, - IR36021_INTEL_MODE_OOFSET, - 1, (void *)&buf, 1); -#else - struct udevice *dev; + ret = vid_get_device(i2caddress, &dev); + if (ret) + return ret; - ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, - (void *)&buf, 1); -#endif + /* check IR chip work on Intel mode */ + ret = I2C_READ(dev, IR36021_INTEL_MODE_OFFSET, (void *)&buf, + sizeof(buf)); if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; @@ -827,52 +672,18 @@ int adjust_vdd(ulong vdd_override) } #endif - /* get the voltage ID from fuse status register */ - fusesr = in_be32(&gur->dcfg_fusesr); - /* - * VID is used according to the table below - * --------------------------------------- - * | DA_V | - * |-------------------------------------| - * | 5b00000 | 5b00001-5b11110 | 5b11111 | - * ---------------+---------+-----------------+---------| - * | D | 5b00000 | NO VID | VID = DA_V | NO VID | - * | A |----------+---------+-----------------+---------| - * | _ | 5b00001 |VID = | VID = |VID = | - * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| - * | _ | 5b11110 | | | | - * | A |----------+---------+-----------------+---------| - * | L | 5b11111 | No VID | VID = DA_V | NO VID | - * | T | | | | | - * ------------------------------------------------------ - */ -#ifdef CONFIG_FSL_LSCH2 - vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; - if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { - vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & - FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; - } -#else - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; - if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_VID_MASK; - } -#endif - vdd_target = vdd[vid]; - /* check override variable for overriding VDD */ vdd_string = env_get(CONFIG_VID_FLS_ENV); + debug("VID: Initial VDD value is %d mV\n", + DIV_ROUND_UP(vdd_target, 10)); if (vdd_override == 0 && vdd_string && !strict_strtoul(vdd_string, 10, &vdd_string_override)) vdd_override = vdd_string_override; if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { vdd_target = vdd_override * 10; /* convert to 1/10 mV */ - debug("VDD override is %lu\n", vdd_override); + debug("VID: VDD override is %lu\n", vdd_override); } else if (vdd_override != 0) { - printf("Invalid value.\n"); + printf("VID: Invalid VDD value.\n"); } if (vdd_target == 0) { debug("VID: VID not used\n"); @@ -895,6 +706,13 @@ int adjust_vdd(ulong vdd_override) } vdd_current = vdd_last; debug("VID: Core voltage is currently at %d mV\n", vdd_last); + +#if defined(CONFIG_VOL_MONITOR_LTC3882_SET) || \ + defined(CONFIG_VOL_MONITOR_ISL68233_SET) + /* Set the target voltage */ + vdd_current = set_voltage(i2caddress, vdd_target); + vdd_last = vdd_current; +#else /* * Adjust voltage to at or one step above target. * As measurements are less precise than setting the values @@ -911,6 +729,13 @@ int adjust_vdd(ulong vdd_override) vdd_current -= IR_VDD_STEP_DOWN; vdd_last = set_voltage(i2caddress, vdd_current); } +#endif + + /* Board specific adjustments */ + if (board_adjust_vdd(vdd_target) < 0) { + ret = -1; + goto exit; + } if (vdd_last > 0) printf("VID: Core voltage after adjustment is at %d mV\n", @@ -925,11 +750,10 @@ exit: return ret; } -#endif static int print_vdd(void) { - int vdd_last, ret, i2caddress = 0; + int vdd_last, ret, i2caddress = I2C_VOL_MONITOR_ADDR; ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); if (ret) { diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index 5bbaecace4..b34c080b4b 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -7,16 +7,17 @@ #ifndef __VID_H_ #define __VID_H_ +/* IR36021 command codes */ #define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A #define IR36021_LOOP1_VOUT_OFFSET 0x9A #define IR36021_MFR_ID_OFFSET 0x92 #define IR36021_MFR_ID 0x43 -#define IR36021_INTEL_MODE_OOFSET 0x14 +#define IR36021_INTEL_MODE_OFFSET 0x14 #define IR36021_MODE_MASK 0x20 #define IR36021_INTEL_MODE 0x00 #define IR36021_AMD_MODE 0x20 -/* step the IR regulator in 5mV increments */ +/* Step the IR regulator in 5mV increments */ #define IR_VDD_STEP_DOWN 5 #define IR_VDD_STEP_UP 5 @@ -50,15 +51,16 @@ #define VDD_MV_MAX 925 #endif -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ -defined(CONFIG_TARGET_LX2160ARDB) /* PM Bus commands code for LTC3882*/ #define PWM_CHANNEL0 0x0 #define PMBUS_CMD_PAGE 0x0 #define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_VOUT_MODE 0x20 #define PMBUS_CMD_VOUT_COMMAND 0x21 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) /* Voltage monitor on channel 2*/ #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 @@ -68,5 +70,6 @@ defined(CONFIG_TARGET_LX2160ARDB) #endif int adjust_vdd(ulong vdd_override); +u16 soc_get_fuse_vid(int vid_index); #endif /* __VID_H_ */ diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index e22cf703b7..f0da86a34c 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -19,9 +19,3 @@ F: configs/P5040DS_NAND_defconfig F: configs/P5040DS_SDCARD_defconfig F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SECURE_BOOT_defconfig - -CORENET_DS_SECURE_BOOT BOARD -M: Ruchika Gupta <ruchika.gupta@nxp.com> -S: Maintained -F: configs/P3041DS_NAND_SECURE_BOOT_defconfig -F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS index 480b6bb325..5fc7e93850 100644 --- a/board/freescale/ls1012afrdm/MAINTAINERS +++ b/board/freescale/ls1012afrdm/MAINTAINERS @@ -1,5 +1,4 @@ LS1012AFRDM BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> M: Rajesh Bhagat <rajesh.bhagat@nxp.com> S: Maintained F: board/freescale/ls1012afrdm/ @@ -10,12 +9,9 @@ F: configs/ls1012afrwy_tfa_defconfig F: configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig LS1012AFRWY BOARD -M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com> +M: Pramod Kumar <pramod.kumar_1@nxp.com> S: Maintained F: board/freescale/ls1012afrwy/ F: include/configs/ls1012afrwy.h F: configs/ls1012afrwy_qspi_defconfig - -M: Vinitha V Pillai <vinitha.pillai@nxp.com> -S: Maintained F: configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS index dbd4670c3b..c1bb8d5150 100644 --- a/board/freescale/ls1012aqds/MAINTAINERS +++ b/board/freescale/ls1012aqds/MAINTAINERS @@ -1,6 +1,6 @@ LS1012AQDS BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> M: Rajesh Bhagat <rajesh.bhagat@nxp.com> +M: Pramod Kumar <pramod.kumar_1@nxp.com> S: Maintained F: board/freescale/ls1012aqds/ F: include/configs/ls1012aqds.h diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS index 60e184d10f..b0c008b5fc 100644 --- a/board/freescale/ls1012ardb/MAINTAINERS +++ b/board/freescale/ls1012ardb/MAINTAINERS @@ -1,6 +1,6 @@ LS1012ARDB BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> M: Rajesh Bhagat <rajesh.bhagat@nxp.com> +M: Pramod Kumar <pramod.kumar_1@nxp.com> S: Maintained F: board/freescale/ls1012ardb/ F: include/configs/ls1012ardb.h @@ -8,13 +8,10 @@ F: configs/ls1012ardb_qspi_defconfig F: configs/ls1012ardb_tfa_defconfig F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig F: configs/ls1012a2g5rdb_tfa_defconfig - -M: Sumit Garg <sumit.garg@nxp.com> -S: Maintained F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig LS1012A2G5RDB BOARD -M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com> +M: Pramod Kumar <pramod.kumar_1@nxp.com> S: Maintained F: board/freescale/ls1012ardb/ F: include/configs/ls1012a2g5rdb.h diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS index 2dab7988ee..65f21bee34 100644 --- a/board/freescale/ls1021aiot/MAINTAINERS +++ b/board/freescale/ls1021aiot/MAINTAINERS @@ -1,5 +1,5 @@ LS1021AIOT BOARD -M: Feng Li <feng.li_2@nxp.com> +M: Alison Wang <alison.wang@nxp.com> S: Maintained F: board/freescale/ls1021aiot/ F: include/configs/ls1021aiot.h diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index c8b93c6469..7ab8347e9e 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -9,7 +9,4 @@ F: configs/ls1021atwr_nor_lpuart_defconfig F: configs/ls1021atwr_sdcard_ifc_defconfig F: configs/ls1021atwr_sdcard_qspi_defconfig F: configs/ls1021atwr_qspi_defconfig - -M: Sumit Garg <sumit.garg@nxp.com> -S: Maintained F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS index 5b7a8db2fa..9e7b0697ff 100644 --- a/board/freescale/ls1028a/MAINTAINERS +++ b/board/freescale/ls1028a/MAINTAINERS @@ -1,6 +1,4 @@ LS1028AQDS BOARD -M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> -M: Rai Harninder <harninder.rai@nxp.com> M: Rajesh Bhagat <rajesh.bhagat@nxp.com> M: Tang Yuantian <andy.tang@nxp.com> S: Maintained @@ -11,8 +9,6 @@ F: configs/ls1028aqds_tfa_defconfig F: configs/ls1028aqds_tfa_lpuart_defconfig LS1028ARDB BOARD -M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> -M: Rai Harninder <harninder.rai@nxp.com> M: Rajesh Bhagat <rajesh.bhagat@nxp.com> M: Tang Yuantian <andy.tang@nxp.com> S: Maintained diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index ed62396760..36e7331538 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -10,10 +10,6 @@ F: configs/ls1043ardb_nand_defconfig F: configs/ls1043ardb_sdcard_defconfig F: configs/ls1043ardb_tfa_defconfig F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig - -LS1043A_SECURE_BOOT BOARD -M: Ruchika Gupta <ruchika.gupta@nxp.com> -S: Maintained F: configs/ls1043ardb_SECURE_BOOT_defconfig F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS index 39a48da95a..72c4253fcf 100644 --- a/board/freescale/ls1046aqds/MAINTAINERS +++ b/board/freescale/ls1046aqds/MAINTAINERS @@ -12,7 +12,4 @@ F: configs/ls1046aqds_qspi_defconfig F: configs/ls1046aqds_lpuart_defconfig F: configs/ls1046aqds_tfa_defconfig F: configs/ls1046aqds_tfa_SECURE_BOOT_defconfig - -M: Sumit Garg <sumit.garg@nxp.com> -S: Maintained F: configs/ls1046aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index 8b4b45e9ed..efdea22bde 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -11,13 +11,6 @@ F: configs/ls1046ardb_sdcard_defconfig F: configs/ls1046ardb_emmc_defconfig F: configs/ls1046ardb_tfa_defconfig F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig - -LS1046A_SECURE_BOOT BOARD -M: Ruchika Gupta <ruchika.gupta@nxp.com> -S: Maintained F: configs/ls1046ardb_SECURE_BOOT_defconfig F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig - -M: Sumit Garg <sumit.garg@nxp.com> -S: Maintained F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS index 98ecb88e3b..5c7925a95f 100644 --- a/board/freescale/ls1088a/MAINTAINERS +++ b/board/freescale/ls1088a/MAINTAINERS @@ -1,5 +1,4 @@ LS1088ARDB BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> M: Ashish Kumar <Ashish.Kumar@nxp.com> M: Rajesh Bhagat <rajesh.bhagat@nxp.com> S: Maintained @@ -11,7 +10,6 @@ F: configs/ls1088ardb_tfa_defconfig F: configs/ls1088ardb_tfa_SECURE_BOOT_defconfig LS1088AQDS BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> M: Ashish Kumar <Ashish.Kumar@nxp.com> M: Rajesh Bhagat <rajesh.bhagat@nxp.com> S: Maintained @@ -25,17 +23,15 @@ F: configs/ls1088aqds_tfa_defconfig LS1088AQDS_QSPI_SECURE_BOOT BOARD M: Udit Agarwal <udit.agarwal@nxp.com> -M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> S: Maintained F: configs/ls1088aqds_qspi_SECURE_BOOT_defconfig LS1088ARDB_QSPI_SECURE_BOOT BOARD M: Udit Agarwal <udit.agarwal@nxp.com> -M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> S: Maintained F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig LS1088ARDB_SD_SECURE_BOOT BOARD -M: Sumit Garg <sumit.garg@nxp.com> +M: Udit Agarwal <udit.agarwal@nxp.com> S: Maintained F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index e76ea01914..f5dc449d89 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -186,6 +186,46 @@ int init_func_vid(void) return 0; } + +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 10250, + 9875, + 9750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 9000, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 10125, + 10250, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; #endif int is_pb_board(void) diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index e3d7635476..84735dce28 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com> +M: Priyanka Jain <priyanka.jain@nxp.com> M: Rajesh Bhagat <rajesh.bhagat@nxp.com> S: Maintained F: board/freescale/ls2080aqds/ @@ -10,8 +10,4 @@ F: configs/ls2080aqds_nand_defconfig F: configs/ls2080aqds_qspi_defconfig F: configs/ls2080aqds_sdcard_defconfig F: configs/ls2088aqds_tfa_defconfig - -LS2080A_SECURE_BOOT BOARD -#M: Saksham Jain <saksham.jain@nxp.freescale.com> -S: Orphan (since 2018-05) F: configs/ls2080aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index 113b7ab3fd..6e25b82db5 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com> +M: Priyanka Jain <priyanka.jain@nxp.com> S: Maintained F: board/freescale/ls2080ardb/ F: board/freescale/ls2080a/ls2080ardb.c @@ -21,8 +21,8 @@ S: Maintained F: configs/ls2081ardb_defconfig LS2080A_SECURE_BOOT BOARD -#M: Saksham Jain <saksham.jain@nxp.freescale.com> -S: Orphan (since 2018-05) +M: Udit Agarwal <udit.agarwal@nxp.com> +S: Maintained F: configs/ls2080ardb_SECURE_BOOT_defconfig LS2088A_QSPI_SECURE_BOOT BOARD diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c5ae02bc93..3a026b0827 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -43,6 +43,48 @@ enum { MUX_TYPE_DSPI, }; +#ifdef CONFIG_VID +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 10500, + 0, /* reserved */ + 9750, + 0, /* reserved */ + 9500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 9000, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 0, /* reserved */ + 10250, + 0, /* reserved */ + 10500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; +#endif + unsigned long long get_qixis_addr(void) { unsigned long long addr; diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index c627417cf7..cc69de2970 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -16,7 +16,6 @@ F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig LX2160AQDS BOARD M: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> -M: Pankaj Bansal <pankaj.bansal@nxp.com> S: Maintained F: board/freescale/lx2160a/eth_lx2160aqds.h F: include/configs/lx2160aqds.h diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index b32e487e76..47a7024f33 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -649,6 +649,48 @@ int misc_init_r(void) } #endif +#ifdef CONFIG_VID +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 8250, + 7875, + 7750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 8000, + 8125, + 8250, + 0, /* reserved */ + 8500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; +#endif + #ifdef CONFIG_FSL_MC_ENET extern int fdt_fixup_board_phy(void *fdt); diff --git a/board/freescale/mpc8569mds/Kconfig b/board/freescale/mpc8569mds/Kconfig deleted file mode 100644 index 48718575ff..0000000000 --- a/board/freescale/mpc8569mds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8569MDS - -config SYS_BOARD - default "mpc8569mds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8569MDS" - -endif diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS deleted file mode 100644 index 9df3f3cca8..0000000000 --- a/board/freescale/mpc8569mds/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8569MDS BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8569mds/ -F: include/configs/MPC8569MDS.h -F: configs/MPC8569MDS_defconfig -F: configs/MPC8569MDS_ATM_defconfig diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile deleted file mode 100644 index 45718dfdae..0000000000 --- a/board/freescale/mpc8569mds/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2004-2009 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8569mds.o -obj-y += bcsr.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8569mds/README b/board/freescale/mpc8569mds/README deleted file mode 100644 index 86c3ccde79..0000000000 --- a/board/freescale/mpc8569mds/README +++ /dev/null @@ -1,77 +0,0 @@ -Overview --------- -MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform -I/O Board). The mpc8569 PowerTM processor is mounted on PB board. - -Building U-Boot ------------ - make MPC8569MDS_config - make - -Memory Map ----------- -0x0000_0000 0x7fff_ffff DDR 2G -0xa000_0000 0xbfff_ffff PCIe MEM 512MB -0xe000_0000 0xe00f_ffff CCSRBAR 1M -0xe280_0000 0xe2ff_ffff PCIe I/O 8M -0xc000_0000 0xdfff_ffff SRIO 512MB -0xf000_0000 0xf3ff_ffff SDRAM 64MB -0xf800_0000 0xf800_7fff BCSR 32KB -0xf800_8000 0xf800_ffff PIB (CS4) 32KB -0xf801_0000 0xf801_7fff PIB (CS5) 32KB -0xfe00_0000 0xffff_ffff Flash 32MB - - -Flashing U-Boot Images ---------------- - -Use the following commands to program U-Boot image into flash: - - => tftp 1000000 u-boot.bin - => protect off all - => erase fff80000 ffffffff - => cp.b 1000000 fff80000 80000 - - -Setting the correct MAC addresses ------------------------ -The command - "mac", is introduced to set on-board system EEPROM in the format -defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC -addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when -we first get the board. The commands are as follows: - => mac i NXID /* Set NXID to this EEPROM */ - => mac e 01 /* Set Errata, this value is not defined by hardware - designer, we can set whatever we want */ - => mac n a0 /* Set Serial Number. This is not defined by hardware - designer, we can set whatever we want */ - => mac date 090512080000 /* Set the date in YYMMDDhhmmss format */ - - => mac p 8 /* Set the number of mac ports, it should be 8 */ - => mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac - address, you can refer to the value on - the sticker of the rear side of the board - */ - ..... - => mac 7 xx:xx:xx:xx:xx:xx - => mac read - => mac save - -After resetting the board, the ethxaddrs will be filled with the mac addresses -if such environment variables are blank(never been set before). If the ethxaddr -has been set but we want to update it, we can use the following commands: - => setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */ - => save - => reset - - -Programming the ucode to flash ---------------------------------- -MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's -IRAM so that the QE can work. The ucode binary can be downloaded from -http://opensource.freescale.com/firmware/, and it must be programmed to -the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot -hangs at "Net:" - - -Please note the above two steps(setting mac addresses and programming ucode) are -very important to get the board booting up and working properly. diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c deleted file mode 100644 index 9ed00f6e5b..0000000000 --- a/board/freescale/mpc8569mds/bcsr.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <flash.h> -#include <asm/io.h> - -#include "bcsr.h" - -void enable_8569mds_flash_write(void) -{ - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); -} - -void disable_8569mds_flash_write(void) -{ - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); -} - -void enable_8569mds_qe_uec(void) -{ -#if defined(CONFIG_SYS_UCC_RGMII_MODE) - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), - BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), - BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), - BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), - BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); -#elif defined(CONFIG_SYS_UCC_RMII_MODE) - /* Set UCC1-4 working at RMII mode */ - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), - BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), - BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), - BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), - BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); - setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); -#endif -} - -void disable_8569mds_brd_eeprom_write_protect(void) -{ - clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); -} diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h deleted file mode 100644 index fee0fe7dbc..0000000000 --- a/board/freescale/mpc8569mds/bcsr.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009 Freescale Semiconductor, Inc. - */ - -#ifndef __BCSR_H_ -#define __BCSR_H_ - -#include <common.h> - -/* BCSR Bit definitions*/ -/****************************************/ -/* BCSR defines */ -/****************************************/ -#define BCSR6_UPC1_EN 0x80 -#define BCSR6_UPC1_POS_EN 0x40 -#define BCSR6_UPC1_ADDR_EN 0x20 -#define BCSR6_UPC1_DEV2 0x10 -#define BCSR6_SD_CARD_1BIT 0x08 -#define BCSR6_SD_CARD_4BITS 0x04 -#define BCSR6_TDM2G_EN 0x02 -#define BCSR6_UCC7_RMII_EN 0x01 - -#define BCSR7_UCC1_GETH_EN 0x80 -#define BCSR7_UCC1_RGMII_EN 0x40 -#define BCSR7_UCC1_RTBI_EN 0x20 -#define BCSR7_GETHRST_MRVL 0x04 -#define BCSR7_BRD_WRT_PROTECT 0x02 - -#define BCSR8_UCC2_GETH_EN 0x80 -#define BCSR8_UCC2_RGMII_EN 0x40 -#define BCSR8_UCC2_RTBI_EN 0x20 -#define BCSR8_UEM_MARVEL_RESET 0x02 - -#define BCSR9_UCC3_GETH_EN 0x80 -#define BCSR9_UCC3_RGMII_EN 0x40 -#define BCSR9_UCC3_RTBI_EN 0x20 -#define BCSR9_UCC3_RMII_EN 0x10 -#define BCSR9_UCC3_UEM_MICREL 0x01 - -#define BCSR10_UCC4_GETH_EN 0x80 -#define BCSR10_UCC4_RGMII_EN 0x40 -#define BCSR10_UCC4_RTBI_EN 0x20 - -#define BCSR11_LED0 0x40 -#define BCSR11_LED1 0x20 -#define BCSR11_LED2 0x10 - -#define BCSR12_UCC6_RMII_EN 0x20 -#define BCSR12_UCC8_RMII_EN 0x20 - -#define BCSR15_SMII6_DIS 0x08 -#define BCSR15_SMII8_DIS 0x04 -#define BCSR15_QEUART_EN 0x01 - -#define BCSR16_UPC1_DEV2 0x02 - -#define BCSR17_nUSBEN 0x80 -#define BCSR17_nUSBLOWSPD 0x40 -#define BCSR17_USBVCC 0x20 -#define BCSR17_USBMODE 0x10 -#define BCSR17_FLASH_nWP 0x01 - -/*BCSR Utils functions*/ - -void enable_8569mds_flash_write(void); -void disable_8569mds_flash_write(void); -void enable_8569mds_qe_uec(void); -void disable_8569mds_brd_eeprom_write_protect(void); - -#endif /* __BCSR_H_ */ diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c deleted file mode 100644 index d049611e64..0000000000 --- a/board/freescale/mpc8569mds/ddr.c +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 4; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0xff; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 2; - - /* - * Enable half drive strength - */ - popts->half_strength_driver_enable = 1; - - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xa; - popts->wrlvl_start = 0x4; - - /* Rtt and Rtt_W override */ - popts->rtt_override = 1; - popts->rtt_override_value = DDR3_RTT_60_OHM; - popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ -} diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c deleted file mode 100644 index 35cdd75d6e..0000000000 --- a/board/freescale/mpc8569mds/law.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB - *-) 0xe000_0000 0xe00f_ffff CCSR 1M - *2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M - *3) 0xc000_0000 0xdfff_ffff SRIO 512MB - *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB - *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB - *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB - *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB - *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB - * - *Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c deleted file mode 100644 index 1d2cffbacd..0000000000 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ /dev/null @@ -1,590 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2010 Freescale Semiconductor. - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - */ - -#include <common.h> -#include <console.h> -#include <flash.h> -#include <hwconfig.h> -#include <init.h> -#include <log.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <spd_sdram.h> -#include <i2c.h> -#include <ioports.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_esdhc.h> -#include <phy.h> - -#include "bcsr.h" -#if defined(CONFIG_PQ_MDS_PIB) -#include "../common/pq-mds-pib.h" -#endif - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* QE_MUX_MDC */ - {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ - - /* QE_MUX_MDIO */ - {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ - -#if defined(CONFIG_SYS_UCC_RGMII_MODE) - /* UCC_1_RGMII */ - {2, 11, 2, 0, 1}, /* CLK12 */ - {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ - {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ - {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ - {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ - {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ - {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ - {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ - {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ - {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ - {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ - {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ - {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ - - /* UCC_2_RGMII */ - {2, 16, 2, 0, 3}, /* CLK17 */ - {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ - {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ - {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ - {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ - {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ - {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ - {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ - {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ - {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ - {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ - {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ - {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ - - /* UCC_3_RGMII */ - {2, 11, 2, 0, 1}, /* CLK12 */ - {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ - {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ - {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */ - {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */ - {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ - {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ - {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */ - {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */ - {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ - {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ - {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */ - {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */ - - /* UCC_4_RGMII */ - {2, 16, 2, 0, 3}, /* CLK17 */ - {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ - {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ - {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */ - {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */ - {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ - {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ - {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */ - {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */ - {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ - {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ - {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ - {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */ - -#elif defined(CONFIG_SYS_UCC_RMII_MODE) - /* UCC_1_RMII */ - {2, 15, 2, 0, 1}, /* CLK16 */ - {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ - {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ - {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ - {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ - {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ - {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ - - /* UCC_2_RMII */ - {2, 15, 2, 0, 1}, /* CLK16 */ - {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ - {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ - {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ - {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ - {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ - {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ - - /* UCC_3_RMII */ - {2, 15, 2, 0, 1}, /* CLK16 */ - {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ - {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ - {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ - {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ - {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ - {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ - - /* UCC_4_RMII */ - {2, 15, 2, 0, 1}, /* CLK16 */ - {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ - {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ - {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ - {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ - {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ - {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ -#endif - - /* UART1 is muxed with QE PortF bit [9-12].*/ - {5, 12, 2, 0, 3}, /* UART1_SIN */ - {5, 9, 1, 0, 3}, /* UART1_SOUT */ - {5, 10, 2, 0, 3}, /* UART1_CTS_B */ - {5, 11, 1, 0, 2}, /* UART1_RTS_B */ - - /* QE UART */ - {0, 19, 1, 0, 2}, /* QEUART_TX */ - {1, 17, 2, 0, 3}, /* QEUART_RX */ - {0, 25, 1, 0, 1}, /* QEUART_RTS */ - {1, 23, 2, 0, 1}, /* QEUART_CTS */ - - /* QE USB */ - {5, 3, 1, 0, 1}, /* USB_OE */ - {5, 4, 1, 0, 2}, /* USB_TP */ - {5, 5, 1, 0, 2}, /* USB_TN */ - {5, 6, 2, 0, 2}, /* USB_RP */ - {5, 7, 2, 0, 1}, /* USB_RX */ - {5, 8, 2, 0, 1}, /* USB_RN */ - {2, 4, 2, 0, 2}, /* CLK5 */ - - /* SPI Flash, M25P40 */ - {4, 27, 3, 0, 1}, /* SPI_MOSI */ - {4, 28, 3, 0, 1}, /* SPI_MISO */ - {4, 29, 3, 0, 1}, /* SPI_CLK */ - {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */ - - {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ -}; - -void local_bus_init(void); - -int board_early_init_f (void) -{ - /* - * Initialize local bus. - */ - local_bus_init (); - - enable_8569mds_flash_write(); - -#ifdef CONFIG_QE - enable_8569mds_qe_uec(); -#endif - -#if CONFIG_SYS_I2C2_OFFSET - /* Enable I2C2 signals instead of SD signals */ - volatile struct ccsr_gur *gur; - gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); - gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; - gur->plppar1 |= PLPPAR1_I2C2_VAL; - gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; - gur->plpdir1 |= PLPDIR1_I2C2_VAL; - - disable_8569mds_brd_eeprom_write_protect(); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_NAND_BASE; - const u8 flash_esel = 0; - - /* - * Remap Boot flash to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, /* ts, esel */ - BOOKE_PAGESZ_64M, 1); /* tsize, iprot */ - - return 0; -} - -int checkboard (void) -{ - printf ("Board: 8569 MDS\n"); - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -phys_size_t fixed_sdram(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - uint d_init; - - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); -#if defined (CONFIG_DDR_ECC) - out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); - out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); - out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); -#endif - udelay(500); - - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - d_init = 1; - debug("DDR - 1st controller: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); - } - debug("DDR: memory initialized\n\n"); - udelay(500); -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - sys_info_t sysinfo; - - get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - - out_be32(&gur->lbiuiplldcr1, 0x00078080); - if (clkdiv == 16) - out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); - else if (clkdiv == 8) - out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); - else if (clkdiv == 4) - out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); - - out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); -} - -static void fdt_board_disable_serial(void *blob, struct bd_info *bd, - const char *alias) -{ - const char *status = "disabled"; - int off; - int err; - - off = fdt_path_offset(blob, alias); - if (off < 0) { - printf("WARNING: could not find %s alias: %s.\n", alias, - fdt_strerror(off)); - return; - } - - err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); - if (err) { - printf("WARNING: could not set status for serial0: %s.\n", - fdt_strerror(err)); - return; - } -} - -/* - * Because of an erratum in prototype boards it is impossible to use eSDHC - * without disabling UART0 (which makes it quite easy to 'brick' the board - * by simply issung 'setenv hwconfig esdhc', and not able to interact with - * U-Boot anylonger). - * - * So, but default we assume that the board is a prototype, which is a most - * safe assumption. There is no way to determine board revision from a - * register, so we use hwconfig. - */ - -static int prototype_board(void) -{ - if (hwconfig_subarg("board", "rev", NULL)) - return hwconfig_subarg_cmp("board", "rev", "prototype"); - return 1; -} - -static int esdhc_disables_uart0(void) -{ - return prototype_board() || - hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); -} - -static void fdt_board_fixup_qe_uart(void *blob, struct bd_info *bd) -{ - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; - const char *devtype = "serial"; - const char *compat = "ucc_uart"; - const char *clk = "brg9"; - u32 portnum = 0; - int off = -1; - - if (!hwconfig("qe_uart")) - return; - - if (hwconfig("esdhc") && esdhc_disables_uart0()) { - printf("QE UART: won't enable with esdhc.\n"); - return; - } - - fdt_board_disable_serial(blob, bd, "serial1"); - - while (1) { - const u32 *idx; - int len; - - off = fdt_node_offset_by_compatible(blob, off, "ucc_geth"); - if (off < 0) { - printf("WARNING: unable to fixup device tree for " - "QE UART\n"); - return; - } - - idx = fdt_getprop(blob, off, "cell-index", &len); - if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2)) - continue; - break; - } - - fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1); - fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1); - fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1); - fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1); - fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum)); - - setbits_8(&bcsr[15], BCSR15_QEUART_EN); -} - -#ifdef CONFIG_FSL_ESDHC - -int board_mmc_init(struct bd_info *bd) -{ - struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; - u8 bcsr6 = BCSR6_SD_CARD_1BIT; - - if (!hwconfig("esdhc")) - return 0; - - printf("Enabling eSDHC...\n" - " For eSDHC to function, I2C2 "); - if (esdhc_disables_uart0()) { - printf("and UART0 should be disabled.\n"); - printf(" Redirecting stderr, stdout and stdin to UART1...\n"); - console_assign(stderr, "eserial1"); - console_assign(stdout, "eserial1"); - console_assign(stdin, "eserial1"); - printf("Switched to UART1 (initial log has been printed to " - "UART0).\n"); - - clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, - PLPPAR1_ESDHC_4BITS_VAL); - clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, - PLPDIR1_ESDHC_4BITS_VAL); - bcsr6 |= BCSR6_SD_CARD_4BITS; - } else { - printf("should be disabled.\n"); - } - - /* Assign I2C2 signals to eSDHC. */ - clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, - PLPPAR1_ESDHC_VAL); - clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, - PLPDIR1_ESDHC_VAL); - - /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ - setbits_8(&bcsr[6], bcsr6); - - return fsl_esdhc_mmc_init(bd); -} - -static void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd) -{ - const char *status = "disabled"; - int off = -1; - - if (!hwconfig("esdhc")) - return; - - if (esdhc_disables_uart0()) - fdt_board_disable_serial(blob, bd, "serial0"); - - while (1) { - const u32 *idx; - int len; - - off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); - if (off < 0) - break; - - idx = fdt_getprop(blob, off, "cell-index", &len); - if (!idx || len != sizeof(*idx)) - continue; - - if (*idx == 1) { - fdt_setprop(blob, off, "status", status, - strlen(status) + 1); - break; - } - } - - if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { - off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); - if (off < 0) { - printf("WARNING: could not find esdhc node\n"); - return; - } - fdt_delprop(blob, off, "sdhci,1-bit-only"); - } -} -#else -static inline void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd) {} -#endif - -static void fdt_board_fixup_qe_usb(void *blob, struct bd_info *bd) -{ - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; - - if (hwconfig_subarg_cmp("qe_usb", "speed", "low")) - clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); - else - setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); - - if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) { - clrbits_8(&bcsr[17], BCSR17_USBVCC); - clrbits_8(&bcsr[17], BCSR17_USBMODE); - do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode", - "peripheral", sizeof("peripheral"), 1); - } else { - setbits_8(&bcsr[17], BCSR17_USBVCC); - setbits_8(&bcsr[17], BCSR17_USBMODE); - } - - clrbits_8(&bcsr[17], BCSR17_nUSBEN); -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ -#if defined(CONFIG_PQ_MDS_PIB) - pib_init(); -#endif - - fsl_pcie_init_board(0); -} -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ -#if defined(CONFIG_SYS_UCC_RMII_MODE) - int nodeoff, off, err; - unsigned int val; - const u32 *ph; - const u32 *index; - - /* fixup device tree for supporting rmii mode */ - nodeoff = -1; - while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff, - "ucc_geth")) >= 0) { - err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", - "clk16"); - if (err < 0) { - printf("WARNING: could not set tx-clock-name %s.\n", - fdt_strerror(err)); - break; - } - - err = fdt_fixup_phy_connection(blob, nodeoff, - PHY_INTERFACE_MODE_RMII); - - if (err < 0) { - printf("WARNING: could not set phy-connection-type " - "%s.\n", fdt_strerror(err)); - break; - } - - index = fdt_getprop(blob, nodeoff, "cell-index", 0); - if (index == NULL) { - printf("WARNING: could not get cell-index of ucc\n"); - break; - } - - ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); - if (ph == NULL) { - printf("WARNING: could not get phy-handle of ucc\n"); - break; - } - - off = fdt_node_offset_by_phandle(blob, *ph); - if (off < 0) { - printf("WARNING: could not get phy node %s.\n", - fdt_strerror(err)); - break; - } - - val = 0x7 + *index; /* RMII phy address starts from 0x8 */ - - err = fdt_setprop(blob, off, "reg", &val, sizeof(u32)); - if (err < 0) { - printf("WARNING: could not set reg for phy-handle " - "%s.\n", fdt_strerror(err)); - break; - } - } -#endif - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - fdt_board_fixup_esdhc(blob, bd); - fdt_board_fixup_qe_uart(blob, bd); - fdt_board_fixup_qe_usb(blob, bd); - - return 0; -} -#endif diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c deleted file mode 100644 index fdbac54984..0000000000 --- a/board/freescale/mpc8569mds/tlb.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 Initializations */ - /* - * TLBe 0: 64M write-through, guarded - * Out of reset this entry is only 4K. - * 0xfc000000 32MB NAND FLASH (CS3) - * 0xfe000000 32MB NOR FLASH (CS0) - */ -#ifdef CONFIG_NAND_SPL - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), -#endif - /* - * TLBe 1: 256KB Non-cacheable, guarded - * 0xf8000000 32K BCSR - * 0xf8008000 32K PIB (CS4) - * 0xf8010000 32K PIB (CS5) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256K, 1), - - /* - * TLBe 2: 256M Non-cacheable, guarded - * 0xa00000000 256M PCIe MEM (lower half) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLBe 3: 256M Non-cacheable, guarded - * 0xb00000000 256M PCIe MEM (higher half) - */ - SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000), - (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLBe 4: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe280_0000 8M PCIe IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mx23evk/MAINTAINERS b/board/freescale/mx23evk/MAINTAINERS index b03ad6ae0a..122b70cd71 100644 --- a/board/freescale/mx23evk/MAINTAINERS +++ b/board/freescale/mx23evk/MAINTAINERS @@ -1,6 +1,8 @@ MX23EVK BOARD +M: Fabio Estevam <festevam@gmail.com> M: Otavio Salvador <otavio@ossystems.com.br> S: Maintained F: board/freescale/mx23evk/ +F: arch/arm/dts/imx23-evk.dts F: include/configs/mx23evk.h F: configs/mx23evk_defconfig diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c index 605cdec218..df4fb39125 100644 --- a/board/freescale/mx23evk/mx23evk.c +++ b/board/freescale/mx23evk/mx23evk.c @@ -54,26 +54,3 @@ int board_init(void) return 0; } - -#ifdef CONFIG_CMD_MMC -static int mx23evk_mmc_wp(int id) -{ - if (id != 0) { - printf("MXS MMC: Invalid card selected (card id = %d)\n", id); - return 1; - } - - return gpio_get_value(MX23_PAD_PWM4__GPIO_1_30); -} - -int board_mmc_init(struct bd_info *bis) -{ - /* Configure WP as input */ - gpio_direction_input(MX23_PAD_PWM4__GPIO_1_30); - - /* Configure MMC0 Power Enable */ - gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0); - - return mxsmmc_initialize(bis, 0, mx23evk_mmc_wp, NULL); -} -#endif diff --git a/board/freescale/mx25pdk/Kconfig b/board/freescale/mx25pdk/Kconfig deleted file mode 100644 index af06b4c827..0000000000 --- a/board/freescale/mx25pdk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX25PDK - -config SYS_BOARD - default "mx25pdk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx25" - -config SYS_CONFIG_NAME - default "mx25pdk" - -endif diff --git a/board/freescale/mx25pdk/MAINTAINERS b/board/freescale/mx25pdk/MAINTAINERS deleted file mode 100644 index fa4651e2df..0000000000 --- a/board/freescale/mx25pdk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX25PDK BOARD -M: Fabio Estevam <fabio.estevam@nxp.com> -S: Maintained -F: board/freescale/mx25pdk/ -F: include/configs/mx25pdk.h -F: configs/mx25pdk_defconfig diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile deleted file mode 100644 index d3697d3f5f..0000000000 --- a/board/freescale/mx25pdk/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx25pdk.o diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg deleted file mode 100644 index 762ccd0ab3..0000000000 --- a/board/freescale/mx25pdk/imximage.cfg +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -/* EIM config-CS5 init -- CPLD */ -DATA 4 0xB8002050 0x0000D843 -DATA 4 0xB8002054 0x22252521 -DATA 4 0xB8002058 0x22220A00 - -/* DDR2 init */ -DATA 4 0xB8001004 0x0076E83A -DATA 4 0xB8001010 0x00000204 -DATA 4 0xB8001000 0x92210000 -DATA 4 0x80000f00 0x12344321 -DATA 4 0xB8001000 0xB2210000 -DATA 1 0x82000000 0xda -DATA 1 0x83000000 0xda -DATA 1 0x81000400 0xda -DATA 1 0x80000333 0xda - -DATA 4 0xB8001000 0x92210000 -DATA 1 0x80000400 0x12345678 - -DATA 4 0xB8001000 0xA2210000 -DATA 4 0x80000000 0x87654321 -DATA 4 0x80000000 0x87654321 - -DATA 4 0xB8001000 0xB2210000 -DATA 1 0x80000233 0xda -DATA 1 0x81000780 0xda -DATA 1 0x81000400 0xda -DATA 4 0xB8001000 0x82216080 -DATA 4 0x43FAC454 0x00001000 - -DATA 4 0x53F80008 0x20034000 - -/* Enable the clocks */ -DATA 4 0x53f8000c 0x1fffffff -DATA 4 0x53f80010 0xffffffff -DATA 4 0x53f80014 0xfdfff diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c deleted file mode 100644 index 3b445a46dd..0000000000 --- a/board/freescale/mx25pdk/mx25pdk.c +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx25.h> -#include <asm/arch/clock.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <i2c.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <mc34704.h> - -#define FEC_RESET_B IMX_GPIO_NR(4, 8) -#define FEC_ENABLE_B IMX_GPIO_NR(2, 3) -#define CARD_DETECT IMX_GPIO_NR(2, 1) - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {IMX_MMC_SDHC1_BASE}, -}; -#endif - -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define FEC_OUT_PAD_CTRL 0 - -#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_ODE) - -static void mx25pdk_fec_init(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), - - NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */ - NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */ - }; - - static const iomux_v3_cfg_t i2c_pads[] = { - NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* Assert RESET and ENABLE low */ - gpio_direction_output(FEC_RESET_B, 0); - gpio_direction_output(FEC_ENABLE_B, 0); - - udelay(10); - - /* Deassert RESET and ENABLE */ - gpio_set_value(FEC_RESET_B, 1); - gpio_set_value(FEC_ENABLE_B, 1); - - /* Setup I2C pins so that PMIC can turn on PHY supply */ - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -/* - * Set up input pins with hysteresis and 100-k pull-ups - */ -#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define UART1_OUT_PAD_CTRL 0 - -static void mx25pdk_uart1_init(void) -{ - static const iomux_v3_cfg_t uart1_pads[] = { - NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -int board_early_init_f(void) -{ - mx25pdk_uart1_init(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int board_late_init(void) -{ - struct pmic *p; - int ret; - - mx25pdk_fec_init(); - - ret = pmic_init(I2C_0); - if (ret) - return ret; - - p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - - /* Turn on Ethernet PHY and LCD supplies */ - pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA); - - return 0; -} - -#ifdef CONFIG_FSL_ESDHC_IMX -int board_mmc_getcd(struct mmc *mmc) -{ - /* Set up the Card Detect pin. */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0)); - - gpio_direction_input(CARD_DETECT); - return !gpio_get_value(CARD_DETECT); -} - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sdhc1_pads[] = { - NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); - - /* - * Set the eSDHC1 PER clock to the maximum frequency lower than or equal - * to 50 MHz that can be obtained, which requires to use UPLL as the - * clock source. This actually gives 48 MHz. - */ - imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000); - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -int checkboard(void) -{ - puts("Board: MX25PDK\n"); - - return 0; -} - -/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */ -void lowlevel_init(void) {} diff --git a/board/freescale/mx51evk/MAINTAINERS b/board/freescale/mx51evk/MAINTAINERS index 0e5f22c26b..1ca55f7d14 100644 --- a/board/freescale/mx51evk/MAINTAINERS +++ b/board/freescale/mx51evk/MAINTAINERS @@ -1,4 +1,5 @@ MX51EVK BOARD +M: Fabio Estevam <festevam@gmail.com> M: Stefano Babic <sbabic@denx.de> S: Maintained F: board/freescale/mx51evk/ diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index ac48e7668c..c8439a6347 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -27,13 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR}, - {MMC_SDHC2_BASE_ADDR}, -}; -#endif - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -64,34 +57,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), - MX51_PAD_NANDF_CS3__FEC_MDC, - NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), - NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), - NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), - MX51_PAD_NANDF_D9__FEC_RDATA0, - MX51_PAD_NANDF_CS6__FEC_TDATA3, - MX51_PAD_NANDF_CS5__FEC_TDATA2, - MX51_PAD_NANDF_CS4__FEC_TDATA1, - MX51_PAD_NANDF_D8__FEC_TDATA0, - MX51_PAD_NANDF_CS7__FEC_TX_EN, - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, - NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), - NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), - MX51_PAD_EIM_CS5__FEC_CRS, - MX51_PAD_EIM_CS4__FEC_RX_ER, - NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - #ifdef CONFIG_MXC_SPI static void setup_iomux_spi(void) { @@ -112,64 +77,6 @@ static void setup_iomux_spi(void) } #endif -#ifdef CONFIG_USB_EHCI_MX5 -#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7) -#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27) -#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1) -#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5) - -static void setup_usb_h1(void) -{ - static const iomux_v3_cfg_t usb_h1_pads[] = { - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_STP__USBH1_STP, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - - NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */ - MX51_PAD_EIM_D17__GPIO2_1, - MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */ - }; - - imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads)); -} - -int board_ehci_hcd_init(int port) -{ - /* Set USBH1_STP to GPIO and toggle it */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27, - MX51_USBH_PAD_CTRL)); - - gpio_direction_output(MX51EVK_USBH1_STP, 0); - gpio_direction_output(MX51EVK_USB_PHY_RESET, 0); - mdelay(10); - gpio_set_value(MX51EVK_USBH1_STP, 1); - - /* Set back USBH1_STP to be function */ - imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP); - - /* De-assert USB PHY RESETB */ - gpio_set_value(MX51EVK_USB_PHY_RESET, 1); - - /* Drive USB_CLK_EN_B line low */ - gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0); - - /* Reset USB hub */ - gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0); - mdelay(2); - gpio_set_value(MX51EVK_USBH1_HUB_RST, 1); - return 0; -} -#endif - static void power_init(void) { unsigned int val; @@ -258,6 +165,7 @@ static void power_init(void) imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, NO_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14"); gpio_direction_output(IMX_GPIO_NR(2, 14), 0); udelay(500); @@ -265,101 +173,9 @@ static void power_init(void) gpio_set_value(IMX_GPIO_NR(2, 14), 1); } -#ifdef CONFIG_FSL_ESDHC_IMX -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0, - NO_PAD_CTRL)); - gpio_direction_input(IMX_GPIO_NR(1, 0)); - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, - NO_PAD_CTRL)); - gpio_direction_input(IMX_GPIO_NR(1, 6)); - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IMX_GPIO_NR(1, 0)); - else - ret = !gpio_get_value(IMX_GPIO_NR(1, 6)); - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | - PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), - NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), - }; - - static const iomux_v3_cfg_t sd2_pads[] = { - NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD, - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK, - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0, - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1, - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2, - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3, - PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS), - NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS), - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; - index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(sd2_pads, - ARRAY_SIZE(sd2_pads)); - break; - default: - printf("Warning: you configured more ESDHC controller" - "(%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - return 0; -} -#endif - int board_early_init_f(void) { setup_iomux_uart(); - setup_iomux_fec(); -#ifdef CONFIG_USB_EHCI_MX5 - setup_usb_h1(); -#endif setup_iomux_lcd(); return 0; diff --git a/board/freescale/mx53ard/Kconfig b/board/freescale/mx53ard/Kconfig deleted file mode 100644 index 41f46a04ac..0000000000 --- a/board/freescale/mx53ard/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX53ARD - -config SYS_BOARD - default "mx53ard" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "mx53ard" - -endif diff --git a/board/freescale/mx53ard/MAINTAINERS b/board/freescale/mx53ard/MAINTAINERS deleted file mode 100644 index fa81afe9a3..0000000000 --- a/board/freescale/mx53ard/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX53ARD BOARD -M: Fabio Estevam <fabio.estevam@nxp.com> -S: Maintained -F: board/freescale/mx53ard/ -F: include/configs/mx53ard.h -F: configs/mx53ard_defconfig diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile deleted file mode 100644 index e963a24025..0000000000 --- a/board/freescale/mx53ard/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx53ard.o diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg deleted file mode 100644 index fd033187b7..0000000000 --- a/board/freescale/mx53ard/imximage_dd3.cfg +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x53fa8554 0x00300000 -DATA 4 0x53fa8558 0x00300040 -DATA 4 0x53fa8560 0x00300000 -DATA 4 0x53fa8564 0x00300040 -DATA 4 0x53fa8568 0x00300040 -DATA 4 0x53fa8570 0x00300000 -DATA 4 0x53fa8574 0x00300000 -DATA 4 0x53fa8578 0x00300000 -DATA 4 0x53fa857c 0x00300040 -DATA 4 0x53fa8580 0x00300040 -DATA 4 0x53fa8584 0x00300000 -DATA 4 0x53fa8588 0x00300000 -DATA 4 0x53fa8590 0x00300040 -DATA 4 0x53fa8594 0x00300000 -DATA 4 0x53fa86f0 0x00300000 -DATA 4 0x53fa86f4 0x00000000 -DATA 4 0x53fa86fc 0x00000000 -DATA 4 0x53fa8714 0x00000000 -DATA 4 0x53fa8718 0x00300000 -DATA 4 0x53fa871c 0x00300000 -DATA 4 0x53fa8720 0x00300000 -DATA 4 0x53fa8724 0x04000000 -DATA 4 0x53fa8728 0x00300000 -DATA 4 0x53fa872c 0x00300000 -DATA 4 0x63fd9088 0x35343535 -DATA 4 0x63fd9090 0x4d444c44 -DATA 4 0x63fd907c 0x01370138 -DATA 4 0x63fd9080 0x013b013c -DATA 4 0x63fd9018 0x00011740 -DATA 4 0x63fd9000 0xc3190000 -DATA 4 0x63fd900c 0x9f5152e3 -DATA 4 0x63fd9010 0xb68e8a63 -DATA 4 0x63fd9014 0x01ff00db -DATA 4 0x63fd902c 0x000026d2 -DATA 4 0x63fd9030 0x009f0e21 -DATA 4 0x63fd9008 0x12273030 -DATA 4 0x63fd9004 0x0002002d -DATA 4 0x63fd901c 0x00008032 -DATA 4 0x63fd901c 0x00008033 -DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x052080b0 -DATA 4 0x63fd901c 0x04008040 -DATA 4 0x63fd901c 0x0000803a -DATA 4 0x63fd901c 0x0000803b -DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x05208138 -DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00005800 -DATA 4 0x63fd9040 0x05380003 -DATA 4 0x63fd9058 0x00022227 -DATA 4 0x63fd901C 0x00000000 diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c deleted file mode 100644 index f9ec5ca6ef..0000000000 --- a/board/freescale/mx53ard/mx53ard.c +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx53.h> -#include <linux/errno.h> -#include <netdev.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <asm/gpio.h> - -#define ETHERNET_INT IMX_GPIO_NR(2, 31) - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - u32 size1, size2; - - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - gd->ram_size = size1 + size2; - - return 0; -} -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return 0; -} - -#ifdef CONFIG_NAND_MXC -static void setup_iomux_nand(void) -{ - static const iomux_v3_cfg_t nand_pads[] = { - NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, - PAD_CTL_PUS_100K_UP), - NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, - PAD_CTL_PUS_100K_UP), - NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - }; - - u32 i, reg; - - reg = __raw_readl(M4IF_BASE_ADDR + 0xc); - reg &= ~M4IF_GENP_WEIM_MM_MASK; - __raw_writel(reg, M4IF_BASE_ADDR + 0xc); - for (i = 0x4; i < 0x94; i += 0x18) { - reg = __raw_readl(WEIM_BASE_ADDR + i); - reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; - __raw_writel(reg, WEIM_BASE_ADDR + i); - } - - imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); -} -#else -static void setup_iomux_nand(void) -{ -} -#endif - -#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR}, - {MMC_SDHC2_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); - gpio_direction_input(IMX_GPIO_NR(1, 1)); - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4); - gpio_direction_input(IMX_GPIO_NR(1, 4)); - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IMX_GPIO_NR(1, 1)); - else - ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); - - return ret; -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - }; - - static const iomux_v3_cfg_t sd2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL), - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(sd2_pads, - ARRAY_SIZE(sd2_pads)); - break; - default: - printf("Warning: you configured more ESDHC controller" - "(%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - -static void weim_smc911x_iomux(void) -{ - static const iomux_v3_cfg_t weim_smc911x_pads[] = { - /* Data bus */ - NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - - /* Address lines */ - NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH), - - /* other EIM signals for ethernet */ - MX53_PAD_EIM_OE__EMI_WEIM_OE, - MX53_PAD_EIM_RW__EMI_WEIM_RW, - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, - }; - - /* ETHERNET_INT as GPIO2_31 */ - imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31); - gpio_direction_input(ETHERNET_INT); - - /* WEIM bus */ - imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads, - ARRAY_SIZE(weim_smc911x_pads)); -} - -static void weim_cs1_settings(void) -{ - struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; - - writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1); - writel(0x0, &weim_regs->cs1gcr2); - writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1); - writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2); - writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1); - writel(0x0, &weim_regs->cs1wcr2); - writel(0x0, &weim_regs->wcr); - - set_chipselect_size(CS0_64M_CS1_64M); -} - -int board_early_init_f(void) -{ - setup_iomux_nand(); - setup_iomux_uart(); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int rc = -ENODEV; - - weim_smc911x_iomux(); - weim_cs1_settings(); - -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} - -int checkboard(void) -{ - puts("Board: MX53ARD\n"); - - return 0; -} diff --git a/board/freescale/mx53loco/MAINTAINERS b/board/freescale/mx53loco/MAINTAINERS index b4bd1a1842..6c23751877 100644 --- a/board/freescale/mx53loco/MAINTAINERS +++ b/board/freescale/mx53loco/MAINTAINERS @@ -1,4 +1,5 @@ MX53LOCO BOARD +M: Fabio Estevam <festevam@gmail.com> M: Jason Liu <jason.hui.liu@nxp.com> S: Maintained F: board/freescale/mx53loco/ diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index ee54a61d87..0888630569 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -18,10 +18,8 @@ #include <env.h> #include <linux/errno.h> #include <asm/mach-imx/mx5_video.h> -#include <netdev.h> #include <i2c.h> #include <input.h> -#include <mmc.h> #include <fsl_esdhc_imx.h> #include <asm/gpio.h> #include <power/pmic.h> @@ -62,127 +60,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } -#ifdef CONFIG_USB_EHCI_MX5 -int board_ehci_hcd_init(int port) -{ - /* request VBUS power enable pin, GPIO7_8 */ - imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); - gpio_direction_output(IMX_GPIO_NR(7, 8), 1); - return 0; -} -#endif - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), - NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - PAD_CTL_HYS | PAD_CTL_PKE), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR}, - {MMC_SDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); - gpio_direction_input(IMX_GPIO_NR(3, 11)); - imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); - gpio_direction_input(IMX_GPIO_NR(3, 13)); - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); - else - ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); - - return ret; -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - }; - - static const iomux_v3_cfg_t sd2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - MX53_PAD_EIM_DA11__GPIO3_11, - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(sd2_pads, - ARRAY_SIZE(sd2_pads)); - break; - default: - printf("Warning: you configured more ESDHC controller" - "(%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) @@ -327,7 +204,6 @@ static void clock_1GHz(void) int board_early_init_f(void) { setup_iomux_uart(); - setup_iomux_fec(); setup_iomux_lcd(); return 0; diff --git a/board/freescale/mx53smd/Kconfig b/board/freescale/mx53smd/Kconfig deleted file mode 100644 index 1195d33d06..0000000000 --- a/board/freescale/mx53smd/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX53SMD - -config SYS_BOARD - default "mx53smd" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "mx53smd" - -endif diff --git a/board/freescale/mx53smd/MAINTAINERS b/board/freescale/mx53smd/MAINTAINERS deleted file mode 100644 index 17ec376f2a..0000000000 --- a/board/freescale/mx53smd/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX53SMD BOARD -M: Fabio Estevam <fabio.estevam@nxp.com> -S: Maintained -F: board/freescale/mx53smd/ -F: include/configs/mx53smd.h -F: configs/mx53smd_defconfig diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile deleted file mode 100644 index f0347578d5..0000000000 --- a/board/freescale/mx53smd/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx53smd.o diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg deleted file mode 100644 index fd033187b7..0000000000 --- a/board/freescale/mx53smd/imximage.cfg +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x53fa8554 0x00300000 -DATA 4 0x53fa8558 0x00300040 -DATA 4 0x53fa8560 0x00300000 -DATA 4 0x53fa8564 0x00300040 -DATA 4 0x53fa8568 0x00300040 -DATA 4 0x53fa8570 0x00300000 -DATA 4 0x53fa8574 0x00300000 -DATA 4 0x53fa8578 0x00300000 -DATA 4 0x53fa857c 0x00300040 -DATA 4 0x53fa8580 0x00300040 -DATA 4 0x53fa8584 0x00300000 -DATA 4 0x53fa8588 0x00300000 -DATA 4 0x53fa8590 0x00300040 -DATA 4 0x53fa8594 0x00300000 -DATA 4 0x53fa86f0 0x00300000 -DATA 4 0x53fa86f4 0x00000000 -DATA 4 0x53fa86fc 0x00000000 -DATA 4 0x53fa8714 0x00000000 -DATA 4 0x53fa8718 0x00300000 -DATA 4 0x53fa871c 0x00300000 -DATA 4 0x53fa8720 0x00300000 -DATA 4 0x53fa8724 0x04000000 -DATA 4 0x53fa8728 0x00300000 -DATA 4 0x53fa872c 0x00300000 -DATA 4 0x63fd9088 0x35343535 -DATA 4 0x63fd9090 0x4d444c44 -DATA 4 0x63fd907c 0x01370138 -DATA 4 0x63fd9080 0x013b013c -DATA 4 0x63fd9018 0x00011740 -DATA 4 0x63fd9000 0xc3190000 -DATA 4 0x63fd900c 0x9f5152e3 -DATA 4 0x63fd9010 0xb68e8a63 -DATA 4 0x63fd9014 0x01ff00db -DATA 4 0x63fd902c 0x000026d2 -DATA 4 0x63fd9030 0x009f0e21 -DATA 4 0x63fd9008 0x12273030 -DATA 4 0x63fd9004 0x0002002d -DATA 4 0x63fd901c 0x00008032 -DATA 4 0x63fd901c 0x00008033 -DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x052080b0 -DATA 4 0x63fd901c 0x04008040 -DATA 4 0x63fd901c 0x0000803a -DATA 4 0x63fd901c 0x0000803b -DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x05208138 -DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00005800 -DATA 4 0x63fd9040 0x05380003 -DATA 4 0x63fd9058 0x00022227 -DATA 4 0x63fd901C 0x00000000 diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c deleted file mode 100644 index 2f91a0525c..0000000000 --- a/board/freescale/mx53smd/mx53smd.c +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx53.h> -#include <linux/errno.h> -#include <netdev.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <asm/gpio.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - u32 size1, size2; - - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - gd->ram_size = size1 + size2; - - return 0; -} -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return 0; -} - -#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), - NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - PAD_CTL_HYS | PAD_CTL_PKE), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {MMC_SDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); - gpio_direction_input(IMX_GPIO_NR(3, 13)); - return !gpio_get_value(IMX_GPIO_NR(3, 13)); -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - - default: - printf("Warning: you configured more ESDHC controller" - "(%d) as supported by the board(1)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_fec(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int checkboard(void) -{ - puts("Board: MX53SMD\n"); - - return 0; -} diff --git a/board/freescale/qemu-ppce500/Kconfig b/board/freescale/qemu-ppce500/Kconfig deleted file mode 100644 index 236cd17f99..0000000000 --- a/board/freescale/qemu-ppce500/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_QEMU_PPCE500 - -config SYS_BOARD - default "qemu-ppce500" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "qemu-ppce500" - -endif diff --git a/board/freescale/qemu-ppce500/MAINTAINERS b/board/freescale/qemu-ppce500/MAINTAINERS deleted file mode 100644 index 77d0a4a13c..0000000000 --- a/board/freescale/qemu-ppce500/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -QEMU-PPCE500 BOARD -M: Alexander Graf <agraf@suse.de> -S: Maintained -F: board/freescale/qemu-ppce500/ -F: include/configs/qemu-ppce500.h -F: configs/qemu-ppce500_defconfig diff --git a/board/freescale/qemu-ppce500/Makefile b/board/freescale/qemu-ppce500/Makefile deleted file mode 100644 index 817d06d845..0000000000 --- a/board/freescale/qemu-ppce500/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += qemu-ppce500.o diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c deleted file mode 100644 index aa5774fd79..0000000000 --- a/board/freescale/qemu-ppce500/qemu-ppce500.c +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007,2009-2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <cpu_func.h> -#include <env.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <pci.h> -#include <time.h> -#include <asm/global_data.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/fsl_pci.h> -#include <asm/io.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <netdev.h> -#include <fdtdec.h> -#include <errno.h> -#include <malloc.h> - -DECLARE_GLOBAL_DATA_PTR; - -static void *get_fdt_virt(void) -{ - return (void *)CONFIG_SYS_TMPVIRT; -} - -static uint64_t get_fdt_phys(void) -{ - return (uint64_t)(uintptr_t)gd->fdt_blob; -} - -static void map_fdt_as(int esel) -{ - u32 mas0, mas1, mas2, mas3, mas7; - uint64_t fdt_phys = get_fdt_phys(); - unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful; - unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful; - - mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel); - mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); - mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0); - mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb); - - write_tlb(mas0, mas1, mas2, mas3, mas7); -} - -uint64_t get_phys_ccsrbar_addr_early(void) -{ - void *fdt = get_fdt_virt(); - uint64_t r; - int size, node; - u32 naddr; - const fdt32_t *prop; - - /* - * To be able to read the FDT we need to create a temporary TLB - * map for it. - */ - map_fdt_as(10); - node = fdt_path_offset(fdt, "/soc"); - naddr = fdt_address_cells(fdt, node); - prop = fdt_getprop(fdt, node, "ranges", &size); - r = fdt_translate_address(fdt, node, prop + naddr); - disable_tlb(10); - - return r; -} - -int board_early_init_f(void) -{ - return 0; -} - -int checkboard(void) -{ - return 0; -} - -static int pci_map_region(void *fdt, int pci_node, int range_id, - phys_size_t *ppaddr, pci_addr_t *pvaddr, - pci_size_t *psize, ulong *pmap_addr) -{ - uint64_t addr; - uint64_t size; - ulong map_addr; - int r; - - r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size); - if (r) - return r; - - if (ppaddr) - *ppaddr = addr; - if (psize) - *psize = size; - - if (!pmap_addr) - return 0; - - map_addr = *pmap_addr; - - /* Align map_addr */ - map_addr += size - 1; - map_addr &= ~(size - 1); - - if (map_addr + size >= CONFIG_SYS_PCI_MAP_END) - return -1; - - /* Map virtual memory for range */ - assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO)); - *pmap_addr = map_addr + size; - - if (pvaddr) - *pvaddr = map_addr; - - return 0; -} - -void pci_init_board(void) -{ - struct pci_controller *pci_hoses; - void *fdt = get_fdt_virt(); - int pci_node = -1; - int pci_num = 0; - int pci_count = 0; - ulong map_addr; - - puts("\n"); - - /* Start MMIO and PIO range maps above RAM */ - map_addr = CONFIG_SYS_PCI_MAP_START; - - /* Count and allocate PCI buses */ - pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, - "device_type", "pci", 4); - while (pci_node != -FDT_ERR_NOTFOUND) { - pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, - "device_type", "pci", 4); - pci_count++; - } - - if (pci_count) { - pci_hoses = malloc(sizeof(struct pci_controller) * pci_count); - } else { - printf("PCI: disabled\n\n"); - return; - } - - /* Spawn PCI buses based on device tree */ - pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, - "device_type", "pci", 4); - while (pci_node != -FDT_ERR_NOTFOUND) { - struct fsl_pci_info pci_info = { }; - const fdt32_t *reg; - int r; - - reg = fdt_getprop(fdt, pci_node, "reg", NULL); - pci_info.regs = fdt_translate_address(fdt, pci_node, reg); - - /* Map MMIO range */ - r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL, - &pci_info.mem_size, &map_addr); - if (r) - break; - - /* Map PIO range */ - r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL, - &pci_info.io_size, &map_addr); - if (r) - break; - - /* - * The PCI framework finds virtual addresses for the buses - * through our address map, so tell it the physical addresses. - */ - pci_info.mem_bus = pci_info.mem_phys; - pci_info.io_bus = pci_info.io_phys; - - /* Instantiate */ - pci_info.pci_num = pci_num + 1; - - fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs); - printf("PCI: base address %lx\n", pci_info.regs); - - fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num); - - /* Jump to next PCI node */ - pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, - "device_type", "pci", 4); - pci_num++; - } - - puts("\n"); -} - -int last_stage_init(void) -{ - void *fdt = get_fdt_virt(); - int len = 0; - const uint64_t *prop; - int chosen; - - chosen = fdt_path_offset(fdt, "/chosen"); - if (chosen < 0) { - printf("Couldn't find /chosen node in fdt\n"); - return -EIO; - } - - /* -kernel boot */ - prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len); - if (prop && (len >= 8)) - env_set_hex("qemu_kernel_addr", *prop); - - /* Give the user a variable for the host fdt */ - env_set_hex("fdt_addr_r", (ulong)fdt); - - return 0; -} - -static uint64_t get_linear_ram_size(void) -{ - void *fdt = get_fdt_virt(); - const void *prop; - int memory; - int len; - - memory = fdt_path_offset(fdt, "/memory"); - prop = fdt_getprop(fdt, memory, "reg", &len); - - if (prop && len >= 16) - return *(uint64_t *)(prop+8); - - panic("Couldn't determine RAM size"); -} - -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; - - return 0; -} -#endif - -void print_laws(void) -{ - /* We don't emulate LAWs yet */ -} - -phys_size_t fixed_sdram(void) -{ - return get_linear_ram_size(); -} - -phys_size_t fsl_ddr_sdram_size(void) -{ - return get_linear_ram_size(); -} - -void init_tlbs(void) -{ - phys_size_t ram_size; - - /* - * Create a temporary AS=1 map for the fdt - * - * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves - * which was only 4k big. This way we don't have to clear any other maps. - */ - map_fdt_as(0); - - /* Fetch RAM size from the fdt */ - ram_size = get_linear_ram_size(); - - /* And remove our fdt map again */ - disable_tlb(0); - - /* Create an internal map of manually created TLB maps */ - init_used_tlb_cams(); - - /* Create a dynamic AS=0 CCSRBAR mapping */ - assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - 1024 * 1024, TLB_MAP_IO)); - - /* Create a RAM map that spans all accessible RAM */ - setup_ddr_tlbs(ram_size >> 20); - - /* Create a map for the TLB */ - assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(), - 1024 * 1024, TLB_MAP_RAM)); -} - -void init_laws(void) -{ - /* We don't emulate LAWs yet */ -} - -static uint32_t get_cpu_freq(void) -{ - void *fdt = get_fdt_virt(); - int cpus_node = fdt_path_offset(fdt, "/cpus"); - int cpu_node = fdt_first_subnode(fdt, cpus_node); - const char *prop = "clock-frequency"; - return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); -} - -void get_sys_info(sys_info_t *sys_info) -{ - int freq = get_cpu_freq(); - - memset(sys_info, 0, sizeof(sys_info_t)); - sys_info->freq_systembus = freq; - sys_info->freq_ddrbus = freq; - sys_info->freq_processor[0] = freq; -} - -int get_clocks(void) -{ - sys_info_t sys_info; - - get_sys_info(&sys_info); - - gd->cpu_clk = sys_info.freq_processor[0]; - gd->bus_clk = sys_info.freq_systembus; - gd->mem_clk = sys_info.freq_ddrbus; - gd->arch.lbc_clk = sys_info.freq_ddrbus; - - return 0; -} - -unsigned long get_tbclk(void) -{ - void *fdt = get_fdt_virt(); - int cpus_node = fdt_path_offset(fdt, "/cpus"); - int cpu_node = fdt_first_subnode(fdt, cpus_node); - const char *prop = "timebase-frequency"; - return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); -} - -/******************************************** - * get_bus_freq - * return system bus freq in Hz - *********************************************/ -ulong get_bus_freq(ulong dummy) -{ - sys_info_t sys_info; - get_sys_info(&sys_info); - return sys_info.freq_systembus; -} - -/* - * Return the number of cores on this SOC. - */ -int cpu_numcores(void) -{ - /* - * The QEMU u-boot target only needs to drive the first core, - * spinning and device tree nodes get driven by QEMU itself - */ - return 1; -} - -/* - * Return a 32-bit mask indicating which cores are present on this SOC. - */ -u32 cpu_mask(void) -{ - return (1 << cpu_numcores()) - 1; -} |