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-rw-r--r--board/freescale/common/sys_eeprom.c8
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c3
-rw-r--r--board/freescale/ls1021atwr/ls1021atwr.c3
-rw-r--r--board/freescale/ls2085a/README11
-rw-r--r--board/freescale/ls2085a/ls2085a.c17
-rw-r--r--board/freescale/ls2085aqds/README19
-rw-r--r--board/freescale/ls2085aqds/eth.c4
-rw-r--r--board/freescale/ls2085aqds/ls2085aqds.c71
-rw-r--r--board/freescale/ls2085ardb/Makefile2
-rw-r--r--board/freescale/ls2085ardb/README11
-rw-r--r--board/freescale/ls2085ardb/eth_ls2085rdb.c148
-rw-r--r--board/freescale/ls2085ardb/ls2085ardb.c111
12 files changed, 365 insertions, 43 deletions
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 5cb7570c8b..29aa778dbe 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -90,7 +90,7 @@ static void show_eeprom(void)
/* EEPROM tag ID, either CCID or NXID */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
- e.version);
+ be32_to_cpu(e.version));
#else
printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
#endif
@@ -340,7 +340,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (cmd == 'i') {
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
memcpy(e.id, "NXID", sizeof(e.id));
- e.version = NXID_VERSION;
+ e.version = cpu_to_be32(NXID_VERSION);
#else
memcpy(e.id, "CCID", sizeof(e.id));
#endif
@@ -485,7 +485,7 @@ int mac_read_from_eeprom(void)
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
- e.version);
+ be32_to_cpu(e.version));
#else
printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
#endif
@@ -496,7 +496,7 @@ int mac_read_from_eeprom(void)
* that at boot time, U-Boot will still say "NXID v0".
*/
if (e.version == 0) {
- e.version = NXID_VERSION;
+ e.version = cpu_to_be32(NXID_VERSION);
update_crc();
}
#endif
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 92f613ad24..ce5cb52c11 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -209,6 +209,9 @@ int board_early_init_f(void)
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
+ /* Configure Little endian for SAI, ASRC and SPDIF */
+ out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
+
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A7 core cluster)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 043d9383c4..8fef8e9662 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -368,6 +368,9 @@ int board_early_init_f(void)
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /* Configure Little endian for SAI, ASRC and SPDIF */
+ out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
+
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A7 core cluster)
diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README
index b7023e1d48..bc1d0bb4a7 100644
--- a/board/freescale/ls2085a/README
+++ b/board/freescale/ls2085a/README
@@ -14,3 +14,14 @@ Memory map from core's view
Other addresses are either reserved, or not used directly by u-boot.
This list should be updated when more addresses are used.
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+ earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+ hugepages=16 mem=2048M'
+
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index dd0acf23b2..73c44102c4 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -80,7 +80,7 @@ unsigned long get_dram_size_to_hide(void)
dram_to_hide += mc_get_dram_block_size();
#endif
- return dram_to_hide;
+ return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
}
int board_eth_init(bd_t *bis)
@@ -127,15 +127,18 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
- phys_addr_t base;
- phys_size_t size;
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
ft_cpu_setup(blob, bd);
- /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
- base = getenv_bootm_low();
- size = getenv_bootm_size();
- fdt_fixup_memory(blob, (u64)base, (u64)size);
+ /* fixup DT for the two GPP DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README
index fb3938e673..11b2e79945 100644
--- a/board/freescale/ls2085aqds/README
+++ b/board/freescale/ls2085aqds/README
@@ -127,3 +127,22 @@ b) NOR boot
c) NAND boot
d) SD boot
e) QSPI boot
+
+Environment Variables
+---------------------
+- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
+ the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+- mcmemsize: MC DRAM block size. If this variable is not defined
+ the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+ earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+ hugepages=16 mem=2048M'
+
diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
index 5ba4770ebc..1f8a31ff00 100644
--- a/board/freescale/ls2085aqds/eth.c
+++ b/board/freescale/ls2085aqds/eth.c
@@ -53,7 +53,7 @@ static int riser_phy_addr[] = {
#define EMI1_SLOT5 4
#define EMI1_SLOT6 5
#define EMI2 6
-#define SFP_TX 1
+#define SFP_TX 0
static const char * const mdio_names[] = {
"LS2085A_QDS_MDIO0",
@@ -210,6 +210,7 @@ static void initialize_dpmac_to_slot(void)
switch (serdes2_prtcl) {
case 0x07:
case 0x08:
+ case 0x49:
printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
serdes2_prtcl);
lane_to_slot_fsm2[0] = EMI1_SLOT4;
@@ -247,6 +248,7 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
switch (serdes2_prtcl) {
case 0x07:
case 0x08:
+ case 0x49:
lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
(dpmac_id - 9));
slot = lane_to_slot_fsm2[lane];
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
index 6a22122ca0..08906a6255 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -17,12 +17,23 @@
#include <environment.h>
#include <i2c.h>
#include <asm/arch-fsl-lsch3/soc.h>
+#include <hwconfig.h>
#include "../common/qixis.h"
#include "ls2085aqds_qixis.h"
+#define PIN_MUX_SEL_SDHC 0x00
+#define PIN_MUX_SEL_DSPI 0x0a
+
+#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
+
DECLARE_GLOBAL_DATA_PTR;
+enum {
+ MUX_TYPE_SDHC,
+ MUX_TYPE_DSPI,
+};
+
unsigned long long get_qixis_addr(void)
{
unsigned long long addr;
@@ -49,11 +60,15 @@ int checkboard(void)
"100 separate SSCG"};
int clock;
+ cpu_name(buf);
+ printf("Board: %s-QDS, ", buf);
+
sw = QIXIS_READ(arch);
- printf("Board: %s, ", CONFIG_IDENT_STRING);
printf("Board Arch: V%d, ", sw >> 4);
printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+ memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
+
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -149,10 +164,47 @@ int select_i2c_ch_pca9547(u8 ch)
return 0;
}
+int config_board_mux(int ctrl_type)
+{
+ u8 reg5;
+
+ reg5 = QIXIS_READ(brdcfg[5]);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_SDHC:
+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+ break;
+ case MUX_TYPE_DSPI:
+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+ break;
+ default:
+ printf("Wrong mux interface type\n");
+ return -1;
+ }
+
+ QIXIS_WRITE(brdcfg[5], reg5);
+
+ return 0;
+}
+
int board_init(void)
{
+ char *env_hwconfig;
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 val;
+
init_final_memctl_regs();
+ val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+ env_hwconfig = getenv("hwconfig");
+
+ if (hwconfig_f("dspi", env_hwconfig) &&
+ DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+ config_board_mux(MUX_TYPE_DSPI);
+ else
+ config_board_mux(MUX_TYPE_SDHC);
+
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
@@ -211,7 +263,7 @@ unsigned long get_dram_size_to_hide(void)
dram_to_hide += mc_get_dram_block_size();
#endif
- return dram_to_hide;
+ return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
}
#ifdef CONFIG_FSL_MC_ENET
@@ -240,15 +292,18 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
- phys_addr_t base;
- phys_size_t size;
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
ft_cpu_setup(blob, bd);
- /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
- base = getenv_bootm_low();
- size = getenv_bootm_size();
- fdt_fixup_memory(blob, (u64)base, (u64)size);
+ /* fixup DT for the two GPP DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile
index 0bfe21c1d8..de383ccc0f 100644
--- a/board/freescale/ls2085ardb/Makefile
+++ b/board/freescale/ls2085ardb/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += ls2085ardb.o
+obj-y += ls2085ardb.o eth_ls2085rdb.o
obj-y += ddr.o
diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README
index cfd5185f46..2f18243a8b 100644
--- a/board/freescale/ls2085ardb/README
+++ b/board/freescale/ls2085ardb/README
@@ -107,3 +107,14 @@ Booting Options
---------------
a) NOR boot
b) NAND boot
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+ earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+ hugepages=16 mem=2048M'
+
diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c
new file mode 100644
index 0000000000..0a1163ab8e
--- /dev/null
+++ b/board/freescale/ls2085ardb/eth_ls2085rdb.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int load_firmware_cortina(struct phy_device *phy_dev)
+{
+ if (phy_dev->drv->config)
+ return phy_dev->drv->config(phy_dev);
+
+ return 0;
+}
+
+void load_phy_firmware(void)
+{
+ int i;
+ u8 phy_addr;
+ struct phy_device *phy_dev;
+ struct mii_dev *dev;
+ phy_interface_t interface;
+
+ /*Initialize and upload firmware for all the PHYs*/
+ for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
+ interface = wriop_get_enet_if(i);
+ if (interface == PHY_INTERFACE_MODE_XGMII) {
+ dev = wriop_get_mdio(i);
+ phy_addr = wriop_get_phy_address(i);
+ phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
+ interface);
+ if (!phy_dev) {
+ printf("No phydev for phyaddr %d\n", phy_addr);
+ continue;
+ }
+
+ /*Flash firmware for All CS4340 PHYS */
+ if (phy_dev->phy_id == PHY_UID_CS4340)
+ load_firmware_cortina(phy_dev);
+ }
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ int i, interface;
+ struct memac_mdio_info mdio_info;
+ struct mii_dev *dev;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+ struct memac_mdio_controller *reg;
+
+ srds_s1 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /* Register the EMI 1 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+ /* Register the EMI 2 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ switch (srds_s1) {
+ case 0x2A:
+ wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+ wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+
+ break;
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
+ interface = wriop_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
+ switch (wriop_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Load CORTINA CS4340 PHY firmware */
+ load_phy_firmware();
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+#ifdef CONFIG_PHY_AQUANTIA
+ /*
+ * Export functions to be used by AQ firmware
+ * upload application
+ */
+ gd->jt->strcpy = strcpy;
+ gd->jt->mdelay = mdelay;
+ gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+ gd->jt->phy_find_by_mask = phy_find_by_mask;
+ gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+ gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index d05f2bc581..5e7997c869 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -10,6 +10,7 @@
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/io.h>
+#include <hwconfig.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl_debug_server.h>
@@ -21,8 +22,17 @@
#include "../common/qixis.h"
#include "ls2085ardb_qixis.h"
+#define PIN_MUX_SEL_SDHC 0x00
+#define PIN_MUX_SEL_DSPI 0x0a
+
+#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
DECLARE_GLOBAL_DATA_PTR;
+enum {
+ MUX_TYPE_SDHC,
+ MUX_TYPE_DSPI,
+};
+
unsigned long long get_qixis_addr(void)
{
unsigned long long addr;
@@ -44,11 +54,14 @@ unsigned long long get_qixis_addr(void)
int checkboard(void)
{
u8 sw;
+ char buf[15];
+
+ cpu_name(buf);
+ printf("Board: %s-RDB, ", buf);
sw = QIXIS_READ(arch);
- printf("Board: %s, ", CONFIG_IDENT_STRING);
printf("Board Arch: V%d, ", sw >> 4);
- printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -109,10 +122,47 @@ int select_i2c_ch_pca9547(u8 ch)
return 0;
}
+int config_board_mux(int ctrl_type)
+{
+ u8 reg5;
+
+ reg5 = QIXIS_READ(brdcfg[5]);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_SDHC:
+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+ break;
+ case MUX_TYPE_DSPI:
+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+ break;
+ default:
+ printf("Wrong mux interface type\n");
+ return -1;
+ }
+
+ QIXIS_WRITE(brdcfg[5], reg5);
+
+ return 0;
+}
+
int board_init(void)
{
+ char *env_hwconfig;
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 val;
+
init_final_memctl_regs();
+ val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+ env_hwconfig = getenv("hwconfig");
+
+ if (hwconfig_f("dspi", env_hwconfig) &&
+ DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+ config_board_mux(MUX_TYPE_DSPI);
+ else
+ config_board_mux(MUX_TYPE_SDHC);
+
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
@@ -129,6 +179,14 @@ int board_early_init_f(void)
return 0;
}
+int misc_init_r(void)
+{
+ if (hwconfig("sdhc"))
+ config_board_mux(MUX_TYPE_SDHC);
+
+ return 0;
+}
+
void detail_board_ddr_info(void)
{
puts("\nDDR ");
@@ -173,20 +231,7 @@ unsigned long get_dram_size_to_hide(void)
dram_to_hide += mc_get_dram_block_size();
#endif
- return dram_to_hide;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int error = 0;
-
-#ifdef CONFIG_FSL_MC_ENET
- error = cpu_eth_init(bis);
-#endif
-
- error = pci_eth_init(bis);
-
- return error;
+ return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
}
#ifdef CONFIG_FSL_MC_ENET
@@ -215,15 +260,18 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
- phys_addr_t base;
- phys_size_t size;
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
ft_cpu_setup(blob, bd);
- /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
- base = getenv_bootm_low();
- size = getenv_bootm_size();
- fdt_fixup_memory(blob, (u64)base, (u64)size);
+ /* fixup DT for the two GPP DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
@@ -247,3 +295,22 @@ void qixis_dump_switch(void)
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
}
}
+
+/*
+ * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
+ * Both slots has 0x54, resulting 2nd slot unusable.
+ */
+void update_spd_address(unsigned int ctrl_num,
+ unsigned int slot,
+ unsigned int *addr)
+{
+ u8 sw;
+
+ sw = QIXIS_READ(arch);
+ if ((sw & 0xf) < 0x3) {
+ if (ctrl_num == 1 && slot == 0)
+ *addr = SPD_EEPROM_ADDRESS4;
+ else if (ctrl_num == 1 && slot == 1)
+ *addr = SPD_EEPROM_ADDRESS3;
+ }
+}
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 12:39:43 +0000