diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/lib/crt0_aarch64_efi.S | 3 | ||||
| -rw-r--r-- | arch/sandbox/cpu/os.c | 25 | ||||
| -rw-r--r-- | arch/sandbox/cpu/start.c | 2 | ||||
| -rw-r--r-- | arch/sandbox/dts/sandbox.dtsi | 10 | ||||
| -rw-r--r-- | arch/sandbox/dts/test.dts | 10 | ||||
| -rw-r--r-- | arch/sandbox/include/asm/test.h | 15 | ||||
| -rw-r--r-- | arch/x86/cpu/i386/cpu.c | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/start.S | 2 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 21 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/iomap.h | 3 |
10 files changed, 85 insertions, 8 deletions
diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S index 368933ecf2..492195f765 100644 --- a/arch/arm/lib/crt0_aarch64_efi.S +++ b/arch/arm/lib/crt0_aarch64_efi.S @@ -18,7 +18,8 @@ .globl ImageBase ImageBase: .short IMAGE_DOS_SIGNATURE /* 'MZ' */ - .skip 58 /* 'MZ' + pad + offset == 64 */ + .skip 54 /* 'MZ' + pad + offset == 64 */ + .long LINUX_ARM64_MAGIC /* For GRUB's linux command */ .long pe_header - ImageBase /* Offset to the PE header */ pe_header: .long IMAGE_NT_SIGNATURE /* 'PE' */ diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 80996a91ce..3d8af0a52b 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -32,6 +32,9 @@ #include <os.h> #include <rtc_def.h> +/* Environment variable for time offset */ +#define ENV_TIME_OFFSET "UBOOT_SB_TIME_OFFSET" + /* Operating System Interface */ struct os_mem_hdr { @@ -798,6 +801,28 @@ int os_spl_to_uboot(const char *fname) return os_jump_to_file(fname); } +long os_get_time_offset(void) +{ + const char *offset; + + offset = getenv(ENV_TIME_OFFSET); + if (offset) + return strtol(offset, NULL, 0); + return 0; +} + +void os_set_time_offset(long offset) +{ + char buf[21]; + int ret; + + snprintf(buf, sizeof(buf), "%ld", offset); + ret = setenv(ENV_TIME_OFFSET, buf, true); + if (ret) + printf("Could not set environment variable %s\n", + ENV_TIME_OFFSET); +} + void os_localtime(struct rtc_time *rt) { time_t t = time(NULL); diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 2d18d9debc..2542580974 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -215,7 +215,7 @@ static int sandbox_cmdline_cb_test_fdt(struct sandbox_state *state, if (!p) p = fname + strlen(fname); len -= p - fname; - snprintf(p, len, fmt, p); + snprintf(p, len, fmt); state->fdt_fname = fname; return 0; diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index d842f02176..dc933f3bfc 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -260,10 +260,14 @@ stringarray = "pre-proper"; }; - spl-test7 { + test-bus { + compatible = "simple-bus"; u-boot,dm-spl; - compatible = "sandbox,spl-test"; - stringarray = "spl"; + spl-test7 { + u-boot,dm-spl; + compatible = "sandbox,spl-test"; + stringarray = "spl"; + }; }; square { diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index f86cd0d3b2..e95f4631bf 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -90,6 +90,16 @@ wp-ro { image-pos = <0xf000>; size = <0x1000>; + used = <0x884>; + compress = "lz4"; + uncomp-size = <0xcf8>; + hash { + algo = "sha256"; + value = [00 01 02 03 04 05 06 07 + 08 09 0a 0b 0c 0d 0e 0f + 10 11 12 13 14 15 16 17 + 18 19 1a 1b 1c 1d 1e 1f]; + }; }; rw { image-pos = <0x10000>; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 05f66f700c..1cb960ac24 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -58,6 +58,13 @@ enum { }; /** + */ +enum cros_ec_test_t { + CROSECT_BREAK_HELLO = BIT(1), + CROSECT_LID_OPEN = BIT(2), +}; + +/** * sandbox_i2c_set_test_mode() - set test mode for running unit tests * * See sandbox_i2c_xfer() for the behaviour changes. @@ -260,4 +267,12 @@ uint sandbox_pci_read_bar(u32 barval, int type, uint size); */ void sandbox_set_enable_memio(bool enable); +/** + * sandbox_cros_ec_set_test_flags() - Set behaviour for testing purposes + * + * @dev: Device to check + * @flags: Flags to control behaviour (CROSECT_...) + */ +void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags); + #endif diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 7517b756f4..6fa0f4d32b 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -175,7 +175,7 @@ void arch_setup_gd(gd_t *new_gd) * Per Intel FSP external architecture specification, before calling any FSP * APIs, we need make sure the system is in flat 32-bit mode and both the code * and data selectors should have full 4GB access range. Here we reuse the one - * we used in arch/x86/cpu/start16.S, and reload the segement registers. + * we used in arch/x86/cpu/start16.S, and reload the segment registers. */ void setup_fsp_gdt(void) { diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 3b6ed37bc0..3d0d95295f 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -77,7 +77,7 @@ _start: lgdt gdt_ptr2 #endif - /* Load the segement registers to match the GDT loaded in start16.S */ + /* Load the segment registers to match the GDT loaded in start16.S */ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax movw %ax, %fs movw %ax, %ds diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index a846022095..9319123c0c 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/x86-gpio.h> /include/ "skeleton.dtsi" @@ -99,6 +100,7 @@ clk: clock { compatible = "intel,apl-clk"; #clock-cells = <1>; + u-boot,dm-pre-reloc; }; cpus { @@ -139,6 +141,7 @@ }; acpi_gpe: general-purpose-events { + u-boot,dm-pre-reloc; reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>; compatible = "intel,acpi-gpe"; interrupt-controller; @@ -417,8 +420,10 @@ }; i2c_2: i2c2@16,2 { - compatible = "intel,apl-i2c"; + compatible = "intel,apl-i2c", "snps,designware-i2c-pci"; reg = <0x0200b210 0 0 0 0>; + early-regs = <IOMAP_I2C2_BASE 0x1000>; + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; @@ -429,6 +434,7 @@ tpm: tpm@50 { reg = <0x50>; compatible = "google,cr50"; + u-boot,dm-pre-reloc; u-boot,i2c-offset-len = <0>; ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; interrupts-extended = <&acpi_gpe GPIO_28_IRQ @@ -583,6 +589,7 @@ u-boot,dm-pre-reloc; cros_ec: cros-ec { u-boot,dm-pre-proper; + u-boot,dm-vpl; compatible = "google,cros-ec-lpc"; reg = <0x204 1 0x200 1 0x880 0x80>; @@ -637,6 +644,7 @@ PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC | PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT) (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE) + PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */ /* * WLAN_PE_RST - default to deasserted just in case FSP @@ -657,6 +665,11 @@ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ + + PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ + PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ >; }; @@ -1210,3 +1223,9 @@ PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */ >; }; + +&rtc { + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h index 21c5f33021..a4ea150707 100644 --- a/arch/x86/include/asm/arch-apollolake/iomap.h +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -33,6 +33,9 @@ #define SRAM_SIZE_2 (4 * KiB) #endif +/* Early address for I2C port 2 */ +#define IOMAP_I2C2_BASE (0xfe020000 + 2 * 0x1000) + /* * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE. |