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-rw-r--r--arch/arm/cpu/armv7/ls102xa/fdt.c6
-rw-r--r--arch/arm/dts/armada-3720-espressobin.dts21
-rw-r--r--arch/arm/dts/armada-3720-turris-mox.dts25
-rw-r--r--arch/arm/dts/armada-3720-uDPU.dts23
-rw-r--r--arch/arm/dts/armada-37xx.dtsi20
-rw-r--r--arch/arm/dts/armada-xp-theadorable.dts12
-rw-r--r--arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c41
-rw-r--r--arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h2
-rw-r--r--arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c17
-rw-r--r--arch/arm/mach-mvebu/spl.c17
10 files changed, 95 insertions, 89 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 0daf8234fb..bf6cc6d4e7 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -184,13 +184,13 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
CONFIG_SYS_IFC_ADDR);
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
QSPI0_BASE_ADDR);
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
DSPI1_BASE_ADDR);
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#endif
}
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
index cba6139be6..360d521bba 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -80,24 +80,6 @@
};
};
-&comphy {
- max-lanes = <3>;
- phy0 {
- phy-type = <COMPHY_TYPE_USB3_HOST0>;
- phy-speed = <COMPHY_SPEED_5G>;
- };
-
- phy1 {
- phy-type = <COMPHY_TYPE_PEX0>;
- phy-speed = <COMPHY_SPEED_2_5G>;
- };
-
- phy2 {
- phy-type = <COMPHY_TYPE_SATA0>;
- phy-speed = <COMPHY_SPEED_5G>;
- };
-};
-
&eth0 {
status = "okay";
pinctrl-names = "default";
@@ -119,6 +101,7 @@
/* CON3 */
&sata {
status = "okay";
+ phys = <&comphy2 0>;
};
&sdhci0 {
@@ -200,6 +183,7 @@
/* CON31 */
&usb3 {
status = "okay";
+ phys = <&comphy0 0>;
};
&pcie0 {
@@ -207,4 +191,5 @@
pinctrl-0 = <&pcie_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
+ phys = <&comphy1 0>;
};
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts
index f47ced05c5..d01757062f 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -94,24 +94,6 @@
};
};
-&comphy {
- max-lanes = <3>;
- phy0 {
- phy-type = <COMPHY_TYPE_SGMII1>;
- phy-speed = <COMPHY_SPEED_3_125G>;
- };
-
- phy1 {
- phy-type = <COMPHY_TYPE_PEX0>;
- phy-speed = <COMPHY_SPEED_5G>;
- };
-
- phy2 {
- phy-type = <COMPHY_TYPE_USB3_HOST0>;
- phy-speed = <COMPHY_SPEED_5G>;
- };
-};
-
&eth0 {
status = "okay";
pinctrl-names = "default";
@@ -120,6 +102,11 @@
phy = <&eth_phy1>;
};
+&eth1 {
+ phy-mode = "2500base-x";
+ phys = <&comphy0 1>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -222,6 +209,7 @@
&usb3 {
vbus-supply = <&reg_usb3_vbus>;
status = "okay";
+ phys = <&comphy2 0>;
};
&pcie0 {
@@ -229,4 +217,5 @@
pinctrl-0 = <&pcie_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "disabled";
+ phys = <&comphy1 0>;
};
diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts
index 4bf6d2eac7..58557c680a 100644
--- a/arch/arm/dts/armada-3720-uDPU.dts
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -106,36 +106,21 @@
};
};
-&comphy {
- phy0 {
- phy-type = <COMPHY_TYPE_SGMII1>;
- phy-speed = <COMPHY_SPEED_1_25G>;
- };
-
- phy1 {
- phy-type = <COMPHY_TYPE_SGMII0>;
- phy-speed = <COMPHY_SPEED_1_25G>;
- };
-
- phy2 {
- phy-type = <COMPHY_TYPE_USB3_HOST1>;
- phy-speed = <COMPHY_SPEED_5G>;
- };
-};
-
&eth0 {
pinctrl-0 = <&pcie_pins>;
status = "okay";
- phy-mode = "2500base-x";
+ phy-mode = "sgmii";
managed = "in-band-status";
phy = <&ethphy0>;
+ phys = <&comphy1 0>;
};
&eth1 {
status = "okay";
- phy-mode = "2500base-x";
+ phy-mode = "sgmii";
managed = "in-band-status";
phy = <&ethphy1>;
+ phys = <&comphy0 1>;
};
&i2c0 {
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index fec34609cf..bef6ef03df 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -316,9 +316,23 @@
compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
reg = <0x18300 0x28>,
<0x1f300 0x3d000>;
- mux-bitcount = <4>;
- mux-lane-order = <1 0 2>;
- max-lanes = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ comphy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ comphy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ comphy2: phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
};
};
diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts
index 6a1df870ab..24cc1cc527 100644
--- a/arch/arm/dts/armada-xp-theadorable.dts
+++ b/arch/arm/dts/armada-xp-theadorable.dts
@@ -71,6 +71,8 @@
spi0 = &spi0;
spi1 = &spi1;
ethernet0 = &eth0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
};
memory {
@@ -156,6 +158,16 @@
};
};
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
&spi0 {
status = "okay";
u-boot,dm-pre-reloc;
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index d2bc3ab25c..9ba60b57aa 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -459,18 +459,41 @@ struct op_params usb3_electrical_config_serdes_rev1_params[] = {
};
struct op_params usb3_electrical_config_serdes_rev2_params[] = {
- /* Spread Spectrum Clock Enable */
- {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
+ /* Spread Spectrum Clock Enable, CFG_DFE_OVERRIDE and PIN_DFE_PAT_DIS */
+ {LANE_CFG4_REG, 0x800, 0xc2, {0xc0}, 0, 0},
+ /* CFG_SQ_DET_SEL and CFG_RX_INIT_SEL */
+ {LANE_CFG5_REG, 0x800, 0x3, {0x3}, 0, 0},
/* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
{G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
- /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
+ /* FFE Setting Force, FFE_RES[2:0]=0x6 and FFE_CAP[3:0]=0xf */
+ {G2_SETTINGS_3_REG, 0x800, 0xff, {0xef}, 0, 0},
+ /* G2_DFE_RES[1:0]=0x0(3mV)*/
+ {G2_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
+ /* HPF_Bw[1:0]=0x3 */
+ {PLLINTP_REG1, 0x800, 0x300, {0x300}, 0, 0},
+ /* TXIMPCAL_TH[3:0]=0x3, RXIMPCAL_TH[3:0]=0x0 */
+ {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
+ /* CFG_SQ_DET_SEL and CFG_RX_INIT_SEL*/
+ {LANE_CFG5_REG, 0x800, 0x3, {0x3}, 0, 0},
+ /* REFCLK_SEL(25Mhz), ICP_FORCE, ICP[3:0]=0xa(210uA); */
+ {MISC_REG, 0x800, 0x42f, {0x42a}, 0, 0},
+ /* REF_FREF_SEL[4:0]=0x2(25Mhz) */
+ {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x02}, 0, 0},
+ /*
+ * G2_RX SELMUFF[1:0]=3, G2_RX_SELMUFI[1:0]=3, G2_RX_SELMUPF[2:0]=2
+ * and G2_RX_SELMUPI[2:0]=2
+ */
{G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
/* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
{RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
+ /* tx_amp_pipe_v0[4:0]=0x1a */
+ {PCIE_REG1, 0x800, 0xf80, {0xd00}, 0, 0},
/* vco_cal_vth_sel */
{REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
- /* Spread Spectrum Clock Enable */
- {LANE_CFG5_REG, 0x800, 0x4, {0x4}, 0, 0},
+ /* PRD_TXDEEMPH0 */
+ {LANE_CFG0_REG, 0x800, 0x1, {0x1}, 0, 0},
+ /* MODE_MARGIN_OVERRIDE */
+ {GLOBAL_TEST_CTRL, 0x800, 0x4, {0x4}, 0, 0},
};
/* PEX and USB3 - TX config seq */
@@ -490,11 +513,11 @@ struct op_params pex_and_usb3_tx_config_params1[] = {
/* 10ms delay */
{0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0},
/* os_ph_offset_force (align 90) */
- {RX_REG3, 0x800, 0xff, {0xdc, NO_DATA}, 0, 0},
+ {RX_REG3, 0x800, 0xff, {0xdc, 0xd8}, 0, 0},
/* Set os_ph_valid */
- {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
+ {RX_REG3, 0x800, 0x100, {0x100, 0x100}, 0, 0},
/* Unset os_ph_valid */
- {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
+ {RX_REG3, 0x800, 0x100, {0x0, 0x0}, 0, 0},
};
struct op_params pex_and_usb3_tx_config_params2[] = {
@@ -1204,7 +1227,7 @@ int hws_serdes_seq_db_init(void)
sizeof(usb3_electrical_config_serdes_rev2_params) /
sizeof(struct op_params);
}
- serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3;
+ serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = 0;
/* USB3_TX_CONFIG_SEQ sequence init */
serdes_seq_db[USB3_TX_CONFIG_SEQ1].op_params_ptr =
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
index 118bf56602..94c43b4daf 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
@@ -50,6 +50,7 @@
#define MISC_REG 0xa013c
#define GLUE_REG 0xa0140
#define GENERATION_DIVIDER_FORCE_REG 0xa0144
+#define PLLINTP_REG1 0xa0150
#define PCIE_REG0 0xa0120
#define LANE_ALIGN_REG0 0xa0124
#define SQUELCH_FFE_SETTING_REG 0xa0018
@@ -78,6 +79,7 @@
#define LANE_CFG4_REG 0xa0620
#define LANE_CFG5_REG 0xa0624
#define GLOBAL_CLK_CTRL 0xa0704
+#define GLOBAL_TEST_CTRL 0xa0708
#define GLOBAL_MISC_CTRL 0xa0718
#define GLOBAL_CLK_SRC_HI 0xa0710
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
index ea3b4c7d5b..0b63664dd8 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
@@ -77,6 +77,7 @@ static u32 board_id_get(void)
__weak u8 board_sat_r_get(u8 dev_num, u8 reg)
{
+ struct udevice *udev;
u8 data;
u8 *dev;
u32 board_id = board_id_get();
@@ -107,8 +108,11 @@ __weak u8 board_sat_r_get(u8 dev_num, u8 reg)
}
/* Read MPP module ID */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
+ ret = i2c_get_chip_for_busnum(0, dev[dev_num], 1, &udev);
+ if (ret)
+ return MV_ERROR;
+
+ ret = dm_i2c_read(udev, 0, &data, 1);
if (ret)
return MV_ERROR;
@@ -124,13 +128,18 @@ static int board_modules_scan(void)
/* Perform scan only for DB board */
if ((board_id == DB_88F78XX0_BP_ID) ||
(board_id == DB_88F78XX0_BP_REV2_ID)) {
+ struct udevice *udev;
+
/* reset modules flags */
config_module = 0;
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ ret = i2c_get_chip_for_busnum(0, MV_BOARD_PEX_MODULE_ADDR,
+ 1, &udev);
+ if (ret)
+ return MV_ERROR;
/* SERDES module (only PEX model is supported now) */
- ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
+ ret = dm_i2c_read(udev, 0, &val, 1);
if (ret)
return MV_ERROR;
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 73c4b9af3e..aada83f190 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -5,7 +5,6 @@
#include <common.h>
#include <dm.h>
-#include <debug_uart.h>
#include <fdtdec.h>
#include <hang.h>
#include <image.h>
@@ -250,18 +249,6 @@ void board_init_f(ulong dummy)
*/
board_early_init_f();
- /* Example code showing how to enable the debug UART on MVEBU */
-#ifdef EARLY_UART
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
-#endif
-
/*
* Use special translation offset for SPL. This needs to be
* configured *before* spl_init() is called as this function
@@ -273,7 +260,7 @@ void board_init_f(ulong dummy)
ret = spl_init();
if (ret) {
- debug("spl_init() failed: %d\n", ret);
+ printf("spl_init() failed: %d\n", ret);
hang();
}
@@ -289,7 +276,7 @@ void board_init_f(ulong dummy)
/* Setup DDR */
ret = ddr3_init();
if (ret) {
- debug("ddr3_init() failed: %d\n", ret);
+ printf("ddr3_init() failed: %d\n", ret);
hang();
}
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-03 15:32:58 +0000