diff options
Diffstat (limited to 'arch')
24 files changed, 880 insertions, 88 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index e4c123cd21..da5bc73185 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -33,6 +33,11 @@ #include <i2c.h> #include <miiphy.h> #include <cpsw.h> +#include <asm/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/musb.h> +#include <asm/omap_musb.h> DECLARE_GLOBAL_DATA_PTR; @@ -63,3 +68,83 @@ void setup_clocks_for_console(void) /* Not yet implemented */ return; } + +/* AM33XX has two MUSB controllers which can be host or gadget */ +#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \ + (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* USB 2.0 PHY Control */ +#define CM_PHY_PWRDN (1 << 0) +#define CM_PHY_OTG_PWRDN (1 << 1) +#define OTGVDET_EN (1 << 19) +#define OTGSESSENDEN (1 << 20) + +static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) +{ + if (on) { + clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, + OTGVDET_EN | OTGSESSENDEN); + } else { + clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); + } +} + +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +#ifdef CONFIG_AM335X_USB0 +static void am33xx_otg0_set_phy_power(u8 on) +{ + am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); +} + +struct omap_musb_board_data otg0_board_data = { + .set_phy_power = am33xx_otg0_set_phy_power, +}; + +static struct musb_hdrc_platform_data otg0_plat = { + .mode = CONFIG_AM335X_USB0_MODE, + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + .board_data = &otg0_board_data, +}; +#endif + +#ifdef CONFIG_AM335X_USB1 +static void am33xx_otg1_set_phy_power(u8 on) +{ + am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); +} + +struct omap_musb_board_data otg1_board_data = { + .set_phy_power = am33xx_otg1_set_phy_power, +}; + +static struct musb_hdrc_platform_data otg1_plat = { + .mode = CONFIG_AM335X_USB1_MODE, + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + .board_data = &otg1_board_data, +}; +#endif +#endif + +int arch_misc_init(void) +{ +#ifdef CONFIG_AM335X_USB0 + musb_register(&otg0_plat, &otg0_board_data, + (void *)AM335X_USB0_OTG_BASE); +#endif +#ifdef CONFIG_AM335X_USB1 + musb_register(&otg1_plat, &otg1_board_data, + (void *)AM335X_USB1_OTG_BASE); +#endif + return 0; +} diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index bc2abb657c..0b4cb4e529 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -40,6 +40,7 @@ #define CLK_MODE_MASK 0xfffffff8 #define CLK_DIV_SEL 0xFFFFFFE0 #define CPGMAC0_IDLE 0x30000 +#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; @@ -194,6 +195,11 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl); while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN) ; + + /* MUSB */ + writel(PRCM_MOD_EN, &cmper->usb0clkctrl); + while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) @@ -290,6 +296,8 @@ static void per_pll_config(void) while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK) ; + + writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper); } void ddr_pll_config(unsigned int ddrpll_m) diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index ac597be25a..de167eea56 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -38,6 +38,7 @@ endif COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o +COBJS-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap3/am35x_musb.c b/arch/arm/cpu/armv7/omap3/am35x_musb.c new file mode 100644 index 0000000000..7183c4f248 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/am35x_musb.c @@ -0,0 +1,75 @@ +/* + * This file configures the internal USB PHY in AM35X. + * + * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com> + * + * Based on omap_phy_internal.c code from Linux by + * Hema HK <hemahk@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/am35x_def.h> + +void am35x_musb_reset(void) +{ + /* Reset the musb interface */ + clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, + 0, USBOTGSS_SW_RST); + clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, + USBOTGSS_SW_RST, 0); +} + +void am35x_musb_phy_power(u8 on) +{ + unsigned long start = get_timer(0); + + if (on) { + /* + * Start the on-chip PHY and its PLL. + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN, + CONF2_PHY_PLLON); + + debug("Waiting for PHY clock good...\n"); + while (!(readl(&am35x_scm_general_regs->devconf2) + & CONF2_PHYCLKGD)) { + + if (get_timer(start) > CONFIG_SYS_HZ / 10) { + printf("musb PHY clock good timed out\n"); + break; + } + } + } else { + /* + * Power down the on-chip PHY. + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_PHY_PLLON, + CONF2_PHYPWRDN | CONF2_OTGPWRDN); + } +} + +void am35x_musb_clear_irq(void) +{ + clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr, + 0, USBOTGSS_INT_CLR); + readl(&am35x_scm_general_regs->lvl_intr_clr); +} + diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 819fd2f026..d6c038e3ae 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -82,7 +82,8 @@ struct cm_wkuppll { unsigned int clkseldpllcore; /* offset 0x68 */ unsigned int resv9[1]; unsigned int idlestdpllper; /* offset 0x70 */ - unsigned int resv10[3]; + unsigned int resv10[2]; + unsigned int clkdcoldodpllper; /* offset 0x7c */ unsigned int divm4dpllcore; /* offset 0x80 */ unsigned int divm5dpllcore; /* offset 0x84 */ unsigned int clkmoddpllmpu; /* offset 0x88 */ @@ -275,12 +276,16 @@ struct ctrl_stat { /* Control Device Register */ struct ctrl_dev { unsigned int deviceid; /* offset 0x00 */ - unsigned int resv1[11]; + unsigned int resv1[7]; + unsigned int usb_ctrl0; /* offset 0x20 */ + unsigned int resv2; + unsigned int usb_ctrl1; /* offset 0x28 */ + unsigned int resv3; unsigned int macid0l; /* offset 0x30 */ unsigned int macid0h; /* offset 0x34 */ unsigned int macid1l; /* offset 0x38 */ unsigned int macid1h; /* offset 0x3c */ - unsigned int resv2[4]; + unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 5bd4bc8722..24ab365ea3 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -87,4 +87,8 @@ /* RTC base address */ #define AM335X_RTC_BASE 0x44E3E000 +/* OTG */ +#define AM335X_USB0_OTG_BASE 0x47401000 +#define AM335X_USB1_OTG_BASE 0x47401800 + #endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h new file mode 100644 index 0000000000..8acdf9b725 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung <jh80.chung@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#define DWMCI_CLKSEL 0x09C +#define DWMCI_SHIFT_0 0x0 +#define DWMCI_SHIFT_1 0x1 +#define DWMCI_SHIFT_2 0x2 +#define DWMCI_SHIFT_3 0x3 +#define DWMCI_SET_SAMPLE_CLK(x) (x) +#define DWMCI_SET_DRV_CLK(x) ((x) << 16) +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24) + +int exynos_dwmci_init(u32 regbase, int bus_width, int index); + +static inline unsigned int exynos_dwmmc_init(int index, int bus_width) +{ + unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + return exynos_dwmci_init(base, bus_width, index); +} diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h index bbaf1bc97b..67698bc7ef 100644 --- a/arch/arm/include/asm/arch-omap3/am35x_def.h +++ b/arch/arm/include/asm/arch-omap3/am35x_def.h @@ -32,9 +32,34 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ +/* LVL_INTR_CLEAR bits */ +#define USBOTGSS_INT_CLR (1 << 4) + /* IP_SW_RESET bits */ +#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ #define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ +/* DEVCONF2 bits */ +#define CONF2_PHY_GPIOMODE (1 << 23) +#define CONF2_OTGMODE (3 << 14) +#define CONF2_NO_OVERRIDE (0 << 14) +#define CONF2_FORCE_HOST (1 << 14) +#define CONF2_FORCE_DEVICE (2 << 14) +#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) +#define CONF2_SESENDEN (1 << 13) +#define CONF2_VBDTCTEN (1 << 12) +#define CONF2_REFFREQ_24MHZ (2 << 8) +#define CONF2_REFFREQ_26MHZ (7 << 8) +#define CONF2_REFFREQ_13MHZ (6 << 8) +#define CONF2_REFFREQ (0xf << 8) +#define CONF2_PHYCLKGD (1 << 7) +#define CONF2_VBUSSENSE (1 << 6) +#define CONF2_PHY_PLLON (1 << 5) +#define CONF2_RESET (1 << 4) +#define CONF2_PHYPWRDN (1 << 3) +#define CONF2_OTGPWRDN (1 << 2) +#define CONF2_DATPOL (1 << 1) + /* General register mappings of system control module */ #define AM35X_SCM_GEN_BASE 0x48002270 struct am35x_scm_general { @@ -49,6 +74,8 @@ struct am35x_scm_general { }; #define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE) +#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 + #endif /*__ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-omap3/musb.h b/arch/arm/include/asm/arch-omap3/musb.h new file mode 100644 index 0000000000..423ac500f4 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/musb.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2012 + * Ilya Yanok, <ilya.yanok@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ASM_ARCH_OMAP3_MUSB_H +#define __ASM_ARCH_OMAP3_MUSB_H +extern void am35x_musb_reset(void); +extern void am35x_musb_phy_power(u8 on); +extern void am35x_musb_clear_irq(void); +#endif diff --git a/arch/arm/include/asm/omap_musb.h b/arch/arm/include/asm/omap_musb.h new file mode 100644 index 0000000000..b04d8650ef --- /dev/null +++ b/arch/arm/include/asm/omap_musb.h @@ -0,0 +1,32 @@ +/* + * Board data structure for musb gadget on OMAPs + * + * Copyright (C) 2012, Ilya Yanok <ilya.yanok@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARM_OMAP_MUSB_H +#define __ASM_ARM_OMAP_MUSB_H + +extern struct musb_platform_ops musb_dsps_ops; +extern const struct musb_platform_ops am35x_ops; +extern const struct musb_platform_ops omap2430_ops; + +struct omap_musb_board_data { + u8 interface_type; + void (*set_phy_power)(u8 on); + void (*clear_irq)(void); + void (*reset)(void); +}; + +enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; +#endif /* __ASM_ARM_OMAP_MUSB_H */ diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c index c747767e1e..b9b0998d48 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c @@ -615,7 +615,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) | usb_pipeendpoint (pipe) << 7 | (usb_pipeisoc (pipe)? 0x8000: 0) | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 + | (usb_dev->speed == USB_SPEED_LOW) << 13 | usb_maxpacket (usb_dev, pipe) << 16); return ed_ret; diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index a30715459d..b7062818bb 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -42,3 +42,8 @@ endif ifeq ($(CROSS_COMPILE),powerpc-openbsd-) PLATFORM_CPPFLAGS+= -D__PPC__ endif + +# Only test once +ifneq ($(CONFIG_SPL_BUILD),y) +ALL-y += checkgcc4 +endif diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c index 607034b7c6..de07343d93 100644 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c +++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c @@ -618,7 +618,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) | usb_pipeendpoint (pipe) << 7 | (usb_pipeisoc (pipe)? 0x8000: 0) | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 + | (usb_dev->speed == USB_SPEED_LOW) << 13 | usb_maxpacket (usb_dev, pipe) << 16); return ed_ret; diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 78c412d9f3..4c2b1040d4 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -28,7 +28,22 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o -START = start.o resetvec.o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +START = start.o resetvec.o + +ifdef MINIMAL + +COBJS-y += cpu_init_early.o tlb.o spl_minimal.o + +else + SOBJS-$(CONFIG_MP) += release.o SOBJS = $(SOBJS-y) @@ -121,17 +136,20 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o -COBJS = $(COBJS-y) -COBJS += cpu.o -COBJS += cpu_init.o -COBJS += cpu_init_early.o -COBJS += interrupts.o -COBJS += speed.o -COBJS += tlb.o -COBJS += traps.o +COBJS-y += cpu.o +COBJS-y += cpu_init.o +COBJS-y += cpu_init_early.o +COBJS-y += interrupts.o +COBJS-y += speed.o +COBJS-y += tlb.o +COBJS-y += traps.o # Stub implementations of cache management functions for USB -COBJS += cache.o +COBJS-y += cache.o + +endif # not minimal + +COBJS = $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index db232e64f8..78486aab85 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -332,7 +332,8 @@ void mpc85xx_reginfo(void) /* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET -#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) +#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ + !defined(CONFIG_SYS_INIT_L2_ADDR) phys_size_t initdram(int board_type) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f01804bbb9..705c16c558 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -470,7 +470,7 @@ int cpu_init_r(void) && l2srbar >= CONFIG_SYS_FLASH_BASE) { l2srbar = CONFIG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); + printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); } #endif /* CONFIG_SYS_INIT_L2_ADDR */ puts("\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index bf7a6f6be6..c6b9cd0acc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -21,12 +21,16 @@ */ #include <common.h> +#include <asm/processor.h> +#include <asm/global_data.h> #include <asm/fsl_ifc.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + void cpu_init_f(void) { -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#ifdef CONFIG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); @@ -40,3 +44,16 @@ void cpu_init_f(void) (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); #endif } + +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif + +void udelay(unsigned long usec) +{ + u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); + u32 ticks = ticks_per_usec * usec; + u32 s = mfspr(SPRN_TBRL); + + while ((mfspr(SPRN_TBRL) - s) < ticks); +} diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index ac17f9d3ca..bb0dc1a653 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -44,6 +44,15 @@ #undef MSR_KERNEL #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ +#if defined(CONFIG_NAND_SPL) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) +#define MINIMAL_SPL +#endif + +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) +#define NOR_BOOT +#endif + /* * Set up GOT: Global Offset Table * @@ -53,7 +62,7 @@ GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) @@ -282,51 +291,8 @@ l2_disabled: isync .endm -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) -/* - * TLB entry for debuggging in AS1 - * Create temporary TLB entry in AS0 to handle debug exception - * As on debug exception MSR is cleared i.e. Address space is changed - * to 0. A TLB entry (in AS0) is required to handle debug exception generated - * in AS1. - */ - -#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) -/* - * TLB entry is created for IVPR + IVOR15 to map on valid OP code address - * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. - * and this window is outside of 4K boot window. - */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_4M, \ - CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ - 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 - -#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 -#else -/* - * TLB entry is created for IVPR + IVOR15 to map on valid OP code address - * because "nexti" will resize TLB to 4K - */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_256K, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I, \ - CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 -#endif -#endif - -/* - * Ne need to setup interrupt vector for NAND SPL - * because NAND SPL never compiles it. - */ -#if !defined(CONFIG_NAND_SPL) +/* Interrupt vectors do not fit in minimal SPL. */ +#if !defined(MINIMAL_SPL) /* Setup interrupt vectors */ lis r1,CONFIG_SYS_MONITOR_BASE@h mtspr IVPR,r1 @@ -534,10 +500,6 @@ nexti: mflr r1 /* R1 = our PC */ li r3, 0 mtspr MAS1, r3 1: cmpw r3, r14 -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) - cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB - cror cr0*4+eq, cr0*4+eq, cr1*4+eq -#endif rlwinm r5, r3, 16, MAS0_ESEL_MSK addi r3, r3, 1 beq 2f /* skip the entry we're executing from */ @@ -553,6 +515,46 @@ nexti: mflr r1 /* R1 = our PC */ 2: cmpw r3, r4 blt 1b +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + */ + +#ifdef NOR_BOOT +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. + * and this window is outside of 4K boot window. + */ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_4M, \ + CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ + 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 + +#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ + CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#else +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * because "nexti" will resize TLB to 4K + */ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_256K, \ + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \ + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#endif +#endif + /* * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default * location is not where we want it. This typically happens on a 36-bit @@ -1036,7 +1038,7 @@ create_init_ram_area: lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l -#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) +#ifdef NOR_BOOT /* create a temp mapping in AS=1 to the 4M boot window */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_4M, \ @@ -1050,8 +1052,8 @@ create_init_ram_area: */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #else /* @@ -1060,8 +1062,8 @@ create_init_ram_area: */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #endif @@ -1111,7 +1113,8 @@ switch_as: bdnz 1b /* Jump out the last 4K page and continue to 'normal' start */ -#ifdef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) + /* We assume that we're already running at the address we're linked at */ b _start_cont #else /* Calculate absolute address in FLASH and jump there */ @@ -1157,7 +1160,7 @@ _start_cont: /* NOTREACHED - board_init_f() does not return */ -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: @@ -1601,7 +1604,7 @@ in32: in32r: lwbrx r3,r0,r3 blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ /*------------------------------------------------------------------------------*/ @@ -1798,7 +1801,7 @@ clear_bss: mr r4,r10 /* Destination Address */ bl board_init_r -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Copy exception vector code to low memory * @@ -1971,4 +1974,4 @@ setup_ivors: #include "fixed_ivor.S" blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index a548dec9a7..f44fadcffd 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -55,7 +55,7 @@ void init_tlbs(void) return ; } -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { @@ -332,4 +332,4 @@ void clear_ddr_tlbs(unsigned int memsize_in_meg) } -#endif /* !CONFIG_NAND_SPL */ +#endif /* not SPL */ diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file mode 100644 index 0000000000..1c408e29f5 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "config.h" /* CONFIG_BOARDDIR */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = CONFIG_SPL_TEXT_BASE; + .text : { + *(.text*) + } + _etext = .; + + .reloc : { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + . = ALIGN(8); + .data : { + *(.rodata*) + *(.data*) + *(.sdata*) + } + _edata = .; + + . = ALIGN(8); + __init_begin = .; + __init_end = .; +/* FIXME for non-NAND SPL */ +#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ + .bootpg ADDR(.text) + 0x1000 : + { + start.o (.bootpg) + } +#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#elif defined(CONFIG_FSL_ELBC) +#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ +#else +#error unknown NAND controller +#endif + .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { + KEEP(*(.resetvec)) + } = 0xffff + + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. + */ + . |= 0x10; + + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + __bss_end__ = .; +} diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 4ae26e4210..3dc8e055b6 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -10,6 +10,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +COBJS-$(CONFIG_FSL_LAW) += law.o + +else + ifneq ($(CPU),mpc83xx) COBJS-y += cpu.o endif @@ -18,6 +32,9 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o COBJS-$(CONFIG_SYS_SRIO) += srio.o +COBJS-$(CONFIG_FSL_LAW) += law.o + +endif SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c new file mode 100644 index 0000000000..ce1d71e307 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -0,0 +1,334 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/compiler.h> +#include <asm/fsl_law.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS + +#ifdef CONFIG_FSL_CORENET +#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR) +#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar) +#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh) +#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl) +#define LAWBAR_SHIFT 0 +#else +#define LAW_BASE (CONFIG_SYS_IMMR + 0xc08) +#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2) +#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x) +#define LAWBAR_SHIFT 12 +#endif + + +static inline phys_addr_t get_law_base_addr(int idx) +{ +#ifdef CONFIG_FSL_CORENET + return (phys_addr_t) + ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) | + in_be32(LAWBARL_ADDR(idx)); +#else + return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT; +#endif +} + +static inline void set_law_base_addr(int idx, phys_addr_t addr) +{ +#ifdef CONFIG_FSL_CORENET + out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff); + out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32); +#else + out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT); +#endif +} + +void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) +{ + gd->used_laws |= (1 << idx); + + out_be32(LAWAR_ADDR(idx), 0); + set_law_base_addr(idx, addr); + out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz); + + /* Read back so that we sync the writes */ + in_be32(LAWAR_ADDR(idx)); +} + +void disable_law(u8 idx) +{ + gd->used_laws &= ~(1 << idx); + + out_be32(LAWAR_ADDR(idx), 0); + set_law_base_addr(idx, 0); + + /* Read back so that we sync the writes */ + in_be32(LAWAR_ADDR(idx)); + + return; +} + +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +static int get_law_entry(u8 i, struct law_entry *e) +{ + u32 lawar; + + lawar = in_be32(LAWAR_ADDR(i)); + + if (!(lawar & LAW_EN)) + return 0; + + e->addr = get_law_base_addr(i); + e->size = lawar & 0x3f; + e->trgt_id = (lawar >> 20) & 0xff; + + return 1; +} +#endif + +int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) +{ + u32 idx = ffz(gd->used_laws); + + if (idx >= FSL_HW_NUM_LAWS) + return -1; + + set_law(idx, addr, sz, id); + + return idx; +} + +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) +{ + u32 idx; + + /* we have no LAWs free */ + if (gd->used_laws == -1) + return -1; + + /* grab the last free law */ + idx = __ilog2(~(gd->used_laws)); + + if (idx >= FSL_HW_NUM_LAWS) + return -1; + + set_law(idx, addr, sz, id); + + return idx; +} + +struct law_entry find_law(phys_addr_t addr) +{ + struct law_entry entry; + int i; + + entry.index = -1; + entry.addr = 0; + entry.size = 0; + entry.trgt_id = 0; + + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + u64 upper; + + if (!get_law_entry(i, &entry)) + continue; + + upper = entry.addr + (2ull << entry.size); + if ((addr >= entry.addr) && (addr < upper)) { + entry.index = i; + break; + } + } + + return entry; +} + +void print_laws(void) +{ + int i; + u32 lawar; + + printf("\nLocal Access Window Configuration\n"); + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + lawar = in_be32(LAWAR_ADDR(i)); +#ifdef CONFIG_FSL_CORENET + printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x", + i, in_be32(LAWBARH_ADDR(i)), + i, in_be32(LAWBARL_ADDR(i))); +#else + printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i))); +#endif + printf(" LAWAR%02d: 0x%08x\n", i, lawar); + printf("\t(EN: %d TGT: 0x%02x SIZE: ", + (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff); + print_size(lawar_size(lawar), ")\n"); + } + + return; +} + +/* use up to 2 LAWs for DDR, used the last available LAWs */ +int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) +{ + u64 start_align, law_sz; + int law_sz_enc; + + if (start == 0) + start_align = 1ull << (LAW_SIZE_32G + 1); + else + start_align = 1ull << (ffs64(start) - 1); + law_sz = min(start_align, sz); + law_sz_enc = __ilog2_u64(law_sz) - 1; + + if (set_last_law(start, law_sz_enc, id) < 0) + return -1; + + /* recalculate size based on what was actually covered by the law */ + law_sz = 1ull << __ilog2_u64(law_sz); + + /* do we still have anything to map */ + sz = sz - law_sz; + if (sz) { + start += law_sz; + + start_align = 1ull << (ffs64(start) - 1); + law_sz = min(start_align, sz); + law_sz_enc = __ilog2_u64(law_sz) - 1; + + if (set_last_law(start, law_sz_enc, id) < 0) + return -1; + } else { + return 0; + } + + /* do we still have anything to map */ + sz = sz - law_sz; + if (sz) + return 1; + + return 0; +} +#endif /* not SPL */ + +void init_laws(void) +{ + int i; + +#if FSL_HW_NUM_LAWS < 32 + gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); +#elif FSL_HW_NUM_LAWS == 32 + gd->used_laws = 0; +#else +#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes +#endif + + /* + * Any LAWs that were set up before we booted assume they are meant to + * be around and mark them used. + */ + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + u32 lawar = in_be32(LAWAR_ADDR(i)); + + if (lawar & LAW_EN) + gd->used_laws |= (1 << i); + } + +#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + /* + * in SPL boot we've already parsed the law_table and setup those LAWs + * so don't do it again. + */ + return; +#endif + + for (i = 0; i < num_law_entries; i++) { + if (law_table[i].index == -1) + set_next_law(law_table[i].addr, law_table[i].size, + law_table[i].trgt_id); + else + set_law(law_table[i].index, law_table[i].addr, + law_table[i].size, law_table[i].trgt_id); + } + +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* check RCW to get which port is used for boot */ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 bootloc = in_be32(&gur->rcwsr[6]); + /* + * in SRIO or PCIE boot we need to set specail LAWs for + * SRIO or PCIE interfaces. + */ + switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { + case 0x0: /* boot from PCIE1 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_1); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_1); + break; + case 0x1: /* boot from PCIE2 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_2); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_2); + break; + case 0x2: /* boot from PCIE3 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_3); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_3); + break; + case 0x8: /* boot from SRIO1 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_1); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_1); + break; + case 0x9: /* boot from SRIO2 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_2); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_2); + break; + default: + break; + } +#endif + + return ; +} diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c index 4ce2726297..f820c37a8f 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c @@ -621,7 +621,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) | usb_pipeendpoint (pipe) << 7 | (usb_pipeisoc (pipe)? 0x8000: 0) | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 + | (usb_dev->speed == USB_SPEED_LOW) << 13 | usb_maxpacket (usb_dev, pipe) << 16); return ed_ret; diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 808021c42e..20c5c3803b 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -38,8 +38,21 @@ endif LIB = $(obj)lib$(ARCH).o -SOBJS-y += ppccache.o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +COBJS-y += cache.o +else + SOBJS-y += ppcstring.o + +SOBJS-y += ppccache.o SOBJS-y += ticks.o SOBJS-y += reloc.o @@ -64,6 +77,8 @@ $(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy COBJS-y += memcpy_mpc5200.o endif +endif # not minimal + COBJS += $(sort $(COBJS-y)) SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ @@ -75,12 +90,6 @@ TARGETS += $(LIB) all: $(TARGETS) $(LIB): $(obj).depend $(OBJS) - @if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\ - then \ - echo "ERROR: Your compiler doesn't generate .fixup sections!";\ - echo " Upgrade to a recent toolchain."; \ - exit 1; \ - fi; $(call cmd_link_o_target, $(OBJS)) $(LIBGCC): $(obj).depend $(LGOBJS) |