diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/armada-3720-eDPU-u-boot.dtsi | 13 | ||||
| -rw-r--r-- | arch/arm/dts/armada-3720-eDPU.dts | 47 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/alleycat5/cpu.c | 66 |
3 files changed, 106 insertions, 20 deletions
diff --git a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi index cb02b70e54..c3d450dd83 100644 --- a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi +++ b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi @@ -32,14 +32,17 @@ bootph-all; }; -ð0 { - /* G.hn does not work without additional configuration */ - status = "disabled"; -}; - ð1 { fixed-link { speed = <1000>; full-duplex; }; }; + +/* + * eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used + * to patch the Linux DTS if its found so enable MDIO by default. + */ +&mdio { + status = "okay"; +}; diff --git a/arch/arm/dts/armada-3720-eDPU.dts b/arch/arm/dts/armada-3720-eDPU.dts index 57fc698e55..d6d37a1f6f 100644 --- a/arch/arm/dts/armada-3720-eDPU.dts +++ b/arch/arm/dts/armada-3720-eDPU.dts @@ -12,3 +12,50 @@ ð0 { phy-mode = "2500base-x"; }; + +/* + * External MV88E6361 switch is only available on v2 of the board. + * U-Boot will enable the MDIO bus and switch nodes. + */ +&mdio { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&smi_pins>; + + /* Actual device is MV88E6361 */ + switch: switch@0 { + compatible = "marvell,mv88e6190"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + phy-mode = "2500base-x"; + managed = "in-band-status"; + ethernet = <ð0>; + }; + + port@9 { + reg = <9>; + label = "downlink"; + phy-mode = "2500base-x"; + managed = "in-band-status"; + }; + + port@a { + reg = <10>; + label = "uplink"; + phy-mode = "2500base-x"; + managed = "in-band-status"; + sfp = <&sfp_eth1>; + }; + }; + }; +}; diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index 8204d96275..0f72ae1709 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -16,7 +16,10 @@ DECLARE_GLOBAL_DATA_PTR; -#define RAM_SIZE SZ_1G +#define AC5_PTE_BLOCK_DEVICE \ + (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \ + PTE_BLOCK_NON_SHARE | \ + PTE_BLOCK_PXN | PTE_BLOCK_UXN) static struct mm_region ac5_mem_map[] = { { @@ -31,30 +34,63 @@ static struct mm_region ac5_mem_map[] = { .phys = 0x00000000, .virt = 0xa0000000, .size = 0x100000, - - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN + .attrs = AC5_PTE_BLOCK_DEVICE, }, { /* MMIO regions */ .phys = 0x100000, .virt = 0x100000, .size = 0x3ff00000, - - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN + .attrs = AC5_PTE_BLOCK_DEVICE, }, { - /* MMIO regions */ .phys = 0x7F000000, .virt = 0x7F000000, - .size = 0x21000000, - - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN + .size = SZ_8M, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7F800000, + .virt = 0x7F800000, + .size = SZ_4M, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7FC00000, + .virt = 0x7FC00000, + .size = SZ_512K, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7FC80000, + .virt = 0x7FC80000, + .size = SZ_512K, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7FD00000, + .virt = 0x7FD00000, + .size = SZ_512K, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + /* ATF region 0x7FE00000-0x7FE20000 not mapped */ + { + .phys = 0x7FE80000, + .virt = 0x7FE80000, + .size = SZ_512K, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7FFF0000, + .virt = 0x7FFF0000, + .size = SZ_1M, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x80000000, + .virt = 0x80000000, + .size = SZ_2G, + .attrs = AC5_PTE_BLOCK_DEVICE, }, { 0, |