diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/dts/zynq-cse-nand.dts | 7 | ||||
| -rw-r--r-- | arch/arm/dts/zynq-cse-nor.dts | 7 | ||||
| -rw-r--r-- | arch/arm/dts/zynq-cse-qspi.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/mach-zynqmp/Kconfig | 9 | ||||
| -rw-r--r-- | arch/arm/mach-zynqmp/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynqmp/include/mach/hardware.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-zynqmp/mp.c | 26 |
8 files changed, 61 insertions, 5 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f95ed71b24..3f68d0988b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1302,7 +1302,7 @@ config ARCH_ZYNQMP select DM select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART select DM_ETH if NET - select DM_MAILBOX + imply DM_MAILBOX select DM_MMC if MMC select DM_SERIAL select DM_SPI if SPI @@ -1319,7 +1319,7 @@ config ARCH_ZYNQMP imply SPL_FIRMWARE if SPL select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL - select ZYNQMP_IPI + imply ZYNQMP_IPI if DM_MAILBOX select SOC_DEVICE imply BOARD_LATE_INIT imply CMD_DM diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 32cb3bffcb..27adfb9216 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -86,6 +86,13 @@ reg = <0x100 0x100>; }; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; }; }; diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index 197fbd717a..f22a149f79 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -85,6 +85,13 @@ #address-cells = <1>; #size-cells = <1>; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; }; }; diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi index 38410eeca8..f7ac92b802 100644 --- a/arch/arm/dts/zynq-cse-qspi.dtsi +++ b/arch/arm/dts/zynq-cse-qspi.dtsi @@ -116,6 +116,13 @@ reg = <0x100 0x100>; }; }; + + scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clock-frequency = <333333333>; + }; }; }; diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 66045067d2..fd6f07715a 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -142,7 +142,14 @@ config ZYNQMP_PSU_INIT_ENABLED bool "Include psu_init" select BOARD_EARLY_INIT_F help - Include psu_init to full u-boot. SPL include psu_init by default. + Include psu_init to full u-boot. + +config SPL_ZYNQMP_PSU_INIT_ENABLED + bool "Include psu_init in SPL" + default y if SPL + select BOARD_EARLY_INIT_F + help + Include psu_init by default in SPL. config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED bool "Overwrite SPL bootmode" diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 4f9f6b56a9..bb1830c846 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -8,4 +8,4 @@ obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o -obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o +obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index a70d6d611b..70221e0305 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -175,7 +175,9 @@ struct csu_regs { #define ZYNQMP_PMU_BASEADDR 0xFFD80000 struct pmu_regs { - u32 reserved[18]; + u32 reserved0[16]; + u32 gen_storage4; /* 0x40 */ + u32 reserved1[1]; u32 gen_storage6; /* 0x48 */ }; diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 949456d530..2891878973 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -42,6 +42,9 @@ #define ZYNQMP_MAX_CORES 6 +#define ZYNQMP_RPU0_USE_MASK BIT(1) +#define ZYNQMP_RPU1_USE_MASK BIT(2) + int is_core_valid(unsigned int core) { if (core < ZYNQMP_MAX_CORES) @@ -250,6 +253,27 @@ void initialize_tcm(bool mode) } } +static void mark_r5_used(u32 nr, u8 mode) +{ + u32 mask = 0; + + if (mode == LOCK) { + mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK; + } else { + switch (nr) { + case ZYNQMP_CORE_RPU0: + mask = ZYNQMP_RPU0_USE_MASK; + break; + case ZYNQMP_CORE_RPU1: + mask = ZYNQMP_RPU1_USE_MASK; + break; + default: + return; + } + } + zynqmp_mmio_write((ulong)&pmu_base->gen_storage4, mask, mask); +} + int cpu_release(u32 nr, int argc, char *const argv[]) { if (nr <= ZYNQMP_CORE_APU3) { @@ -305,6 +329,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) write_tcm_boot_trampoline(boot_addr_uniq); dcache_enable(); set_r5_halt_mode(nr, RELEASE, LOCK); + mark_r5_used(nr, LOCK); } else if (!strncmp(argv[1], "split", 5)) { printf("R5 split mode\n"); set_r5_reset(nr, SPLIT); @@ -317,6 +342,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) write_tcm_boot_trampoline(boot_addr_uniq); dcache_enable(); set_r5_halt_mode(nr, RELEASE, SPLIT); + mark_r5_used(nr, SPLIT); } else { printf("Unsupported mode\n"); return 1; |