diff options
Diffstat (limited to 'arch')
179 files changed, 1329 insertions, 692 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 3aa99e08fc..27843cd79c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -7,6 +7,17 @@ config HAVE_ARCH_IOREMAP config NEEDS_MANUAL_RELOC bool +config LINKER_LIST_ALIGN + int + default 32 if SANDBOX + default 8 if ARM64 || X86 + default 4 + help + Force the each linker list to be aligned to this boundary. This + is required if ll_entry_get() is used, since otherwise the linker + may add padding into the table, thus breaking it. + See linker_lists.rst for full details. + choice prompt "Architecture select" default SANDBOX @@ -112,6 +123,7 @@ config SANDBOX imply BITREVERSE select BLOBLIST imply CMD_DM + imply CMD_EXCEPTION imply CMD_GETTIME imply CMD_HASH imply CMD_IO @@ -146,6 +158,8 @@ config SANDBOX imply ACPI_PMC_SANDBOX imply CMD_PMC imply CMD_CLONE + imply SILENT_CONSOLE + imply BOOTARGS_SUBST config SH bool "SuperH architecture" diff --git a/arch/arc/include/asm/spl.h b/arch/arc/include/asm/spl.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/arch/arc/include/asm/spl.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fbe90875ae..54762ce03a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1045,6 +1045,7 @@ config ARCH_SUNXI select SPL_USE_TINY_PRINTF select USE_PREBOOT select SYS_RELOC_GD_ENV_ADDR + imply BOARD_LATE_INIT imply CMD_DM imply CMD_GPT imply CMD_UBI if MTD_RAW_NAND diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index d8cb78ecc6..2556980cde 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -52,7 +52,11 @@ void ft_fixup_enet_phy_connect_type(void *fdt) continue; } +#ifdef CONFIG_DM_ETH + priv = dev_get_priv(dev); +#else priv = dev->priv; +#endif if (priv->flags & TSEC_SGMII) continue; diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 93d26f9856..f7b4a5ee46 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -27,6 +27,8 @@ obj-$(CONFIG_ARM_SMCCC) += smccc-call.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o +else +obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o endif obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 97d4473a68..61c38b17cb 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -9,7 +9,7 @@ #include <asm/system.h> #include <asm/armv8/sec_firmware.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) int psci_update_dt(void *fdt) { /* diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S new file mode 100644 index 0000000000..9510dcd9e4 --- /dev/null +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -0,0 +1,78 @@ +/* + * Utility functions for FEL mode, when running SPL in AArch64. + * + * Copyright (c) 2017 Arm Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/system.h> +#include <linux/linkage.h> + +/* + * We don't overwrite save_boot_params() here, to save the FEL state upon + * entry, since this would run *after* the RMR reset, which clobbers that + * state. + * Instead we store the state _very_ early in the boot0 hook, *before* + * resetting to AArch64. + */ + +/* + * The FEL routines in BROM run in AArch32. + * Reset back into 32-bit mode here and restore the saved FEL state + * afterwards. + * Resetting back into AArch32/EL3 using the RMR always enters the BROM, + * but we can use the CPU hotplug mechanism to branch back to our code + * immediately. + */ +ENTRY(return_to_fel) + /* + * the RMR reset will clear all registers, so save the arguments + * (LR and SP) in the fel_stash structure, which we read anyways later + */ + adr x2, fel_stash + str w0, [x2] + str w1, [x2, #4] + + adr x1, fel_stash_addr // to find the fel_stash address in AA32 + str w2, [x1] + + ldr x0, =0xfa50392f // CPU hotplug magic +#ifdef CONFIG_MACH_SUN50I_H6 + ldr x2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG + str w0, [x2], #0x4 +#else + ldr x2, =(SUNXI_CPUCFG_BASE + 0x1a4) // offset for CPU hotplug base + str w0, [x2, #0x8] +#endif + adr x0, back_in_32 + str w0, [x2] + + dsb sy + isb sy + mov x0, #2 // RMR reset into AArch32 + dsb sy + msr RMR_EL3, x0 + isb sy +1: wfi + b 1b + +/* AArch32 code to restore the state from fel_stash and return back to FEL. */ +back_in_32: + .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address + .word 0xe5901008 // ldr r1, [r0, #8] + .word 0xe129f001 // msr CPSR_fc, r1 + .word 0xf57ff06f // isb + .word 0xe590d000 // ldr sp, [r0] + .word 0xe590e004 // ldr lr, [r0, #4] + .word 0xe5901010 // ldr r1, [r0, #16] + .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR + .word 0xe590100c // ldr r1, [r0, #12] + .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR + .word 0xf57ff06f // isb + .word 0xe12fff1e // bx lr ; return to FEL +fel_stash_addr: + .word 0x00000000 // receives fel_stash addr, by AA64 code above +ENDPROC(return_to_fel) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 3a04dce56f..7f29aa4725 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -26,7 +26,7 @@ #endif #include <fsl_sec.h> #include <asm/arch-fsl-layerscape/soc.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) #include <asm/armv8/sec_firmware.h> #endif #include <asm/arch/speed.h> @@ -81,7 +81,7 @@ void ft_fixup_cpu(void *blob) "device_type", "cpu", 4); } -#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) int node; u32 psci_ver; @@ -383,7 +383,7 @@ static void fdt_fixup_msi(void *blob) } #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) /* Remove JR node used by SEC firmware */ void fdt_fixup_remove_jr(void *blob) { @@ -490,7 +490,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) else { ccsr_sec_t __iomem *sec; -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) fdt_fixup_remove_jr(blob); fdt_fixup_kaslr(blob); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a519f6ed67..d8803738f1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -192,6 +192,7 @@ ENTRY(lowlevel_init) #endif /* Initialize GIC Secure Bank Status */ +#if !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f bl get_gic_offset @@ -205,6 +206,7 @@ ENTRY(lowlevel_init) bl gic_init_secure_percpu #endif #endif +#endif 100: branch_if_master x0, x1, 2f diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index 1ddb267093..2285296ea0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -16,7 +16,7 @@ #elif defined(CONFIG_FSL_LSCH2) #include <asm/arch/immap_lsch2.h> #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) #include <asm/armv8/sec_firmware.h> #endif #ifdef CONFIG_CHAIN_OF_TRUST diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 77724336d6..215ed9759e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -38,6 +38,9 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_BUILD +/* Define board data structure */ +static struct bd_info bdata __attribute__ ((section(".data"))); + void spl_board_init(void) { #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2) @@ -74,7 +77,7 @@ void board_init_f(ulong dummy) get_clocks(); preloader_console_init(); - spl_set_bd(); + gd->bd = &bdata; #ifdef CONFIG_SYS_I2C #ifdef CONFIG_SPL_I2C_SUPPORT diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 073cf0672e..0f738c224f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -590,6 +590,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-s3-pinecube.dtb \ sun8i-v3s-licheepi-zero.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-bananapi-m2-plus.dtb \ diff --git a/arch/arm/dts/armada-xp-gp-u-boot.dtsi b/arch/arm/dts/armada-xp-gp-u-boot.dtsi new file mode 100644 index 0000000000..2422856616 --- /dev/null +++ b/arch/arm/dts/armada-xp-gp-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + soc { + internal-regs { + serial@12000 { + u-boot,dm-pre-reloc; + }; + }; + }; +}; + +&spi0 { + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts index 1139e9469a..d46475fe22 100644 --- a/arch/arm/dts/armada-xp-gp.dts +++ b/arch/arm/dts/armada-xp-gp.dts @@ -31,6 +31,10 @@ stdout-path = "serial0:115200n8"; }; + aliases { + spi0 = &spi0; + }; + memory@0 { device_type = "memory"; /* diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 80d6475b7c..9e0d264b71 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 771ab635f1..701af4434d 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index e63684c334..9b4e0298a7 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -16,7 +16,7 @@ ethernet3 = &enetc6; }; - binman { + binman: binman { filename = "u-boot.rom"; pad-byte = <0xff>; @@ -80,21 +80,18 @@ conf-1 { description = "fsl-ls1028a-kontron-sl28"; firmware = "uboot"; - loadables = "uboot"; fdt = "fdt-1"; }; conf-2 { description = "fsl-ls1028a-kontron-sl28-var3"; firmware = "uboot"; - loadables = "uboot"; fdt = "fdt-2"; }; conf-3 { description = "fsl-ls1028a-kontron-sl28-var4"; firmware = "uboot"; - loadables = "uboot"; fdt = "fdt-3"; }; }; @@ -102,6 +99,81 @@ }; }; +#ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31 +&binman { + fit { + images { + bl31 { + description = "ARM Trusted Firmware (bl31)"; + type = "firmware"; + arch = "arm"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <CONFIG_SL28_BL31_ENTRY_ADDR>; + entry = <CONFIG_SL28_BL31_ENTRY_ADDR>; + + blob-ext { + filename = "bl31.bin"; + }; + }; + }; + + configurations { + conf-1 { + firmware = "bl31"; + loadables = "uboot"; + }; + + conf-2 { + firmware = "bl31"; + loadables = "uboot"; + }; + + conf-3 { + firmware = "bl31"; + loadables = "uboot"; + }; + }; + }; +}; +#endif + +#ifdef CONFIG_SL28_SPL_LOADS_OPTEE_BL32 +&binman { + fit { + images { + bl32 { + description = "OP-TEE Trusted OS (bl32)"; + type = "firmware"; + arch = "arm"; + os = "tee"; + compression = "none"; + load = <CONFIG_SL28_BL32_ENTRY_ADDR>; + entry = <CONFIG_SL28_BL32_ENTRY_ADDR>; + + blob-ext { + filename = "tee.bin"; + }; + }; + }; + + configurations { + conf-1 { + loadables = "uboot", "bl32"; + }; + + conf-2 { + loadables = "uboot", "bl32"; + }; + + conf-3 { + loadables = "uboot", "bl32"; + }; + }; + }; +}; +#endif + &i2c0 { rtc: rtc@32 { }; diff --git a/arch/arm/dts/imx6q-ba16.dtsi b/arch/arm/dts/imx6q-ba16.dtsi index 7d8f61f2fd..9da2bb6e86 100644 --- a/arch/arm/dts/imx6q-ba16.dtsi +++ b/arch/arm/dts/imx6q-ba16.dtsi @@ -174,6 +174,17 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; status = "okay"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &hdmi { diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi b/arch/arm/dts/imx6ull-dart-6ul.dtsi index e96669f493..805a382da9 100644 --- a/arch/arm/dts/imx6ull-dart-6ul.dtsi +++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi @@ -14,6 +14,10 @@ chosen { stdout-path = &uart1; }; + + aliases { + eeprom0 = &eeprom_som; + }; }; &fec1 { @@ -52,6 +56,10 @@ }; }; +&gpio1 { + u-boot,dm-pre-reloc; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -96,10 +104,13 @@ scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; status = "okay"; + u-boot,dm-pre-reloc; - eeprom@50 { - compatible = "cat,24c32"; + eeprom_som: eeprom@50 { + u-boot,dm-pre-reloc; + compatible = "atmel,24c04"; reg = <0x50>; + status = "okay"; }; }; @@ -205,6 +216,7 @@ }; pinctrl_i2c2: i2cgrp { + u-boot,dm-pre-reloc; fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 @@ -212,6 +224,7 @@ }; pinctrl_i2c2_gpio: i2c2grp_gpio { + u-boot,dm-pre-reloc; fsl,pins = < MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi index baa5f997d0..d6b9dedd16 100644 --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi @@ -10,19 +10,19 @@ led0 { label = "gen_led0"; gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led1 { label = "gen_led1"; gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led2 { label = "gen_led2"; gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led3 { @@ -70,7 +70,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; eeprom@0 { @@ -210,7 +210,7 @@ >; }; - pinctrl_pcal6414: pcal6414-gpio { + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 >; @@ -240,7 +240,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -259,7 +259,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -271,7 +271,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index fc1aebb2fe..6d80a529ae 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -37,6 +37,10 @@ /delete-property/ assigned-clock-rates; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &fec1 { phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi index 801bd02eae..b88c3c99b0 100644 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -24,6 +24,26 @@ cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -52,9 +72,10 @@ pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { @@ -116,7 +137,7 @@ ldo1_reg: LDO1 { regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; @@ -124,7 +145,7 @@ ldo2_reg: LDO2 { regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; @@ -164,7 +185,7 @@ status = "okay"; eeprom@50 { - compatible = "microchip, at24c64d", "atmel,24c64"; + compatible = "microchip,24c64", "atmel,24c64"; pagesize = <32>; read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x50>; @@ -190,6 +211,7 @@ host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; clocks = <&osc_32k>; + max-speed = <4000000>; clock-names = "extclk"; }; }; @@ -270,9 +292,9 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; @@ -289,7 +311,7 @@ >; }; - pinctrl_usdhc1_gpio: usdhc1grpgpio { + pinctrl_usdhc1_gpio: usdhc1gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 >; @@ -306,7 +328,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 @@ -317,7 +339,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 @@ -344,7 +366,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -360,7 +382,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index b5c12105a9..e843a5648e 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -46,6 +46,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &pinctrl_reg_usdhc2_vmmc { u-boot,dm-spl; }; @@ -96,10 +100,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &i2c1 { diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index 1e5e11592f..05ee062548 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -18,10 +18,18 @@ aliases { ethernet0 = &fec1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -29,14 +37,6 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; }; cpus { @@ -68,6 +68,7 @@ nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -80,6 +81,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -92,6 +94,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -104,6 +107,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -125,7 +129,7 @@ opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; + opp-microvolt = <950000>; opp-supported-hw = <0xc>, <0x7>; clock-latency-ns = <150000>; opp-suspend; @@ -204,6 +208,38 @@ arm,no-tick-in-suspend; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + usbphynop1: usbphynop1 { compatible = "usb-nop-xceiv"; clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; @@ -227,12 +263,14 @@ ranges = <0x0 0x0 0x0 0x3e000000>; aips1: bus@30000000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30000000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; sai1: sai@30010000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@ -246,6 +284,7 @@ }; sai2: sai@30020000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@ -273,6 +312,7 @@ }; sai5: sai@30050000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; @@ -286,6 +326,7 @@ }; sai6: sai@30060000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; @@ -363,6 +404,13 @@ gpio-ranges = <&iomuxc 0 119 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -419,7 +467,7 @@ reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { + ocotp: efuse@30350000 { compatible = "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; @@ -455,6 +503,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "snvs-pwrkey"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; @@ -469,16 +519,20 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MM_CLK_NOC>, + assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, + <&clk IMX8MM_CLK_A53_CORE>, + <&clk IMX8MM_CLK_NOC>, <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_ARM_PLL_OUT>, + <&clk IMX8MM_SYS_PLL3_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, + assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, <750000000>, @@ -496,7 +550,8 @@ }; aips2: bus@30400000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30400000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30400000 0x30400000 0x400000>; @@ -555,10 +610,12 @@ }; aips3: bus@30800000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30800000 0x400000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; ecspi1: spi@30820000 { compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; @@ -718,6 +775,14 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_MU_ROOT>; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; @@ -760,6 +825,19 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, + <&clk IMX8MM_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; @@ -776,7 +854,8 @@ reg = <0x30be0000 0x10000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET_TIMER>, @@ -800,7 +879,8 @@ }; aips4: bus@32c00000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; @@ -896,7 +976,6 @@ ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 4419679d4c..025090fff4 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -47,6 +47,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &pinctrl_uart2 { u-boot,dm-spl; }; @@ -93,10 +97,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 24a93ac2d6..4f00b5a3a9 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -49,6 +49,10 @@ }; ®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +®_usdhc2_vmmc { u-boot,dm-spl; }; @@ -122,10 +126,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi new file mode 100644 index 0000000000..44af663727 --- /dev/null +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +&usdhc1 { + mmc-hs400-1_8v; +}; + +&usdhc2 { + sd-uhs-sdr104; + sd-uhs-ddr50; +}; diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi new file mode 100644 index 0000000000..4712cf6a44 --- /dev/null +++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-a1.dts index 5f9ac955ed..d1f2fff869 100644 --- a/arch/arm/dts/imx8qm-rom7720-a1.dts +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts @@ -293,7 +293,7 @@ &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,ar8031-phy-fixup; fsl,magic-packet; @@ -318,7 +318,7 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy1>; fsl,ar8031-phy-fixup; fsl,magic-packet; diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index ded7db0aef..ee3b98698e 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { - aliases { - spi0 = &spi1; - }; - chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts index e8508aa4d5..4948ccd401 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts @@ -37,7 +37,7 @@ */ usb-hub { gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; + gpios = <8 0>; output-high; line-name = "rs485-rx-en"; }; @@ -65,7 +65,7 @@ */ usb-hub { gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; + gpios = <2 0>; output-high; line-name = "usb-hub-reset"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts index 7f5cff49b7..59d13713d8 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts @@ -37,7 +37,7 @@ */ usb-port-power { gpio-hog; - gpios = <13 GPIO_ACTIVE_LOW>; + gpios = <13 0>; output-low; line-name = "usb-port-power"; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index b612215f40..1de890c30f 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -23,6 +23,7 @@ serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; + ethernet0 = &gem1; }; chosen { @@ -40,6 +41,29 @@ status = "okay"; }; +&gem1 { + status = "okay"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ + rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ + txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ + txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ + rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ + rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ + rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ + rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ + rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ + txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ + txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ + txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ + txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ + }; + }; +}; + &qspi { status = "okay"; flash@0 { diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index f041df83da..21d62e993a 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -23,6 +23,7 @@ serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; + ethernet0 = &gem1; /* EMIO */ i2c = &i2c0; /* EMIO */ }; @@ -222,6 +223,28 @@ }; }; +&gem1 { + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ + rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ + txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ + txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ + rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ + rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ + rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ + rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ + rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ + txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ + txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ + txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ + txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ + }; + }; +}; + &qspi { status = "okay"; flash@0 { diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 1634af0bd8..aa0ac95e12 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -115,8 +115,10 @@ <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; - reg-names = "local_request_region", "local_response_region", - "remote_request_region", "remote_response_region"; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; @@ -145,15 +147,10 @@ firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; + #power-domain-cells = <1>; method = "smc"; - #power-domain-cells = <0x1>; u-boot,dm-pre-reloc; - zynqmp_pcap: pcap { - compatible = "xlnx,zynqmp-pcap-fpga"; - clock-names = "ref_clk"; - }; - zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; @@ -163,6 +160,11 @@ mbox-names = "tx", "rx"; }; + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + clock-names = "ref_clk"; + }; + zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; @@ -206,26 +208,7 @@ }; }; - amba_apu: amba-apu@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0 0xffffffff>; - - gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf9020000 0x20000>, - <0x0 0xf9040000 0x20000>, - <0x0 0xf9060000 0x20000>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; - }; - }; - - amba: amba { + amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; @@ -380,6 +363,18 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; + gic: interrupt-controller@f9010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + reg = <0x0 0xf9010000 0x0 0x10000>, + <0x0 0xf9020000 0x0 0x20000>, + <0x0 0xf9040000 0x0 0x20000>, + <0x0 0xf9060000 0x0 0x20000>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <1 9 0xf04>; + }; + gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; @@ -590,7 +585,7 @@ }; i2c0: i2c@ff020000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; @@ -601,7 +596,7 @@ }; i2c1: i2c@ff030000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; @@ -639,8 +634,8 @@ <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ + <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, @@ -770,7 +765,7 @@ clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; - smmu: smmu@fd800000 { + smmu: iommu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h index c5ee359a3a..12717a96aa 100644 --- a/arch/arm/include/asm/arch-hi6220/gpio.h +++ b/arch/arm/include/asm/arch-hi6220/gpio.h @@ -18,7 +18,7 @@ struct gpio_bank { }; /* Information about a GPIO bank */ -struct hikey_gpio_platdata { +struct hikey_gpio_plat { int bank_index; ulong base; /* address of registers in physical memory */ }; diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h index 1396008877..1db86a1209 100644 --- a/arch/arm/include/asm/arch-imx8/power-domain.h +++ b/arch/arm/include/asm/arch-imx8/power-domain.h @@ -8,7 +8,7 @@ #include <asm/arch/sci/types.h> -struct imx8_power_domain_platdata { +struct imx8_power_domain_plat { sc_rsrc_t resource_id; }; diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h index 0f94945894..7a833e564b 100644 --- a/arch/arm/include/asm/arch-imx8m/power-domain.h +++ b/arch/arm/include/asm/arch-imx8m/power-domain.h @@ -6,7 +6,7 @@ #ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H #define _ASM_ARCH_IMX8M_POWER_DOMAIN_H -struct imx8m_power_domain_platdata { +struct imx8m_power_domain_plat { int resource_id; int has_pd; struct power_domain pd; diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index 54c144afd8..46d0f0666c 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -15,6 +15,19 @@ tst x0, x0 // this is "b #0x84" in ARM b reset .space 0x7c + + .word 0xe28f0058 // add r0, pc, #88 + .word 0xe59f1054 // ldr r1, [pc, #84] + .word 0xe0800001 // add r0, r0, r1 + .word 0xe580d000 // str sp, [r0] + .word 0xe580e004 // str lr, [r0, #4] + .word 0xe10fe000 // mrs lr, CPSR + .word 0xe580e008 // str lr, [r0, #8] + .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0} + .word 0xe580e00c // str lr, [r0, #12] + .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} + .word 0xe580e010 // str lr, [r0, #16] + .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0 .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE .word 0xe5810000 // str r0, [r1] @@ -36,6 +49,7 @@ #else .word CONFIG_SYS_TEXT_BASE #endif + .word fel_stash - . #else /* normal execution */ b reset diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index 8c916e8c75..58cdf806d9 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -7,19 +7,7 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_ARCH_SPL_H_ -#define BOOT0_MAGIC "eGON.BT0" -#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ -#define SPL_MAJOR_BITS 3 -#define SPL_MINOR_BITS 5 -#define SPL_VERSION(maj, min) \ - ((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \ - ((min) & ((1U << SPL_MINOR_BITS) - 1))) - -#define SPL_HEADER_VERSION SPL_VERSION(0, 2) - -#define SPL_ENV_HEADER_VERSION SPL_VERSION(0, 1) -#define SPL_DT_HEADER_VERSION SPL_VERSION(0, 2) -#define SPL_DRAM_HEADER_VERSION SPL_VERSION(0, 3) +#include <sunxi_image.h> #define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS @@ -31,59 +19,7 @@ #define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10 #define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12 -/* boot head definition from sun4i boot code */ -struct boot_file_head { - uint32_t b_instruction; /* one intruction jumping to real code */ - uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ - uint32_t check_sum; /* generated by PC */ - uint32_t length; /* generated by PC */ - /* - * We use a simplified header, only filling in what is needed - * by the boot ROM. To be compatible with Allwinner tools we - * would need to implement the proper fields here instead of - * padding. - * - * Actually we want the ability to recognize our "sunxi" variant - * of the SPL. To do so, let's place a special signature into the - * "pub_head_size" field. We can reasonably expect Allwinner's - * boot0 to always have the upper 16 bits of this set to 0 (after - * all the value shouldn't be larger than the limit imposed by - * SRAM size). - * If the signature is present (at 0x14), then we know it's safe - * to use the remaining 8 bytes (at 0x18) for our own purposes. - * (E.g. sunxi-tools "fel" utility can pass information there.) - */ - union { - uint32_t pub_head_size; - uint8_t spl_signature[4]; - }; - uint32_t fel_script_address; /* since v0.1, set by sunxi-fel */ - /* - * If the fel_uEnv_length member below is set to a non-zero value, - * it specifies the size (byte count) of data at fel_script_address. - * At the same time this indicates that the data is in uEnv.txt - * compatible format, ready to be imported via "env import -t". - */ - uint32_t fel_uEnv_length; /* since v0.1, set by sunxi-fel */ - /* - * Offset of an ASCIIZ string (relative to the SPL header), which - * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE). - * This is optional and may be set to NULL. Is intended to be used - * by flash programming tools for providing nice informative messages - * to the users. - */ - uint32_t dt_name_offset; /* since v0.2, set by mksunxiboot */ - uint32_t dram_size; /* in MiB, since v0.3, set by SPL */ - uint32_t boot_media; /* written here by the boot ROM */ - /* A padding area (may be used for storing text strings) */ - uint32_t string_pool[13]; /* since v0.2, filled by mksunxiboot */ - /* The header must be a multiple of 32 bytes (for VBAR alignment) */ -}; - -/* Compile time check to assure proper alignment of structure */ -typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)]; - -#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) +#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0) uint32_t sunxi_get_boot_device(void); diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h index 9bfdf16873..0b9e10f51e 100644 --- a/arch/arm/include/asm/arch-vf610/gpio.h +++ b/arch/arm/include/asm/arch-vf610/gpio.h @@ -20,7 +20,7 @@ struct vybrid_gpio_regs { u32 gpio_pdir; }; -struct vybrid_gpio_platdata { +struct vybrid_gpio_plat { unsigned int chip; u32 base; const char *port_name; diff --git a/arch/arm/include/asm/mach-imx/mxc_i2c.h b/arch/arm/include/asm/mach-imx/mxc_i2c.h index 81fd981444..c016aa7474 100644 --- a/arch/arm/include/asm/mach-imx/mxc_i2c.h +++ b/arch/arm/include/asm/mach-imx/mxc_i2c.h @@ -42,7 +42,7 @@ struct mxc_i2c_bus { /* * board file can use this index to locate which i2c_pads_info is for * i2c_idle_bus. When pinmux is implement, this entry can be - * discarded. Here we do not use dev->seq, because we do not want to + * discarded. Here we do not use dev_seq(dev), because we do not want to * export device to board file. */ int index; diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h index 151afa8f44..4084210021 100644 --- a/arch/arm/include/asm/omap_gpio.h +++ b/arch/arm/include/asm/omap_gpio.h @@ -25,7 +25,7 @@ #if CONFIG_IS_ENABLED(DM_GPIO) /* Information about a GPIO bank */ -struct omap_gpio_platdata { +struct omap_gpio_plat { int bank_index; ulong base; /* address of registers in physical memory */ const char *port_name; diff --git a/arch/arm/include/asm/omap_i2c.h b/arch/arm/include/asm/omap_i2c.h index a6975401da..ec7a145f17 100644 --- a/arch/arm/include/asm/omap_i2c.h +++ b/arch/arm/include/asm/omap_i2c.h @@ -6,7 +6,7 @@ #ifdef CONFIG_DM_I2C /* Information about a GPIO bank */ -struct omap_i2c_platdata { +struct omap_i2c_plat { ulong base; /* address of registers in physical memory */ int speed; int ip_rev; diff --git a/arch/arm/include/asm/omap_musb.h b/arch/arm/include/asm/omap_musb.h index b40ea005be..614c93def8 100644 --- a/arch/arm/include/asm/omap_musb.h +++ b/arch/arm/include/asm/omap_musb.h @@ -23,7 +23,7 @@ struct omap_musb_board_data { enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; -struct ti_musb_platdata { +struct ti_musb_plat { void *base; void *ctrl_mod_base; struct musb_hdrc_platform_data plat; diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 02a49a8e10..fe46a7d7c9 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -63,7 +63,7 @@ int arch_fixup_fdt(void *blob) #endif #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \ - defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) + CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) ret = psci_update_dt(blob); if (ret) return ret; diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index a1657e3853..f5a921b3d1 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -43,10 +43,10 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv) int ret; ret = uclass_get_device_by_driver(UCLASS_IRQ, - DM_GET_DRIVER(arm_gic_v3_its), &dev); + DM_DRIVER_GET(arm_gic_v3_its), &dev); if (ret) { pr_err("%s: failed to get %s irq device\n", __func__, - DM_GET_DRIVER(arm_gic_v3_its)->name); + DM_DRIVER_GET(arm_gic_v3_its)->name); return ret; } @@ -74,17 +74,17 @@ static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv) int ret; ret = uclass_get_device_by_driver(UCLASS_SYSCON, - DM_GET_DRIVER(gic_lpi_syscon), &dev); + DM_DRIVER_GET(gic_lpi_syscon), &dev); if (ret) { pr_err("%s: failed to get %s syscon device\n", __func__, - DM_GET_DRIVER(gic_lpi_syscon)->name); + DM_DRIVER_GET(gic_lpi_syscon)->name); return ret; } regmap = syscon_get_regmap(dev); if (!regmap) { pr_err("%s: failed to regmap for %s syscon device\n", __func__, - DM_GET_DRIVER(gic_lpi_syscon)->name); + DM_DRIVER_GET(gic_lpi_syscon)->name); return -ENODEV; } priv->lpi_base = regmap->ranges[0].start; diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index 0ed29a43f1..903b335704 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -10,7 +10,7 @@ #include <linux/sizes.h> #include <linux/kernel.h> #include <asm/psci.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) #include <asm/armv8/sec_firmware.h> #endif @@ -64,7 +64,7 @@ int fdt_psci(void *fdt) return nodeoff; init_psci_node: -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) psci_ver = sec_firmware_support_psci_version(); #elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI) psci_ver = ARM_PSCI_VER_1_0; @@ -85,7 +85,7 @@ init_psci_node: return tmp; } -#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if !CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) /* * The Secure firmware framework isn't able to support PSCI version 0.1. */ diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c index 3e9f5e57ed..02bd3f67c9 100644 --- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c @@ -12,7 +12,7 @@ int ast_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(aspeed_ast2500_scu), devp); + DM_DRIVER_GET(aspeed_ast2500_scu), devp); } void *ast_get_scu(void) diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index 8122d2f98e..c10571fa28 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -213,13 +213,13 @@ void at91_sdram_hw_init(void) } /* Platform data for the GPIOs */ -static const struct at91_port_platdata at91sam9260_plat[] = { +static const struct at91_port_plat at91sam9260_plat[] = { { ATMEL_BASE_PIOA, "PA" }, { ATMEL_BASE_PIOB, "PB" }, { ATMEL_BASE_PIOC, "PC" }, }; -U_BOOT_DEVICES(at91sam9260_gpios) = { +U_BOOT_DRVINFOS(at91sam9260_gpios) = { { "atmel_at91rm9200_gpio", &at91sam9260_plat[0] }, { "atmel_at91rm9200_gpio", &at91sam9260_plat[1] }, { "atmel_at91rm9200_gpio", &at91sam9260_plat[2] }, diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index 08ca3edd78..d517810c99 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -167,7 +167,7 @@ void at91_mci_hw_init(void) #endif /* Platform data for the GPIOs */ -static const struct at91_port_platdata at91sam9260_plat[] = { +static const struct at91_port_plat at91sam9260_plat[] = { { ATMEL_BASE_PIOA, "PA" }, { ATMEL_BASE_PIOB, "PB" }, { ATMEL_BASE_PIOC, "PC" }, @@ -175,7 +175,7 @@ static const struct at91_port_platdata at91sam9260_plat[] = { { ATMEL_BASE_PIOE, "PE" }, }; -U_BOOT_DEVICES(at91sam9260_gpios) = { +U_BOOT_DRVINFOS(at91sam9260_gpios) = { { "atmel_at91rm9200_gpio", &at91sam9260_plat[0] }, { "atmel_at91rm9200_gpio", &at91sam9260_plat[1] }, { "atmel_at91rm9200_gpio", &at91sam9260_plat[2] }, diff --git a/arch/arm/mach-at91/include/mach/atmel_serial.h b/arch/arm/mach-at91/include/mach/atmel_serial.h index c53a509ff8..5d14269364 100644 --- a/arch/arm/mach-at91/include/mach/atmel_serial.h +++ b/arch/arm/mach-at91/include/mach/atmel_serial.h @@ -7,7 +7,7 @@ #define _ATMEL_SERIAL_H /* Information about a serial port */ -struct atmel_serial_platdata { +struct atmel_serial_plat { uint32_t base_addr; }; diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 575c6436ad..c1aef798b1 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -253,7 +253,7 @@ static inline unsigned at91_gpio_to_pin(unsigned gpio) } /* Platform data for each GPIO port */ -struct at91_port_platdata { +struct at91_port_plat { uint32_t base_addr; const char *bank_name; }; diff --git a/arch/arm/mach-bcm283x/include/mach/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h index 3263de9a35..4aeb48eeb2 100644 --- a/arch/arm/mach-bcm283x/include/mach/gpio.h +++ b/arch/arm/mach-bcm283x/include/mach/gpio.h @@ -52,11 +52,11 @@ struct bcm2835_gpio_regs { }; /** - * struct bcm2835_gpio_platdata - GPIO platform description + * struct bcm2835_gpio_plat - GPIO platform description * * @base: Base address of GPIO controller */ -struct bcm2835_gpio_platdata { +struct bcm2835_gpio_plat { unsigned long base; }; diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 07bf19b5e4..759c93747c 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -290,8 +290,8 @@ int arch_cpu_init(void) board_gpio_init(); #if !CONFIG_IS_ENABLED(DM_SERIAL) - NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif /* * Fix Power and Emulation Management Register diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 5fea935d6e..d0d7a81471 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -27,9 +27,9 @@ void puts(const char *str) void putc(char c) { if (c == '\n') - NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r'); + ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r'); - NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c); + ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c); } #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 4bb7c46921..600a1108ce 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -303,10 +303,11 @@ static int confirm_close(void) static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + int confirmed = argc >= 2 && !strcmp(argv[1], "-y"); int err; u16 lc; - if (!confirm_close()) + if (!confirmed && !confirm_close()) return -EACCES; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index f43a2460f9..bf6dddfdc9 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -44,9 +44,9 @@ static const struct imx_thermal_plat imx6_thermal_plat = { .fuse_word = 6, }; -U_BOOT_DEVICE(imx6_thermal) = { +U_BOOT_DRVINFO(imx6_thermal) = { .name = "imx_thermal", - .platdata = &imx6_thermal_plat, + .plat = &imx6_thermal_plat, }; #endif diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index aba9461d92..6a1bad855e 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -916,7 +916,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } if (5 == i) { - printf("Fail to set rate to %dkhz", freq); + printf("Fail to set rate to %u kHz", freq); return; } } @@ -936,7 +936,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } if (best == 0) { - printf("Fail to set rate to %dkhz", freq); + printf("Fail to set rate to %u kHz", freq); return; } @@ -1115,17 +1115,17 @@ int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, printf("\n"); - printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); - printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); + printf("IPG %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); + printf("UART %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); #ifdef CONFIG_MXC_SPI - printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); + printf("CSPI %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); #endif - printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); - printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); - printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); - printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); - printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); - printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); + printf("AHB %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); + printf("AXI %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); + printf("DDR %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + printf("USDHC1 %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); + printf("USDHC2 %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); + printf("USDHC3 %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); return 0; } diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index d0385b36e4..fda25ba66a 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -60,9 +60,9 @@ static const struct imx_thermal_plat imx7_thermal_plat = { .fuse_word = 3, }; -U_BOOT_DEVICE(imx7_thermal) = { +U_BOOT_DRVINFO(imx7_thermal) = { .name = "imx_thermal", - .platdata = &imx7_thermal_plat, + .plat = &imx7_thermal_plat, }; #endif diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c index 31ae9719e8..c1d5c4ecdd 100644 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c @@ -8,8 +8,8 @@ * */ -#include <common.h> #include <clk-uclass.h> +#include <common.h> #include <dm.h> #include <errno.h> @@ -25,9 +25,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ return 0; - break; default: - return 0; + return -EINVAL; } } @@ -35,7 +34,7 @@ static int msm_clk_probe(struct udevice *dev) { struct msm_clk_priv *priv = dev_get_priv(dev); - priv->base = devfdt_get_addr(dev); + priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; @@ -53,13 +52,19 @@ static int msm_enable(struct clk *clk) case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ /* This clock is already initialized by SBL1 */ return 0; - break; case GCC_PRNG_AHB_CLK: /*PRNG*/ /* This clock is already initialized by SBL1 */ return 0; - break; - default: + case GCC_USB3_MASTER_CLK: + case GCC_USB3_SLEEP_CLK: + case GCC_USB3_MOCK_UTMI_CLK: + case GCC_USB2_MASTER_CLK: + case GCC_USB2_SLEEP_CLK: + case GCC_USB2_MOCK_UTMI_CLK: + /* These clocks is already initialized by SBL1 */ return 0; + default: + return -EINVAL; } } @@ -78,6 +83,6 @@ U_BOOT_DRIVER(clk_msm) = { .id = UCLASS_CLK, .of_match = msm_clk_ids, .ops = &msm_clk_ops, - .priv_auto_alloc_size = sizeof(struct msm_clk_priv), + .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, }; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c index 64b8b049fa..c51a75ee94 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c +++ b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c @@ -131,7 +131,7 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = { .name = "pinctrl_msm", .id = UCLASS_PINCTRL, .of_match = msm_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv), + .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, }; diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 603834e507..dea470c02f 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -208,7 +208,7 @@ void board_init_f(ulong dummy) * firmware (SYSFW) image for various purposes and SYSFW depends on us * to initialize its pin settings. */ - ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev); + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); if (!ret) pinctrl_select_state(dev, "default"); @@ -238,7 +238,7 @@ void board_init_f(ulong dummy) do_board_detect(); #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) - ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs), + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), &dev); if (ret) printf("AVS init failed: %d\n", ret); diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 8c903f14ff..8b54e0cf52 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -33,7 +33,7 @@ struct ti_sci_handle *get_ti_sci_handle(void) int ret; ret = uclass_get_device_by_driver(UCLASS_FIRMWARE, - DM_GET_DRIVER(ti_sci), &dev); + DM_DRIVER_GET(ti_sci), &dev); if (ret) panic("Failed to get SYSFW (%d)\n", ret); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index a36e4ed603..1a4f796e5e 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -167,7 +167,7 @@ void board_init_f(ulong dummy) * firmware (SYSFW) image for various purposes and SYSFW depends on us * to initialize its pin settings. */ - ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev); + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); if (!ret) pinctrl_select_state(dev, "default"); @@ -206,7 +206,7 @@ void board_init_f(ulong dummy) do_board_detect(); #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) - ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs), + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), &dev); if (ret) printf("AVS init failed: %d\n", ret); diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 78c158c63f..708d9c8508 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -223,7 +223,7 @@ static void *k3_sysfw_get_spi_addr(void) int ret; ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS, - true, &dev); + &dev); if (ret) return NULL; diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 88e8912959..4950f14655 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -185,7 +185,7 @@ int arch_cpu_init(void) * driver doesn't handle this. */ #ifndef CONFIG_DM_SERIAL - NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2), + ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 7e7646a2e1..e1e2e0d094 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -43,7 +43,7 @@ void lpc32xx_uart_init(unsigned int uart_id) } #if !CONFIG_IS_ENABLED(OF_CONTROL) -static const struct ns16550_platdata lpc32xx_uart[] = { +static const struct ns16550_plat lpc32xx_uart[] = { { .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART4_BASE, .reg_shift = 2, @@ -55,14 +55,14 @@ static const struct ns16550_platdata lpc32xx_uart[] = { }; #if defined(CONFIG_LPC32XX_HSUART) -static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = { +static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = { { HS_UART1_BASE, }, { HS_UART2_BASE, }, { HS_UART7_BASE, }, }; #endif -U_BOOT_DEVICES(lpc32xx_uarts) = { +U_BOOT_DRVINFOS(lpc32xx_uarts) = { #if defined(CONFIG_LPC32XX_HSUART) { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, @@ -124,7 +124,7 @@ void lpc32xx_i2c_init(unsigned int devnum) writel(ctrl, &clk->i2cclk_ctrl); } -U_BOOT_DEVICE(lpc32xx_gpios) = { +U_BOOT_DRVINFO(lpc32xx_gpios) = { .name = "gpio_lpc32xx" }; diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c index c260413a57..1f102dddd4 100644 --- a/arch/arm/mach-mediatek/mt7629/init.c +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -40,7 +40,7 @@ int mtk_pll_early_init(void) int ret, i; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(mtk_clk_apmixedsys), &dev); + DM_DRIVER_GET(mtk_clk_apmixedsys), &dev); if (ret) return ret; @@ -59,7 +59,7 @@ int mtk_pll_early_init(void) /* setup mcu bus */ ret = uclass_get_device_by_driver(UCLASS_SYSCON, - DM_GET_DRIVER(mtk_mcucfg), &dev); + DM_DRIVER_GET(mtk_mcucfg), &dev); if (ret) return ret; diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 13be391221..2ffa5595cf 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -52,7 +52,7 @@ int mtk_pll_early_init(void) int ret, i; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(mtk_clk_apmixedsys), &dev); + DM_DRIVER_GET(mtk_clk_apmixedsys), &dev); if (ret) return ret; diff --git a/arch/arm/mach-nexell/include/mach/display.h b/arch/arm/mach-nexell/include/mach/display.h index b167e63a5a..b0ee912605 100644 --- a/arch/arm/mach-nexell/include/mach/display.h +++ b/arch/arm/mach-nexell/include/mach/display.h @@ -212,7 +212,7 @@ struct dp_hdmi_dev { }; /* platform data for the driver model */ -struct nx_display_platdata { +struct nx_display_plat { int module; struct dp_sync_info sync; struct dp_ctrl_info ctrl; @@ -267,7 +267,7 @@ int dp_plane_wait_vsync(int module, int layer, int fps); #if defined CONFIG_SPL_BUILD || \ (!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)) -int nx_display_probe(struct nx_display_platdata *plat); +int nx_display_probe(struct nx_display_plat *plat); #endif #endif diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 2888390d24..e17898d8fb 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -80,7 +80,7 @@ int dram_init_banksize(void) } #if !CONFIG_IS_ENABLED(OF_CONTROL) -static const struct ns16550_platdata am33xx_serial[] = { +static const struct ns16550_plat am33xx_serial[] = { { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # ifdef CONFIG_SYS_NS16550_COM2 @@ -99,7 +99,7 @@ static const struct ns16550_platdata am33xx_serial[] = { # endif }; -U_BOOT_DEVICES(am33xx_uarts) = { +U_BOOT_DRVINFOS(am33xx_uarts) = { { "ns16550_serial", &am33xx_serial[0] }, # ifdef CONFIG_SYS_NS16550_COM2 { "ns16550_serial", &am33xx_serial[1] }, @@ -113,13 +113,13 @@ U_BOOT_DEVICES(am33xx_uarts) = { }; #ifdef CONFIG_DM_I2C -static const struct omap_i2c_platdata am33xx_i2c[] = { +static const struct omap_i2c_plat am33xx_i2c[] = { { I2C_BASE1, 100000, OMAP_I2C_REV_V2}, { I2C_BASE2, 100000, OMAP_I2C_REV_V2}, { I2C_BASE3, 100000, OMAP_I2C_REV_V2}, }; -U_BOOT_DEVICES(am33xx_i2c) = { +U_BOOT_DRVINFOS(am33xx_i2c) = { { "i2c_omap", &am33xx_i2c[0] }, { "i2c_omap", &am33xx_i2c[1] }, { "i2c_omap", &am33xx_i2c[2] }, @@ -127,7 +127,7 @@ U_BOOT_DEVICES(am33xx_i2c) = { #endif #if CONFIG_IS_ENABLED(DM_GPIO) -static const struct omap_gpio_platdata am33xx_gpio[] = { +static const struct omap_gpio_plat am33xx_gpio[] = { { 0, AM33XX_GPIO0_BASE }, { 1, AM33XX_GPIO1_BASE }, { 2, AM33XX_GPIO2_BASE }, @@ -138,7 +138,7 @@ static const struct omap_gpio_platdata am33xx_gpio[] = { #endif }; -U_BOOT_DEVICES(am33xx_gpios) = { +U_BOOT_DRVINFOS(am33xx_gpios) = { { "gpio_omap", &am33xx_gpio[0] }, { "gpio_omap", &am33xx_gpio[1] }, { "gpio_omap", &am33xx_gpio[2] }, @@ -155,9 +155,9 @@ static const struct omap3_spi_plat omap3_spi_pdata = { .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT, }; -U_BOOT_DEVICE(am33xx_spi) = { +U_BOOT_DRVINFO(am33xx_spi) = { .name = "omap3_spi", - .platdata = &omap3_spi_pdata, + .plat = &omap3_spi_pdata, }; #endif #endif @@ -214,7 +214,7 @@ static struct musb_hdrc_config musb_config = { }; #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL) -static struct ti_musb_platdata usb0 = { +static struct ti_musb_plat usb0 = { .base = (void *)USB0_OTG_BASE, .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0, .plat = { @@ -224,7 +224,7 @@ static struct ti_musb_platdata usb0 = { }, }; -static struct ti_musb_platdata usb1 = { +static struct ti_musb_plat usb1 = { .base = (void *)USB1_OTG_BASE, .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1, .plat = { @@ -234,7 +234,7 @@ static struct ti_musb_platdata usb1 = { }, }; -U_BOOT_DEVICES(am33xx_usbs) = { +U_BOOT_DRVINFOS(am33xx_usbs) = { #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL { "ti-musb-peripheral", &usb0 }, #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index f08c8ab43a..4da8df47cc 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -38,7 +38,7 @@ static void omap3_invalidate_l2_cache_secure(void); #if CONFIG_IS_ENABLED(DM_GPIO) #if !CONFIG_IS_ENABLED(OF_CONTROL) /* Manually initialize GPIO banks when OF_CONTROL doesn't */ -static const struct omap_gpio_platdata omap34xx_gpio[] = { +static const struct omap_gpio_plat omap34xx_gpio[] = { { 0, OMAP34XX_GPIO1_BASE }, { 1, OMAP34XX_GPIO2_BASE }, { 2, OMAP34XX_GPIO3_BASE }, @@ -47,7 +47,7 @@ static const struct omap_gpio_platdata omap34xx_gpio[] = { { 5, OMAP34XX_GPIO6_BASE }, }; -U_BOOT_DEVICES(omap34xx_gpios) = { +U_BOOT_DRVINFOS(omap34xx_gpios) = { { "gpio_omap", &omap34xx_gpio[0] }, { "gpio_omap", &omap34xx_gpio[1] }, { "gpio_omap", &omap34xx_gpio[2] }, diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig index 588d2d3102..186c3582eb 100644 --- a/arch/arm/mach-qemu/Kconfig +++ b/arch/arm/mach-qemu/Kconfig @@ -16,12 +16,14 @@ choice config TARGET_QEMU_ARM_32BIT bool "ARMv7-A, 32bit" select ARCH_SUPPORT_PSCI + select BOARD_LATE_INIT select CPU_V7A select SYS_ARCH_TIMER config TARGET_QEMU_ARM_64BIT bool "ARMv8, 64bit" select ARM64 + select BOARD_LATE_INIT endchoice diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c index 28c7c7214c..87eebd9872 100644 --- a/arch/arm/mach-rockchip/misc.c +++ b/arch/arm/mach-rockchip/misc.c @@ -67,10 +67,10 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset, /* retrieve the device */ #if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(rockchip_efuse), &dev); + DM_DRIVER_GET(rockchip_efuse), &dev); #elif CONFIG_IS_ENABLED(ROCKCHIP_OTP) ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(rockchip_otp), &dev); + DM_DRIVER_GET(rockchip_otp), &dev); #endif if (ret) { debug("%s: could not find efuse device\n", __func__); diff --git a/arch/arm/mach-rockchip/px30/clk_px30.c b/arch/arm/mach-rockchip/px30/clk_px30.c index 98a1bcd224..7edf1321fe 100644 --- a/arch/arm/mach-rockchip/px30/clk_px30.c +++ b/arch/arm/mach-rockchip/px30/clk_px30.c @@ -13,7 +13,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_px30_cru), devp); + DM_DRIVER_GET(rockchip_px30_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c b/arch/arm/mach-rockchip/px30/syscon_px30.c index 4672bdbf00..37e88f5ccb 100644 --- a/arch/arm/mach-rockchip/px30/syscon_px30.c +++ b/arch/arm/mach-rockchip/px30/syscon_px30.c @@ -23,7 +23,7 @@ U_BOOT_DRIVER(syscon_px30) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int px30_syscon_bind_of_platdata(struct udevice *dev) +static int px30_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -35,20 +35,20 @@ U_BOOT_DRIVER(rockchip_px30_pmu) = { .name = "rockchip_px30_pmu", .id = UCLASS_SYSCON, .of_match = px30_syscon_ids, - .bind = px30_syscon_bind_of_platdata, + .bind = px30_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_px30_pmugrf) = { .name = "rockchip_px30_pmugrf", .id = UCLASS_SYSCON, .of_match = px30_syscon_ids + 1, - .bind = px30_syscon_bind_of_platdata, + .bind = px30_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_px30_grf) = { .name = "rockchip_px30_grf", .id = UCLASS_SYSCON, .of_match = px30_syscon_ids + 2, - .bind = px30_syscon_bind_of_platdata, + .bind = px30_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c index 5d0def3b52..116dccd7b8 100644 --- a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c @@ -14,7 +14,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3036_cru), devp); + DM_DRIVER_GET(rockchip_rk3036_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c index f9ce1f7234..a1b038c648 100644 --- a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -13,7 +13,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3128_cru), devp); + DM_DRIVER_GET(rockchip_rk3128_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c index a0dcac3732..94d1d23e1f 100644 --- a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -14,7 +14,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3188_cru), devp); + DM_DRIVER_GET(rockchip_rk3188_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c index ea7d7b5b1a..917ff37c0f 100644 --- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -24,7 +24,7 @@ U_BOOT_DRIVER(syscon_rk3188) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3188_syscon_bind_of_platdata(struct udevice *dev) +static int rk3188_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -36,20 +36,20 @@ U_BOOT_DRIVER(rockchip_rk3188_noc) = { .name = "rockchip_rk3188_noc", .id = UCLASS_SYSCON, .of_match = rk3188_syscon_ids, - .bind = rk3188_syscon_bind_of_platdata, + .bind = rk3188_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3188_grf) = { .name = "rockchip_rk3188_grf", .id = UCLASS_SYSCON, .of_match = rk3188_syscon_ids + 1, - .bind = rk3188_syscon_bind_of_platdata, + .bind = rk3188_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3188_pmu) = { .name = "rockchip_rk3188_pmu", .id = UCLASS_SYSCON, .of_match = rk3188_syscon_ids + 2, - .bind = rk3188_syscon_bind_of_platdata, + .bind = rk3188_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c index fc5abd736e..2e57672b24 100644 --- a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c @@ -13,7 +13,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk322x_cru), devp); + DM_DRIVER_GET(rockchip_rk322x_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index e05bd06a8d..fb4c0891d0 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -14,7 +14,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3288_cru), devp); + DM_DRIVER_GET(rockchip_rk3288_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index e3da0a0194..9c1ae880c7 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -25,7 +25,7 @@ U_BOOT_DRIVER(syscon_rk3288) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3288_syscon_bind_of_platdata(struct udevice *dev) +static int rk3288_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -37,27 +37,27 @@ U_BOOT_DRIVER(rockchip_rk3288_noc) = { .name = "rockchip_rk3288_noc", .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids, - .bind = rk3288_syscon_bind_of_platdata, + .bind = rk3288_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3288_grf) = { .name = "rockchip_rk3288_grf", .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids + 1, - .bind = rk3288_syscon_bind_of_platdata, + .bind = rk3288_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3288_sgrf) = { .name = "rockchip_rk3288_sgrf", .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids + 2, - .bind = rk3288_syscon_bind_of_platdata, + .bind = rk3288_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3288_pmu) = { .name = "rockchip_rk3288_pmu", .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids + 3, - .bind = rk3288_syscon_bind_of_platdata, + .bind = rk3288_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c index 1feb237224..ccda53380c 100644 --- a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c @@ -13,7 +13,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3308_cru), devp); + DM_DRIVER_GET(rockchip_rk3308_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c index e5375514de..70c0eb6f98 100644 --- a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -12,7 +12,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3328_cru), devp); + DM_DRIVER_GET(rockchip_rk3328_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c index 9a33c67bc9..b075319720 100644 --- a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -14,7 +14,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3368_cru), devp); + DM_DRIVER_GET(rockchip_rk3368_cru), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index cba0dda3e8..dc2d831dd8 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -30,7 +30,7 @@ U_BOOT_DRIVER(syscon_rk3368) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3368_syscon_bind_of_platdata(struct udevice *dev) +static int rk3368_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -42,27 +42,27 @@ U_BOOT_DRIVER(rockchip_rk3368_grf) = { .name = "rockchip_rk3368_grf", .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids, - .bind = rk3368_syscon_bind_of_platdata, + .bind = rk3368_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = { .name = "rockchip_rk3368_pmugrf", .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids + 1, - .bind = rk3368_syscon_bind_of_platdata, + .bind = rk3368_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3368_msch) = { .name = "rockchip_rk3368_msch", .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids + 2, - .bind = rk3368_syscon_bind_of_platdata, + .bind = rk3368_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3368_sgrf) = { .name = "rockchip_rk3368_sgrf", .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids + 3, - .bind = rk3368_syscon_bind_of_platdata, + .bind = rk3368_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index d23a5e9435..9d9a837fc7 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -14,7 +14,7 @@ static int rockchip_get_cruclk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(clk_rk3399), devp); + DM_DRIVER_GET(clk_rk3399), devp); } void *rockchip_get_cru(void) @@ -35,7 +35,7 @@ void *rockchip_get_cru(void) static int rockchip_get_pmucruclk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp); + DM_DRIVER_GET(rockchip_rk3399_pmuclk), devp); } void *rockchip_get_pmucru(void) diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 690cbe7f27..b360ca7dde 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -28,7 +28,7 @@ U_BOOT_DRIVER(syscon_rk3399) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3399_syscon_bind_of_platdata(struct udevice *dev) +static int rk3399_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -40,34 +40,34 @@ U_BOOT_DRIVER(rockchip_rk3399_grf) = { .name = "rockchip_rk3399_grf", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = { .name = "rockchip_rk3399_pmugrf", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids + 1, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = { .name = "rockchip_rk3399_pmusgrf", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids + 2, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3399_cic) = { .name = "rockchip_rk3399_cic", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids + 3, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3399_pmu) = { .name = "rockchip_rk3399_pmu", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids + 4, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c index b37ae1c494..44b53c407a 100644 --- a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c @@ -14,7 +14,7 @@ int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(clk_rv1108), devp); + DM_DRIVER_GET(clk_rv1108), devp); } void *rockchip_get_cru(void) diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 94673f34c9..8ccd5afb56 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -46,7 +46,7 @@ static int spl_node_to_boot_device(int node) dev; device_find_next_child(&dev)) { if (device_get_uclass_id(dev) == UCLASS_BLK) { - desc = dev_get_uclass_platdata(dev); + desc = dev_get_uclass_plat(dev); break; } } @@ -99,7 +99,7 @@ __weak const char *board_spl_was_booted_from(void) void board_boot_order(u32 *spl_boot_list) { - /* In case of no fdt (or only platdata), use spl_boot_device() */ + /* In case of no fdt (or only plat), use spl_boot_device() */ if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) { spl_boot_list[0] = spl_boot_device(); return; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 69d65c82e3..fbe0b5212f 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -143,6 +143,6 @@ U_BOOT_DRIVER(clk_msm) = { .id = UCLASS_CLK, .of_match = msm_clk_ids, .ops = &msm_clk_ops, - .priv_auto_alloc_size = sizeof(struct msm_clk_priv), + .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index 4c2af21308..e6b87c3573 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -123,7 +123,7 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = { .name = "pinctrl_msm", .id = UCLASS_PINCTRL, .of_match = msm_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv), + .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, }; diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 6188a8c3d2..a960176da7 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -24,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id) int ret; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(socfpga_agilex_clk), + DM_DRIVER_GET(socfpga_agilex_clk), &dev); if (ret) return 0; diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index a9b9bd0902..84e0bddcd4 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -280,13 +280,13 @@ static int bsec_program_otp(long base, u32 val, u32 otp) } /* BSEC MISC driver *******************************************************/ -struct stm32mp_bsec_platdata { +struct stm32mp_bsec_plat { u32 base; }; static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) { - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; u32 tmp_data = 0; int ret; @@ -295,7 +295,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) STM32_SMC_READ_OTP, otp, 0, val); - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); /* read current shadow value */ ret = bsec_read_shadow(plat->base, &tmp_data, otp); @@ -319,21 +319,21 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) { - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; if (IS_ENABLED(CONFIG_TFABOOT)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_SHADOW, otp, 0, val); - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); return bsec_read_shadow(plat->base, val, otp); } static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) { - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_plat *plat = dev_get_plat(dev); /* return OTP permanent write lock status */ *val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp); @@ -343,14 +343,14 @@ static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) { - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; if (IS_ENABLED(CONFIG_TFABOOT)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_PROG_OTP, otp, val); - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); return bsec_program_otp(plat->base, val, otp); @@ -358,14 +358,14 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) { - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; if (IS_ENABLED(CONFIG_TFABOOT)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRITE_SHADOW, otp, val); - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); return bsec_write_shadow(plat->base, val, otp); } @@ -473,9 +473,9 @@ static const struct misc_ops stm32mp_bsec_ops = { .write = stm32mp_bsec_write, }; -static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev) +static int stm32mp_bsec_of_to_plat(struct udevice *dev) { - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_plat *plat = dev_get_plat(dev); plat->base = (u32)dev_read_addr_ptr(dev); @@ -485,7 +485,7 @@ static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev) static int stm32mp_bsec_probe(struct udevice *dev) { int otp; - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; /* * update unlocked shadow for OTP cleared by the rom code @@ -493,7 +493,7 @@ static int stm32mp_bsec_probe(struct udevice *dev) */ if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) { - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++) if (!bsec_read_SR_lock(plat->base, otp)) @@ -512,8 +512,8 @@ U_BOOT_DRIVER(stm32mp_bsec) = { .name = "stm32mp_bsec", .id = UCLASS_MISC, .of_match = stm32mp_bsec_ids, - .ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata), + .of_to_plat = stm32mp_bsec_of_to_plat, + .plat_auto = sizeof(struct stm32mp_bsec_plat), .ops = &stm32mp_bsec_ops, .probe = stm32mp_bsec_probe, }; @@ -521,17 +521,17 @@ U_BOOT_DRIVER(stm32mp_bsec) = { bool bsec_dbgswenable(void) { struct udevice *dev; - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; int ret; ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stm32mp_bsec), &dev); + DM_DRIVER_GET(stm32mp_bsec), &dev); if (ret || !dev) { pr_debug("bsec driver not available\n"); return false; } - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE) return true; diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index f191085a12..544bab3848 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -31,7 +31,7 @@ static void fuse_hash_value(u32 addr, bool print) int i, ret; ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stm32mp_bsec), + DM_DRIVER_GET(stm32mp_bsec), &dev); if (ret) { pr_err("Can't find stm32mp_bsec driver\n"); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index a777827c55..fc9a2af545 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1340,7 +1340,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer, pr_debug("%s: %x %lx\n", __func__, offset, *size); ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stpmic1_nvm), + DM_DRIVER_GET(stpmic1_nvm), &dev); if (ret) return ret; @@ -1351,7 +1351,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer, memset(data->pmic_part, 0, PMIC_SIZE); ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stpmic1_nvm), + DM_DRIVER_GET(stpmic1_nvm), &dev); if (ret) return ret; @@ -1389,7 +1389,7 @@ int stm32prog_pmic_start(struct stm32prog_data *data) } ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stpmic1_nvm), + DM_DRIVER_GET(stpmic1_nvm), &dev); if (ret) return ret; diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 1520c6eaed..29c0d92195 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -318,7 +318,7 @@ static u32 get_otp(int index, int shift, int mask) u32 otp = 0; ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stm32mp_bsec), + DM_DRIVER_GET(stm32mp_bsec), &dev); if (!ret) @@ -563,7 +563,7 @@ __weak int setup_mac_address(void) return 0; ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stm32mp_bsec), + DM_DRIVER_GET(stm32mp_bsec), &dev); if (ret) return ret; @@ -601,7 +601,7 @@ static int setup_serial_number(void) return 0; ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(stm32mp_bsec), + DM_DRIVER_GET(stm32mp_bsec), &dev); if (ret) return ret; diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/pwr_regulator.c index 900dee4c38..766ed95f1a 100644 --- a/arch/arm/mach-stm32mp/pwr_regulator.c +++ b/arch/arm/mach-stm32mp/pwr_regulator.c @@ -9,6 +9,7 @@ #include <syscon.h> #include <asm/io.h> #include <dm/device_compat.h> +#include <dm/device-internal.h> #include <linux/bitops.h> #include <linux/err.h> #include <power/pmic.h> @@ -59,7 +60,7 @@ static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff, return 0; } -static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev) +static int stm32mp_pwr_of_to_plat(struct udevice *dev) { struct stm32mp_pwr_priv *priv = dev_get_priv(dev); @@ -80,7 +81,7 @@ static int stm32mp_pwr_bind(struct udevice *dev) { int children; - children = pmic_bind_children(dev, dev->node, pwr_children_info); + children = pmic_bind_children(dev, dev_ofnode(dev), pwr_children_info); if (!children) dev_dbg(dev, "no child found\n"); @@ -103,8 +104,8 @@ U_BOOT_DRIVER(stm32mp_pwr_pmic) = { .of_match = stm32mp_pwr_ids, .bind = stm32mp_pwr_bind, .ops = &stm32mp_pwr_ops, - .ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata, - .priv_auto_alloc_size = sizeof(struct stm32mp_pwr_priv), + .of_to_plat = stm32mp_pwr_of_to_plat, + .priv_auto = sizeof(struct stm32mp_pwr_priv), }; static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = { @@ -135,9 +136,9 @@ static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = { static int stm32mp_pwr_regulator_probe(struct udevice *dev) { const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos; - struct dm_regulator_uclass_platdata *uc_pdata; + struct dm_regulator_uclass_plat *uc_pdata; - uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata = dev_get_uclass_plat(dev); while (*p) { int rc; @@ -165,16 +166,16 @@ static int stm32mp_pwr_regulator_probe(struct udevice *dev) } uc_pdata->type = REGULATOR_TYPE_FIXED; - dev->priv = (void *)*p; + dev_set_priv(dev, (void *)*p); return 0; } static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV) { - struct dm_regulator_uclass_platdata *uc_pdata; + struct dm_regulator_uclass_plat *uc_pdata; - uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata) return -ENXIO; @@ -188,9 +189,9 @@ static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV) static int stm32mp_pwr_regulator_get_value(struct udevice *dev) { - struct dm_regulator_uclass_platdata *uc_pdata; + struct dm_regulator_uclass_plat *uc_pdata; - uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata) return -ENXIO; diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 49ef217f08..11e6445192 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1016,4 +1016,15 @@ config PINEPHONE_DT_SELECTION Enable this option to automatically select the device tree for the correct PinePhone hardware revision during boot. +config BLUETOOTH_DT_DEVICE_FIXUP + string "Fixup the Bluetooth controller address" + default "" + help + This option specifies the DT compatible name of the Bluetooth + controller for which to set the "local-bd-address" property. + Set this option if your device ships with the Bluetooth controller + default address. + The used address is "bdaddr" if set, and "ethaddr" with the LSB + flipped elsewise. + endif diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 9e34da4747..32ec0bc4cd 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -37,9 +37,9 @@ static void mctl_sys_init(struct dram_para *para); static void mctl_com_init(struct dram_para *para); -static void mctl_channel_init(struct dram_para *para); +static bool mctl_channel_init(struct dram_para *para); -static void mctl_core_init(struct dram_para *para) +static bool mctl_core_init(struct dram_para *para) { mctl_sys_init(para); mctl_com_init(para); @@ -51,7 +51,7 @@ static void mctl_core_init(struct dram_para *para) default: panic("Unsupported DRAM type!"); }; - mctl_channel_init(para); + return mctl_channel_init(para); } /* PHY initialisation */ @@ -411,7 +411,7 @@ static void mctl_bit_delay_set(struct dram_para *para) } } -static void mctl_channel_init(struct dram_para *para) +static bool mctl_channel_init(struct dram_para *para) { struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; @@ -528,46 +528,15 @@ static void mctl_channel_init(struct dram_para *para) clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); udelay(10); - if (readl(&mctl_phy->pgsr[0]) & 0x400000) - { - /* Check for single rank and optionally half DQ. */ - if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) { - para->ranks = 1; - - if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 || - (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2) - para->bus_full_width = 0; - - /* Restart DRAM initialization from scratch. */ - mctl_core_init(para); - return; - } - - /* - * Check for dual rank and half DQ. NOTE: This combination - * is highly unlikely and was not tested. Condition is the - * same as in libdram, though. - */ - if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 && - (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) { - para->bus_full_width = 0; - - /* Restart DRAM initialization from scratch. */ - mctl_core_init(para); - return; - } - - panic("This DRAM setup is currently not supported.\n"); - } - if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { /* Oops! There's something wrong! */ debug("PLL = %x\n", readl(0x3001010)); debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0])); for (i = 0; i < 4; i++) debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0])); - panic("Error while initializing DRAM PHY!\n"); + debug("Error while initializing DRAM PHY!\n"); + + return false; } if (sunxi_dram_is_lpddr(para->type)) @@ -582,13 +551,59 @@ static void mctl_channel_init(struct dram_para *para) writel(0xffffffff, &mctl_com->maer0); writel(0x7ff, &mctl_com->maer1); writel(0xffff, &mctl_com->maer2); + + return true; +} + +static void mctl_auto_detect_rank_width(struct dram_para *para) +{ + /* this is minimum size that it's supported */ + para->cols = 8; + para->rows = 13; + + /* + * Previous versions of this driver tried to auto detect the rank + * and width by looking at controller registers. However this proved + * to be not reliable, so this approach here is the more robust + * solution. Check the git history for details. + * + * Strategy here is to test most demanding combination first and least + * demanding last, otherwise HW might not be fully utilized. For + * example, half bus width and rank = 1 combination would also work + * on HW with full bus width and rank = 2, but only 1/4 RAM would be + * visible. + */ + + debug("testing 32-bit width, rank = 2\n"); + para->bus_full_width = 1; + para->ranks = 2; + if (mctl_core_init(para)) + return; + + debug("testing 32-bit width, rank = 1\n"); + para->bus_full_width = 1; + para->ranks = 1; + if (mctl_core_init(para)) + return; + + debug("testing 16-bit width, rank = 2\n"); + para->bus_full_width = 0; + para->ranks = 2; + if (mctl_core_init(para)) + return; + + debug("testing 16-bit width, rank = 1\n"); + para->bus_full_width = 0; + para->ranks = 1; + if (mctl_core_init(para)) + return; + + panic("This DRAM setup is currently not supported.\n"); } static void mctl_auto_detect_dram_size(struct dram_para *para) { /* TODO: non-(LP)DDR3 */ - /* Detect rank number and half DQ by the code in mctl_channel_init. */ - mctl_core_init(para); /* detect row address bits */ para->cols = 8; @@ -652,10 +667,6 @@ unsigned long sunxi_dram_init(void) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct dram_para para = { .clk = CONFIG_DRAM_CLK, - .ranks = 2, - .cols = 11, - .rows = 14, - .bus_full_width = 1, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 .type = SUNXI_DRAM_TYPE_LPDDR3, .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, @@ -673,6 +684,7 @@ unsigned long sunxi_dram_init(void) setbits_le32(0x7010310, BIT(8)); clrbits_le32(0x7010318, 0x3f); + mctl_auto_detect_rank_width(¶); mctl_auto_detect_dram_size(¶); mctl_core_init(¶); diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 03faacbd57..9de9836c8d 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -257,14 +257,14 @@ void board_init_uart_f(void) } #if !CONFIG_IS_ENABLED(OF_CONTROL) -static struct ns16550_platdata ns16550_com1_pdata = { +static struct ns16550_plat ns16550_com1_pdata = { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }; -U_BOOT_DEVICE(ns16550_com1) = { +U_BOOT_DRVINFO(ns16550_com1) = { "ns16550_serial", &ns16550_com1_pdata }; #endif diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 48c4f32d6f..8569ad7c6f 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ -U_BOOT_DEVICE(tegra_gpios) = { +U_BOOT_DRVINFO(tegra_gpios) = { "gpio_tegra" }; #endif diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index dbd156ffce..95780f79c2 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -95,7 +95,7 @@ void support_card_init(void) /* The system bus must be initialized for access to the support card. */ ret = uclass_get_device_by_driver(UCLASS_SIMPLE_BUS, - DM_GET_DRIVER(uniphier_system_bus_driver), + DM_DRIVER_GET(uniphier_system_bus_driver), &dev); if (ret) return; diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 1ace117fc8..856047613c 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -40,7 +40,7 @@ int set_cpu_clk_info(void) int i, ret; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(zynq_clk), &dev); + DM_DRIVER_GET(zynq_clk), &dev); if (ret) return ret; @@ -75,7 +75,7 @@ int soc_clk_dump(void) int i, ret; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(zynq_clk), &dev); + DM_DRIVER_GET(zynq_clk), &dev); if (ret) return ret; diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index cc0e24cbfe..37193157d9 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -68,7 +68,7 @@ int timer_init(void) int ret; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(zynq_clk), &dev); + DM_DRIVER_GET(zynq_clk), &dev); if (ret) return ret; diff --git a/arch/m68k/include/asm/spl.h b/arch/m68k/include/asm/spl.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/arch/m68k/include/asm/spl.h diff --git a/arch/mips/mach-mtmips/mt7628/init.c b/arch/mips/mach-mtmips/mt7628/init.c index 77d1f2ea0d..33538647a2 100644 --- a/arch/mips/mach-mtmips/mt7628/init.c +++ b/arch/mips/mach-mtmips/mt7628/init.c @@ -74,7 +74,7 @@ int print_cpuinfo(void) ddr ? "" : "2", chipmode & 0x01 ? 4 : 3, chipmode & 0x02 ? "XTAL" : "CPLL"); - ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(mt7628_clk), + ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7628_clk), &clkdev); if (ret) return ret; diff --git a/arch/nds32/include/asm/spl.h b/arch/nds32/include/asm/spl.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/arch/nds32/include/asm/spl.h diff --git a/arch/nios2/include/asm/spl.h b/arch/nios2/include/asm/spl.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/arch/nios2/include/asm/spl.h diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h b/arch/riscv/include/asm/arch-fu540/gpio.h index 0d16c59ca6..b87282b974 100644 --- a/arch/riscv/include/asm/arch-fu540/gpio.h +++ b/arch/riscv/include/asm/arch-fu540/gpio.h @@ -28,7 +28,7 @@ enum gpio_state { }; /* Details about a GPIO bank */ -struct sifive_gpio_platdata { +struct sifive_gpio_plat { void *base; /* address of registers in physical memory */ }; diff --git a/arch/riscv/include/asm/arch-generic/gpio.h b/arch/riscv/include/asm/arch-generic/gpio.h index dfcb753051..b1f403027d 100644 --- a/arch/riscv/include/asm/arch-generic/gpio.h +++ b/arch/riscv/include/asm/arch-generic/gpio.h @@ -28,7 +28,7 @@ enum gpio_state { }; /* Details about a GPIO bank */ -struct sifive_gpio_platdata { +struct sifive_gpio_plat { void *base; /* address of registers in physical memory */ }; diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index c8079dc510..cfa288a01a 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -25,7 +25,7 @@ int riscv_init_ipi(void) struct udevice *dev; ret = uclass_get_device_by_driver(UCLASS_TIMER, - DM_GET_DRIVER(sifive_clint), &dev); + DM_DRIVER_GET(sifive_clint), &dev); if (ret) return ret; diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 65f988e736..f83282d9d5 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -51,6 +51,15 @@ config HOST_64BIT endchoice +config SANDBOX_CRASH_RESET + bool "Reset on crash" + help + If an illegal instruction or an illegal memory access occurs, the + sandbox by default writes a crash dump and exits. If you set this + flag, the sandbox is reset instead. This may be useful when running + test suites like the UEFI self certification test which continue + with the next test after a crash. + config SANDBOX_BITS_PER_LONG int default 32 if HOST_32BIT diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index bac96447d5..de7fe7f391 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -5,7 +5,7 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y := cpu.o state.o +obj-y := cache.o cpu.o state.o extra-y := start.o os.o extra-$(CONFIG_SANDBOX_SDL) += sdl.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/sandbox/cpu/cache.c b/arch/sandbox/cpu/cache.c new file mode 100644 index 0000000000..46c62c0b44 --- /dev/null +++ b/arch/sandbox/cpu/cache.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de> + */ + +#include <common.h> +#include <cpu_func.h> +#include <asm/state.h> + +void flush_cache(unsigned long addr, unsigned long size) +{ + /* Clang uses (char *) parameters, GCC (void *) */ + __builtin___clear_cache((void *)addr, (void *)(addr + size)); +} + +void invalidate_icache_all(void) +{ + struct sandbox_state *state = state_get_current(); + + /* Clang uses (char *) parameters, GCC (void *) */ + __builtin___clear_cache((void *)state->ram_buf, + (void *)(state->ram_buf + state->ram_size)); +} diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 0d8efd83f6..80996a91ce 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -3,6 +3,8 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#define _GNU_SOURCE + #include <dirent.h> #include <errno.h> #include <fcntl.h> @@ -15,11 +17,13 @@ #include <string.h> #include <termios.h> #include <time.h> +#include <ucontext.h> #include <unistd.h> #include <sys/mman.h> #include <sys/stat.h> #include <sys/time.h> #include <sys/types.h> +#include <linux/compiler_attributes.h> #include <linux/types.h> #include <asm/getopt.h> @@ -191,6 +195,42 @@ static void os_sigint_handler(int sig) raise(SIGINT); } +static void os_signal_handler(int sig, siginfo_t *info, void *con) +{ + ucontext_t __maybe_unused *context = con; + unsigned long pc; + +#if defined(__x86_64__) + pc = context->uc_mcontext.gregs[REG_RIP]; +#elif defined(__aarch64__) + pc = context->uc_mcontext.pc; +#elif defined(__riscv) + pc = context->uc_mcontext.__gregs[REG_PC]; +#else + const char msg[] = + "\nUnsupported architecture, cannot read program counter\n"; + + os_write(1, msg, sizeof(msg)); + pc = 0; +#endif + + os_signal_action(sig, pc); +} + +int os_setup_signal_handlers(void) +{ + struct sigaction act; + + act.sa_sigaction = os_signal_handler; + sigemptyset(&act.sa_mask); + act.sa_flags = SA_SIGINFO | SA_NODEFER; + if (sigaction(SIGILL, &act, NULL) || + sigaction(SIGBUS, &act, NULL) || + sigaction(SIGSEGV, &act, NULL)) + return -1; + return 0; +} + /* Put tty into raw mode so <tab> and <ctrl+c> work */ void os_tty_raw(int fd, bool allow_sigs) { @@ -750,6 +790,11 @@ int os_find_u_boot(char *fname, int maxlen) int os_spl_to_uboot(const char *fname) { + struct sandbox_state *state = state_get_current(); + + printf("%s\n", __func__); + /* U-Boot will delete ram buffer after read: "--rm_memory"*/ + state->ram_buf_rm = true; return os_jump_to_file(fname); } diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index a03e5aa0b3..8322ed7a1f 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -6,6 +6,7 @@ #include <common.h> #include <command.h> #include <dm/root.h> +#include <efi_loader.h> #include <errno.h> #include <init.h> #include <os.h> @@ -406,6 +407,15 @@ void state_show(struct sandbox_state *state) printf("\n"); } +void __efi_runtime EFIAPI efi_reset_system( + enum efi_reset_type reset_type, + efi_status_t reset_status, + unsigned long data_size, void *reset_data) +{ + os_fd_restore(); + os_relaunch(os_argv); +} + void sandbox_reset(void) { /* Do this here while it still has an effect */ @@ -447,10 +457,21 @@ int main(int argc, char *argv[]) if (os_parse_args(state, argc, argv)) return 1; + /* Remove old memory file if required */ + if (state->ram_buf_rm && state->ram_buf_fname) { + os_unlink(state->ram_buf_fname); + state->write_ram_buf = false; + state->ram_buf_fname = NULL; + } + ret = sandbox_read_state(state, state->state_fname); if (ret) goto err; + ret = os_setup_signal_handlers(); + if (ret) + goto err; + #if CONFIG_VAL(SYS_MALLOC_F_LEN) gd->malloc_base = CONFIG_MALLOC_F_ADDR; #endif diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 59f37fab0b..b2901b7a8c 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -415,10 +415,6 @@ int state_uninit(void) } } - /* Remove old memory file if required */ - if (state->ram_buf_rm && state->ram_buf_fname) - os_unlink(state->ram_buf_fname); - /* Delete this at the last moment so as not to upset gdb too much */ if (state->jumped_fname) os_unlink(state->jumped_fname); diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 8b50a40289..a8938a3acc 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -41,7 +41,7 @@ cros_ec: cros-ec { reg = <0 0>; - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; compatible = "google,cros-ec-sandbox"; }; @@ -83,7 +83,7 @@ }; spi: spi@0 { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; #address-cells = <1>; #size-cells = <0>; reg = <0 0>; diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index 81cdc55b0d..d842f02176 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -56,7 +56,7 @@ }; gpio_a: gpios@0 { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; gpio-controller; compatible = "sandbox,gpio"; #gpio-cells = <1>; @@ -65,7 +65,7 @@ }; gpio_b: gpios@1 { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; gpio-controller; compatible = "sandbox,gpio"; #gpio-cells = <2>; @@ -120,7 +120,7 @@ }; lcd { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; compatible = "sandbox,lcd-sdl"; xres = <1366>; yres = <768>; @@ -209,7 +209,7 @@ spi@0 { firmware_storage_spi: flash@0 { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; reg = <0>; compatible = "spansion,m25p16", "jedec,spi-nor"; spi-max-frequency = <40000000>; @@ -248,11 +248,6 @@ stringarray = "one"; }; - spl-test4 { - u-boot,dm-pre-reloc; - compatible = "sandbox,spl-test.2"; - }; - spl-test5 { u-boot,dm-tpl; compatible = "sandbox,spl-test"; @@ -283,7 +278,6 @@ }; tpm { - u-boot,dm-pre-reloc; compatible = "google,sandbox-tpm"; }; @@ -420,6 +414,6 @@ }; keyboard-controller { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; }; }; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index f3b766271d..c9b9b7b75e 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -33,10 +33,11 @@ testfdt6 = "/e-test"; testbus3 = "/some-bus"; testfdt0 = "/some-bus/c-test@0"; - testfdt1 = "/some-bus/c-test@1"; + testfdt12 = "/some-bus/c-test@1"; testfdt3 = "/b-test"; testfdt5 = "/some-bus/c-test@5"; testfdt8 = "/a-test"; + testfdtm1 = &testfdtm1; fdt-dummy0 = "/translation-test@8000/dev@0,0"; fdt-dummy1 = "/translation-test@8000/dev@1,100"; fdt-dummy2 = "/translation-test@8000/dev@2,200"; @@ -864,13 +865,21 @@ #size-cells = <0>; reg = <0 1>; compatible = "sandbox,spi"; - cs-gpios = <0>, <&gpio_a 0>; + cs-gpios = <0>, <0>, <&gpio_a 0>; spi.bin@0 { reg = <0>; compatible = "spansion,m25p16", "jedec,spi-nor"; spi-max-frequency = <40000000>; sandbox,filename = "spi.bin"; }; + spi.bin@1 { + reg = <1>; + compatible = "spansion,m25p16", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + sandbox,filename = "spi.bin"; + spi-cpol; + spi-cpha; + }; }; syscon0: syscon@0 { @@ -917,6 +926,18 @@ idle-state = <0xabcd>; }; + testfdtm0 { + compatible = "denx,u-boot-fdtm-test"; + }; + + testfdtm1: testfdtm1 { + compatible = "denx,u-boot-fdtm-test"; + }; + + testfdtm2 { + compatible = "denx,u-boot-fdtm-test"; + }; + timer@0 { compatible = "sandbox,timer"; clock-frequency = <1000000>; diff --git a/arch/sandbox/include/asm/i2c.h b/arch/sandbox/include/asm/i2c.h new file mode 100644 index 0000000000..b482be485c --- /dev/null +++ b/arch/sandbox/include/asm/i2c.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __asn_i2c_h +#define __asn_i2c_h + +struct sandbox_i2c_priv { + bool test_mode; +}; + +#endif /* __asn_i2c_h */ diff --git a/arch/sandbox/include/asm/serial.h b/arch/sandbox/include/asm/serial.h new file mode 100644 index 0000000000..bc82aebd0e --- /dev/null +++ b/arch/sandbox/include/asm/serial.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __asm_serial_h +#define __asm_serial_h + +#include <dt-structs.h> + +struct sandbox_serial_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_sandbox_serial dtplat; +#endif + int colour; /* Text colour to use for output, -1 for none */ +}; + +/** + * struct sandbox_serial_priv - Private data for this driver + * + * @buf: holds input characters available to be read by this driver + */ +struct sandbox_serial_priv { + struct membuff buf; + char serial_buf[16]; + bool start_of_line; +}; + +#endif /* __asm_serial_h */ diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h index 98e1826e2c..e8268bbe07 100644 --- a/arch/sandbox/include/asm/spi.h +++ b/arch/sandbox/include/asm/spi.h @@ -32,14 +32,4 @@ struct sandbox_spi_emu_ops { int (*xfer)(void *priv, const u8 *rx, u8 *tx, uint bytes); }; -/* - * Extract the bus/cs from the spi spec and return the start of the spi - * client spec. If the bus/cs are invalid for the current config, then - * it returns NULL. - * - * Example: arg="0:1:foo" will set bus to 0, cs to 1, and return "foo" - */ -const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus, - unsigned long *cs); - #endif diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 7f99d07c47..05f66f700c 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -203,6 +203,22 @@ void sandbox_set_allow_beep(struct udevice *dev, bool allow); int sandbox_get_beep_frequency(struct udevice *dev); /** + * sandbox_spi_get_speed() - Get current speed setting of a sandbox spi bus + * + * @dev: Device to check + * @return current bus speed + */ +uint sandbox_spi_get_speed(struct udevice *dev); + +/** + * sandbox_spi_get_mode() - Get current mode setting of a sandbox spi bus + * + * @dev: Device to check + * @return current mode + */ +uint sandbox_spi_get_mode(struct udevice *dev); + +/** * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status * * @dev: Device to check diff --git a/arch/sandbox/lib/interrupts.c b/arch/sandbox/lib/interrupts.c index 21f761ac3b..9c2c60b8c6 100644 --- a/arch/sandbox/lib/interrupts.c +++ b/arch/sandbox/lib/interrupts.c @@ -6,7 +6,13 @@ */ #include <common.h> +#include <efi_loader.h> #include <irq_func.h> +#include <os.h> +#include <asm-generic/signal.h> +#include <asm/u-boot-sandbox.h> + +DECLARE_GLOBAL_DATA_PTR; int interrupt_init(void) { @@ -21,3 +27,32 @@ int disable_interrupts(void) { return 0; } + +void os_signal_action(int sig, unsigned long pc) +{ + efi_restore_gd(); + + switch (sig) { + case SIGILL: + printf("\nIllegal instruction\n"); + break; + case SIGBUS: + printf("\nBus error\n"); + break; + case SIGSEGV: + printf("\nSegmentation violation\n"); + break; + default: + break; + } + printf("pc = 0x%lx, ", pc); + printf("pc_reloc = 0x%lx\n\n", pc - gd->reloc_off); + efi_print_image_infos((void *)pc); + + if (IS_ENABLED(CONFIG_SANDBOX_CRASH_RESET)) { + printf("resetting ...\n\n"); + sandbox_reset(); + } else { + sandbox_exit(); + } +} diff --git a/arch/sh/include/asm/spl.h b/arch/sh/include/asm/spl.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/arch/sh/include/asm/spl.h diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c index 70badb15a3..83128c33c2 100644 --- a/arch/x86/cpu/acpi_gpe.c +++ b/arch/x86/cpu/acpi_gpe.c @@ -51,7 +51,7 @@ static int acpi_gpe_read_and_clear(struct irq *irq) return ret; } -static int acpi_gpe_ofdata_to_platdata(struct udevice *dev) +static int acpi_gpe_of_to_plat(struct udevice *dev) { struct acpi_gpe_priv *priv = dev_get_priv(dev); @@ -107,6 +107,6 @@ U_BOOT_DRIVER(acpi_gpe_drv) = { .id = UCLASS_IRQ, .of_match = acpi_gpe_ids, .ops = &acpi_gpe_ops, - .ofdata_to_platdata = acpi_gpe_ofdata_to_platdata, - .priv_auto_alloc_size = sizeof(struct acpi_gpe_priv), + .of_to_plat = acpi_gpe_of_to_plat, + .priv_auto = sizeof(struct acpi_gpe_priv), }; diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index c6c1350f4f..f5dbd6cbd3 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -19,6 +19,7 @@ config INTEL_APOLLOLAKE select SMP_AP_WORK select INTEL_GMA_SWSMISCI select ACPI_GNVS_EXTERNAL + select TPL_OF_PLATDATA_PARENT imply ENABLE_MRC_CACHE imply AHCI_PCI imply SCSI diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index d37f91d1ce..328f79255f 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -63,7 +63,7 @@ static int apl_get_info(const struct udevice *dev, struct cpu_info *info) static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) { - uint core_id = dev->req_seq; + uint core_id = dev_seq(dev); int cores_per_package; int ret; diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index cef937573b..c6be707e4e 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -32,7 +32,10 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) node = dev_ofnode(dev); if (!ofnode_valid(node)) - return log_msg_ret("fsp-m settings", -ENOENT); + return log_msg_ret("node", -ENOENT); + node = ofnode_find_subnode(node, "fsp-m"); + if (!ofnode_valid(node)) + return log_msg_ret("fspm", -ENOENT); ret = fsp_m_update_config_from_dtb(node, cfg); if (ret) diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index cafd9d65b2..9decab7aa3 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -24,6 +24,7 @@ #include <asm/io.h> #include <asm/pci.h> #include <asm/arch/acpi.h> +#include <asm/arch/hostbridge.h> #include <asm/arch/systemagent.h> #include <dt-bindings/sound/nhlt.h> #include <dm/acpi.h> @@ -41,25 +42,7 @@ enum { TOLUD = 0xbc, }; -/** - * struct apl_hostbridge_platdata - platform data for hostbridge - * - * @dtplat: Platform data for of-platdata - * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1) - * @early_pads_count: Number of pads to process - * @pciex_region_size: BAR length in bytes - * @bdf: Bus/device/function of hostbridge - */ -struct apl_hostbridge_platdata { -#if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_intel_apl_hostbridge dtplat; -#endif - u32 *early_pads; - int early_pads_count; - uint pciex_region_size; - pci_dev_t bdf; -}; - +#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) static const struct nhlt_format_config dmic_1ch_formats[] = { /* 48 KHz 16-bits per sample. */ { @@ -155,10 +138,11 @@ static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { .num_formats = ARRAY_SIZE(dmic_4ch_formats), }, }; +#endif static int apl_hostbridge_early_init_pinctrl(struct udevice *dev) { - struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct apl_hostbridge_plat *plat = dev_get_plat(dev); struct udevice *pinctrl; int ret; @@ -172,7 +156,7 @@ static int apl_hostbridge_early_init_pinctrl(struct udevice *dev) static int apl_hostbridge_early_init(struct udevice *dev) { - struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct apl_hostbridge_plat *plat = dev_get_plat(dev); u32 region_size; ulong base; u32 reg; @@ -221,9 +205,9 @@ static int apl_hostbridge_early_init(struct udevice *dev) return 0; } -static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev) +static int apl_hostbridge_of_to_plat(struct udevice *dev) { - struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct apl_hostbridge_plat *plat = dev_get_plat(dev); struct udevice *pinctrl; int ret; @@ -283,7 +267,7 @@ static int apl_acpi_hb_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "RHUB"); } -#ifdef CONFIG_GENERATE_ACPI_TABLE +#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) static int apl_acpi_hb_write_tables(const struct udevice *dev, struct acpi_ctx *ctx) { @@ -322,7 +306,6 @@ static int apl_acpi_hb_write_tables(const struct udevice *dev, return 0; } -#endif static int apl_acpi_setup_nhlt(const struct udevice *dev, struct acpi_ctx *ctx) { @@ -347,6 +330,7 @@ static int apl_acpi_setup_nhlt(const struct udevice *dev, struct acpi_ctx *ctx) return log_msg_ret("channels", -EINVAL); } +#endif static int apl_hostbridge_remove(struct udevice *dev) { @@ -385,25 +369,27 @@ ulong sa_get_tseg_base(struct udevice *dev) struct acpi_ops apl_hostbridge_acpi_ops = { .get_name = apl_acpi_hb_get_name, -#ifdef CONFIG_GENERATE_ACPI_TABLE +#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) .write_tables = apl_acpi_hb_write_tables, -#endif .setup_nhlt = apl_acpi_setup_nhlt, +#endif }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct udevice_id apl_hostbridge_ids[] = { { .compatible = "intel,apl-hostbridge" }, { } }; +#endif U_BOOT_DRIVER(intel_apl_hostbridge) = { .name = "intel_apl_hostbridge", .id = UCLASS_NORTHBRIDGE, - .of_match = apl_hostbridge_ids, - .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata, + .of_match = of_match_ptr(apl_hostbridge_ids), + .of_to_plat = apl_hostbridge_of_to_plat, .probe = apl_hostbridge_probe, .remove = apl_hostbridge_remove, - .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata), + .plat_auto = sizeof(struct apl_hostbridge_plat), ACPI_OPS_PTR(&apl_hostbridge_acpi_ops) .flags = DM_FLAG_OS_PREPARE, }; diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index d8e05f6a8f..e085890d63 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -81,10 +81,11 @@ int lpc_open_pmio_window(uint base, uint size) lgir_reg_num = find_unused_pmio_window(); if (lgir_reg_num < 0) { - log_err("LPC: Cannot open IO window: %lx size %lx\n", - bridge_base, size - bridged_size); - log_err("No more IO windows\n"); - + if (spl_phase() > PHASE_TPL) { + log_err("LPC: Cannot open IO window: %lx size %lx\n", + bridge_base, size - bridged_size); + log_err("No more IO windows\n"); + } return -ENOSPC; } lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); @@ -127,15 +128,17 @@ struct acpi_ops apl_lpc_acpi_ops = { .inject_dsdt = southbridge_inject_dsdt, }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct udevice_id apl_lpc_ids[] = { { .compatible = "intel,apl-lpc" }, { } }; +#endif /* All pads are LPC already configured by the hostbridge, so no probing here */ U_BOOT_DRIVER(intel_apl_lpc) = { .name = "intel_apl_lpc", .id = UCLASS_LPC, - .of_match = apl_lpc_ids, + .of_match = of_match_ptr(apl_lpc_ids), ACPI_OPS_PTR(&apl_lpc_acpi_ops) }; diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c index d9832ff249..39d6ad5ed4 100644 --- a/arch/x86/cpu/apollolake/pch.c +++ b/arch/x86/cpu/apollolake/pch.c @@ -23,14 +23,16 @@ static const struct pch_ops apl_pch_ops = { .set_spi_protect = apl_set_spi_protect, }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct udevice_id apl_pch_ids[] = { { .compatible = "intel,apl-pch" }, { } }; +#endif U_BOOT_DRIVER(intel_apl_pch) = { .name = "intel_apl_pch", .id = UCLASS_PCH, - .of_match = apl_pch_ids, + .of_match = of_match_ptr(apl_pch_ids), .ops = &apl_pch_ops, }; diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index cacaa007e0..e23d38ea07 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -16,6 +16,7 @@ #include <acpi/acpi_s3.h> #include <asm/io.h> #include <asm/pci.h> +#include <asm/arch/pmc.h> #include <linux/bitops.h> #include <power/acpi_pmc.h> @@ -53,13 +54,6 @@ enum { CF9_GLB_RST = 1 << 20, }; -struct apl_pmc_platdata { -#if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_intel_apl_pmc dtplat; -#endif - pci_dev_t bdf; -}; - static int apl_pmc_fill_power_state(struct udevice *dev) { struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); @@ -108,10 +102,10 @@ static int apl_global_reset_set_enable(struct udevice *dev, bool enable) return 0; } -int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev) +int apl_pmc_ofdata_to_uc_plat(struct udevice *dev) { struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); - struct apl_pmc_platdata *plat = dev_get_platdata(dev); + struct apl_pmc_plat *plat = dev_get_plat(dev); #if !CONFIG_IS_ENABLED(OF_PLATDATA) u32 base[6]; @@ -144,7 +138,7 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev) if (ret) return log_msg_ret("Bad gpe0-dw", ret); - return pmc_ofdata_to_uc_platdata(dev); + return pmc_ofdata_to_uc_plat(dev); #else struct dtd_intel_apl_pmc *dtplat = &plat->dtplat; @@ -169,7 +163,7 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev) static int enable_pmcbar(struct udevice *dev) { struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); - struct apl_pmc_platdata *priv = dev_get_platdata(dev); + struct apl_pmc_plat *priv = dev_get_plat(dev); pci_dev_t pmc = priv->bdf; /* @@ -205,24 +199,26 @@ static int apl_pmc_probe(struct udevice *dev) return 0; } -static struct acpi_pmc_ops apl_pmc_ops = { +static const struct acpi_pmc_ops apl_pmc_ops = { .init = apl_pmc_fill_power_state, .prev_sleep_state = apl_prev_sleep_state, .disable_tco = apl_disable_tco, .global_reset_set_enable = apl_global_reset_set_enable, }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct udevice_id apl_pmc_ids[] = { { .compatible = "intel,apl-pmc" }, { } }; +#endif U_BOOT_DRIVER(intel_apl_pmc) = { .name = "intel_apl_pmc", .id = UCLASS_ACPI_PMC, - .of_match = apl_pmc_ids, - .ofdata_to_platdata = apl_pmc_ofdata_to_uc_platdata, + .of_match = of_match_ptr(apl_pmc_ids), + .of_to_plat = apl_pmc_ofdata_to_uc_plat, .probe = apl_pmc_probe, .ops = &apl_pmc_ops, - .platdata_auto_alloc_size = sizeof(struct apl_pmc_platdata), + .plat_auto = sizeof(struct apl_pmc_plat), }; diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c index 089b37c59f..8991d5e648 100644 --- a/arch/x86/cpu/apollolake/spl.c +++ b/arch/x86/cpu/apollolake/spl.c @@ -83,33 +83,6 @@ static int apl_flash_probe(struct udevice *dev) return spi_flash_std_probe(dev); } -/* - * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also - * need to allocate the parent_platdata since by the time this function is - * called device_bind() has already gone past that step. - */ -static int apl_flash_bind(struct udevice *dev) -{ - if (CONFIG_IS_ENABLED(OF_PLATDATA) && - !CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) { - struct dm_spi_slave_platdata *plat; - struct udevice *spi; - int ret; - - ret = uclass_first_device_err(UCLASS_SPI, &spi); - if (ret) - return ret; - dev->parent = spi; - - plat = calloc(sizeof(*plat), 1); - if (!plat) - return -ENOMEM; - dev->parent_platdata = plat; - } - - return 0; -} - static const struct dm_spi_flash_ops apl_flash_ops = { .read = apl_flash_std_read, }; @@ -123,9 +96,8 @@ U_BOOT_DRIVER(winbond_w25q128fw) = { .name = "winbond_w25q128fw", .id = UCLASS_SPI_FLASH, .of_match = apl_flash_ids, - .bind = apl_flash_bind, .probe = apl_flash_probe, - .priv_auto_alloc_size = sizeof(struct spi_flash), + .priv_auto = sizeof(struct spi_nor), .ops = &apl_flash_ops, }; diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c index c522aa9780..876fa592b8 100644 --- a/arch/x86/cpu/apollolake/uart.c +++ b/arch/x86/cpu/apollolake/uart.c @@ -16,6 +16,8 @@ #include <asm/io.h> #include <asm/pci.h> #include <asm/lpss.h> +#include <dm/device-internal.h> +#include <asm/arch/uart.h> /* Low-power Subsystem (LPSS) clock register */ enum { @@ -68,48 +70,52 @@ void apl_uart_init(pci_dev_t bdf, ulong base) * This driver uses its own compatible string but almost everything else from * the standard ns16550 driver. This allows us to provide an of-platdata * implementation, since the platdata produced by of-platdata does not match - * struct ns16550_platdata. + * struct apl_ns16550_plat. * * When running with of-platdata (generally TPL), the platdata is converted to * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot - * proper), we use ns16550's ofdata_to_platdata routine. + * proper), we use ns16550's of_to_plat routine. */ static int apl_ns16550_probe(struct udevice *dev) { - struct ns16550_platdata *plat = dev_get_platdata(dev); + struct apl_ns16550_plat *plat = dev_get_plat(dev); if (!CONFIG_IS_ENABLED(PCI)) - apl_uart_init(plat->bdf, plat->base); + apl_uart_init(plat->ns16550.bdf, plat->ns16550.base); return ns16550_serial_probe(dev); } -static int apl_ns16550_ofdata_to_platdata(struct udevice *dev) +static int apl_ns16550_of_to_plat(struct udevice *dev) { #if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_intel_apl_ns16550 *dtplat = dev_get_platdata(dev); - struct ns16550_platdata *plat; + struct dtd_intel_apl_ns16550 *dtplat; + struct apl_ns16550_plat *plat = dev_get_plat(dev); + struct ns16550_plat ns; /* - * Convert our platdata to the ns16550's platdata, so we can just use - * that driver + * The device's plat uses struct apl_ns16550_plat which starts with the + * dtd struct, but the ns16550 driver expects it to be struct ns16550. + * Set up what that driver expects. Note that this means that the values + * cannot be read in this driver when using of-platdata. + * + * TODO(sjg@chromium.org): Consider having a separate plat pointer for + * of-platdata so that it is not necessary to overwrite this. */ - plat = malloc(sizeof(*plat)); - if (!plat) - return -ENOMEM; - plat->base = dtplat->early_regs[0]; - plat->reg_width = 1; - plat->reg_shift = dtplat->reg_shift; - plat->reg_offset = 0; - plat->clock = dtplat->clock_frequency; - plat->fcr = UART_FCR_DEFVAL; - plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]); - dev->platdata = plat; + dtplat = &plat->dtplat; + ns.base = dtplat->early_regs[0]; + ns.reg_width = 1; + ns.reg_shift = dtplat->reg_shift; + ns.reg_offset = 0; + ns.clock = dtplat->clock_frequency; + ns.fcr = UART_FCR_DEFVAL; + ns.bdf = pci_ofplat_get_devfn(dtplat->reg[0]); + memcpy(plat, &ns, sizeof(ns)); #else int ret; - ret = ns16550_serial_ofdata_to_platdata(dev); + ret = ns16550_serial_of_to_plat(dev); if (ret) return ret; #endif /* OF_PLATDATA */ @@ -117,18 +123,20 @@ static int apl_ns16550_ofdata_to_platdata(struct udevice *dev) return 0; } +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct udevice_id apl_ns16550_serial_ids[] = { { .compatible = "intel,apl-ns16550" }, { }, }; +#endif U_BOOT_DRIVER(intel_apl_ns16550) = { .name = "intel_apl_ns16550", .id = UCLASS_SERIAL, - .of_match = apl_ns16550_serial_ids, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), + .of_match = of_match_ptr(apl_ns16550_serial_ids), + .plat_auto = sizeof(struct apl_ns16550_plat), + .priv_auto = sizeof(struct ns16550), .ops = &ns16550_serial_ops, - .ofdata_to_platdata = apl_ns16550_ofdata_to_platdata, + .of_to_plat = apl_ns16550_of_to_plat, .probe = apl_ns16550_probe, }; diff --git a/arch/x86/cpu/broadwell/adsp.c b/arch/x86/cpu/broadwell/adsp.c index 41f7d5d4d1..1fa1823780 100644 --- a/arch/x86/cpu/broadwell/adsp.c +++ b/arch/x86/cpu/broadwell/adsp.c @@ -122,7 +122,7 @@ static int broadwell_adsp_probe(struct udevice *dev) return 0; } -static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev) +static int broadwell_adsp_of_to_plat(struct udevice *dev) { struct broadwell_adsp_priv *priv = dev_get_priv(dev); @@ -142,7 +142,7 @@ static const struct udevice_id broadwell_adsp_ids[] = { U_BOOT_DRIVER(broadwell_adsp_drv) = { .name = "adsp", .id = UCLASS_SYSCON, - .ofdata_to_platdata = broadwell_adsp_ofdata_to_platdata, + .of_to_plat = broadwell_adsp_of_to_plat, .of_match = broadwell_adsp_ids, .bind = dm_scan_fdt_dev, .probe = broadwell_adsp_probe, diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index 706f68f63d..ea9e98dde6 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -638,7 +638,7 @@ static int broadwell_get_count(const struct udevice *dev) static int cpu_x86_broadwell_probe(struct udevice *dev) { - if (dev->seq == 0) { + if (dev_seq(dev) == 0) { cpu_core_init(dev); return broadwell_init(dev); } @@ -665,6 +665,6 @@ U_BOOT_DRIVER(cpu_x86_broadwell_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_broadwell_probe, .ops = &cpu_x86_broadwell_ops, - .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv), + .priv_auto = sizeof(struct cpu_broadwell_priv), .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c index 641da515c8..ceb395ddcf 100644 --- a/arch/x86/cpu/broadwell/sata.c +++ b/arch/x86/cpu/broadwell/sata.c @@ -17,7 +17,7 @@ #include <asm/arch/pch.h> #include <linux/delay.h> -struct sata_platdata { +struct sata_plat { int port_map; uint port0_gen3_tx; uint port1_gen3_tx; @@ -41,7 +41,7 @@ struct sata_platdata { static void broadwell_sata_init(struct udevice *dev) { - struct sata_platdata *plat = dev_get_platdata(dev); + struct sata_plat *plat = dev_get_plat(dev); u32 reg32; u8 *abar; u16 reg16; @@ -211,7 +211,7 @@ static void broadwell_sata_init(struct udevice *dev) static int broadwell_sata_enable(struct udevice *dev) { - struct sata_platdata *plat = dev_get_platdata(dev); + struct sata_plat *plat = dev_get_plat(dev); struct gpio_desc desc; u16 map; int ret; @@ -232,9 +232,9 @@ static int broadwell_sata_enable(struct udevice *dev) return 0; } -static int broadwell_sata_ofdata_to_platdata(struct udevice *dev) +static int broadwell_sata_of_to_plat(struct udevice *dev) { - struct sata_platdata *plat = dev_get_platdata(dev); + struct sata_plat *plat = dev_get_plat(dev); const void *blob = gd->fdt_blob; int node = dev_of_offset(dev); @@ -264,7 +264,7 @@ U_BOOT_DRIVER(ahci_broadwell_drv) = { .name = "ahci_broadwell", .id = UCLASS_AHCI, .of_match = broadwell_ahci_ids, - .ofdata_to_platdata = broadwell_sata_ofdata_to_platdata, + .of_to_plat = broadwell_sata_of_to_plat, .probe = broadwell_sata_probe, - .platdata_auto_alloc_size = sizeof(struct sata_platdata), + .plat_auto = sizeof(struct sata_plat), }; diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 7e83051646..bfb511a510 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; int cpu_x86_bind(struct udevice *dev) { - struct cpu_platdata *plat = dev_get_parent_platdata(dev); + struct cpu_plat *plat = dev_get_parent_plat(dev); struct cpuid_result res; plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), diff --git a/arch/x86/cpu/i386/call64.S b/arch/x86/cpu/i386/call64.S index 275063c4af..0ffc1006bb 100644 --- a/arch/x86/cpu/i386/call64.S +++ b/arch/x86/cpu/i386/call64.S @@ -11,6 +11,7 @@ #include <asm/processor-flags.h> .code32 +.section .text_call64 .globl cpu_call64 cpu_call64: /* diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 4a5cf17e41..8b9a810f66 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -26,7 +26,7 @@ obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o obj-y += lpss.o -obj-$(CONFIG_INTEL_GENERIC_WIFI) += generic_wifi.o +obj-$(CONFIG_$(SPL_)INTEL_GENERIC_WIFI) += generic_wifi.o ifndef CONFIG_TARGET_EFI_APP obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o ifndef CONFIG_$(SPL_)X86_64 diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index de17b93ed4..ae4de4ca8c 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -19,25 +19,6 @@ #include <spl.h> #include <asm/itss.h> -struct itss_platdata { -#if CONFIG_IS_ENABLED(OF_PLATDATA) - /* Put this first since driver model will copy the data here */ - struct dtd_intel_itss dtplat; -#endif -}; - -/* struct pmc_route - Routing for PMC to GPIO */ -struct pmc_route { - u32 pmc; - u32 gpio; -}; - -struct itss_priv { - struct pmc_route *route; - uint route_count; - u32 irq_snapshot[NUM_IPC_REGS]; -}; - static int set_polarity(struct udevice *dev, uint irq, bool active_low) { u32 mask; @@ -178,13 +159,13 @@ static int itss_bind(struct udevice *dev) return 0; } -static int itss_ofdata_to_platdata(struct udevice *dev) +static int itss_of_to_plat(struct udevice *dev) { struct itss_priv *priv = dev_get_priv(dev); int ret; #if CONFIG_IS_ENABLED(OF_PLATDATA) - struct itss_platdata *plat = dev_get_platdata(dev); + struct itss_plat *plat = dev_get_plat(dev); struct dtd_intel_itss *dtplat = &plat->dtplat; /* @@ -230,18 +211,20 @@ static const struct irq_ops itss_ops = { #endif }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct udevice_id itss_ids[] = { { .compatible = "intel,itss", .data = X86_IRQT_ITSS }, { } }; +#endif U_BOOT_DRIVER(intel_itss) = { .name = "intel_itss", .id = UCLASS_IRQ, - .of_match = itss_ids, + .of_match = of_match_ptr(itss_ids), .ops = &itss_ops, .bind = itss_bind, - .ofdata_to_platdata = itss_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct itss_platdata), - .priv_auto_alloc_size = sizeof(struct itss_priv), + .of_to_plat = itss_of_to_plat, + .plat_auto = sizeof(struct itss_plat), + .priv_auto = sizeof(struct itss_priv), }; diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index a0a4001e03..d73ae438bb 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -13,20 +13,13 @@ #include <log.h> #include <p2sb.h> #include <spl.h> +#include <asm/p2sb.h> #include <asm/pci.h> #include <linux/bitops.h> #define PCH_P2SB_E0 0xe0 #define HIDE_BIT BIT(0) -struct p2sb_platdata { -#if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_intel_p2sb dtplat; -#endif - ulong mmio_base; - pci_dev_t bdf; -}; - /* PCI config space registers */ #define HPTC_OFFSET 0x60 #define HPTC_ADDR_ENABLE_BIT BIT(7) @@ -57,7 +50,7 @@ struct p2sb_platdata { */ static int p2sb_early_init(struct udevice *dev) { - struct p2sb_platdata *plat = dev_get_platdata(dev); + struct p2sb_plat *plat = dev_get_plat(dev); pci_dev_t pdev = plat->bdf; /* @@ -90,10 +83,10 @@ static int p2sb_spl_init(struct udevice *dev) return 0; } -int p2sb_ofdata_to_platdata(struct udevice *dev) +int p2sb_of_to_plat(struct udevice *dev) { struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev); - struct p2sb_platdata *plat = dev_get_platdata(dev); + struct p2sb_plat *plat = dev_get_plat(dev); #if !CONFIG_IS_ENABLED(OF_PLATDATA) int ret; @@ -167,7 +160,7 @@ static int p2sb_remove(struct udevice *dev) static int p2sb_child_post_bind(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); int ret; u32 pid; @@ -180,26 +173,27 @@ static int p2sb_child_post_bind(struct udevice *dev) return 0; } -struct p2sb_ops p2sb_ops = { +static const struct p2sb_ops p2sb_ops = { .set_hide = intel_p2sb_set_hide, }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct udevice_id p2sb_ids[] = { { .compatible = "intel,p2sb" }, { } }; +#endif U_BOOT_DRIVER(intel_p2sb) = { .name = "intel_p2sb", .id = UCLASS_P2SB, - .of_match = p2sb_ids, + .of_match = of_match_ptr(p2sb_ids), .probe = p2sb_probe, .remove = p2sb_remove, .ops = &p2sb_ops, - .ofdata_to_platdata = p2sb_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct p2sb_platdata), - .per_child_platdata_auto_alloc_size = - sizeof(struct p2sb_child_platdata), + .of_to_plat = p2sb_of_to_plat, + .plat_auto = sizeof(struct p2sb_plat), + .per_child_plat_auto = sizeof(struct p2sb_child_plat), .child_post_bind = p2sb_child_post_bind, .flags = DM_FLAG_OS_PREPARE, }; diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 836a0e8b86..8b53b96822 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -362,5 +362,5 @@ U_BOOT_DRIVER(irq_router_drv) = { .id = UCLASS_IRQ, .of_match = irq_router_ids, .probe = irq_router_probe, - .priv_auto_alloc_size = sizeof(struct irq_router), + .priv_auto = sizeof(struct irq_router), }; diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 55f7cc2b2e..598ebcdf08 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -425,7 +425,7 @@ static int model_206ax_get_count(const struct udevice *dev) static int cpu_x86_model_206ax_probe(struct udevice *dev) { - if (dev->seq == 0) + if (dev_seq(dev) == 0) model_206ax_init(dev); return 0; diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index d2f1ee38cf..0e61c7b5d7 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -87,7 +87,7 @@ DECLARE_GLOBAL_DATA_PTR; * intel,apic-id = <2>; * }; * - * Here the 'reg' property is the CPU number and then is placed in dev->req_seq + * Here the 'reg' property is the CPU number and then is placed in dev_seq(cpu) * so that we can index into ap_callbacks[] using that. The APIC ID is different * and may not be sequential (it typically is if hyperthreading is supported). * @@ -135,7 +135,7 @@ struct mp_flight_plan { * * @func: Function to run * @arg: Argument to pass to the function - * @logical_cpu_number: Either a CPU number (i.e. dev->req_seq) or a special + * @logical_cpu_number: Either a CPU number (i.e. dev_seq(cpu) or a special * value like MP_SELECT_BSP. It tells the AP whether it should process this * callback */ @@ -152,7 +152,7 @@ static struct mp_flight_plan mp_info; * ap_callbacks - Callback mailbox array * * Array of callback, one entry for each available CPU, indexed by the CPU - * number, which is dev->req_seq. The entry for the main CPU is never used. + * number, which is dev_seq(cpu). The entry for the main CPU is never used. * When this is NULL, there is no pending work for the CPU to run. When * non-NULL it points to the mp_callback structure. This is shared between all * CPUs, so should only be written by the main CPU. @@ -221,7 +221,7 @@ static int find_cpu_by_apic_id(int apic_id, struct udevice **devp) for (uclass_find_first_device(UCLASS_CPU, &dev); dev; uclass_find_next_device(&dev)) { - struct cpu_platdata *plat = dev_get_parent_platdata(dev); + struct cpu_plat *plat = dev_get_parent_plat(dev); if (plat->cpu_id == apic_id) { *devp = dev; @@ -562,7 +562,7 @@ static int get_bsp(struct udevice **devp, int *cpu_countp) if (cpu_countp) *cpu_countp = ret; - return dev->req_seq >= 0 ? dev->req_seq : 0; + return dev_seq(dev) >= 0 ? dev_seq(dev) : 0; } /** @@ -614,7 +614,7 @@ static void store_callback(struct mp_callback **slot, struct mp_callback *val) static int run_ap_work(struct mp_callback *callback, struct udevice *bsp, int num_cpus, uint expire_ms) { - int cur_cpu = bsp->req_seq; + int cur_cpu = dev_seq(bsp); int num_aps = num_cpus - 1; /* number of non-BSPs to get this message */ int cpus_accepted; ulong start; @@ -679,7 +679,7 @@ static int ap_wait_for_instruction(struct udevice *cpu, void *unused) if (!IS_ENABLED(CONFIG_SMP_AP_WORK)) return 0; - per_cpu_slot = &ap_callbacks[cpu->req_seq]; + per_cpu_slot = &ap_callbacks[dev_seq(cpu)]; while (1) { struct mp_callback *cb = read_callback(per_cpu_slot); @@ -694,7 +694,7 @@ static int ap_wait_for_instruction(struct udevice *cpu, void *unused) mfence(); if (lcb.logical_cpu_number == MP_SELECT_ALL || lcb.logical_cpu_number == MP_SELECT_APS || - cpu->req_seq == lcb.logical_cpu_number) + dev_seq(cpu) == lcb.logical_cpu_number) lcb.func(lcb.arg); /* Indicate we are finished */ @@ -706,7 +706,7 @@ static int ap_wait_for_instruction(struct udevice *cpu, void *unused) static int mp_init_cpu(struct udevice *cpu, void *unused) { - struct cpu_platdata *plat = dev_get_parent_platdata(cpu); + struct cpu_plat *plat = dev_get_parent_plat(cpu); plat->ucode_version = microcode_read_rev(); plat->device_id = gd->arch.x86_device; @@ -839,7 +839,6 @@ int mp_init(void) int num_aps, num_cpus; atomic_t *ap_count; struct udevice *cpu; - struct uclass *uc; int ret; if (IS_ENABLED(CONFIG_QFW)) { @@ -848,14 +847,6 @@ int mp_init(void) return ret; } - /* - * Multiple APs are brought up simultaneously and they may get the same - * seq num in the uclass_resolve_seq() during device_probe(). To avoid - * this, set req_seq to the reg number in the device tree in advance. - */ - uclass_id_foreach_dev(UCLASS_CPU, cpu, uc) - cpu->req_seq = dev_read_u32_default(cpu, "reg", -1); - ret = get_bsp(&cpu, &num_cpus); if (ret < 0) { debug("Cannot init boot CPU: err=%d\n", ret); diff --git a/arch/x86/cpu/qfw_cpu.c b/arch/x86/cpu/qfw_cpu.c index 349bab1583..a35de878b5 100644 --- a/arch/x86/cpu/qfw_cpu.c +++ b/arch/x86/cpu/qfw_cpu.c @@ -18,7 +18,7 @@ int qemu_cpu_fixup(void) int cpu_num; int cpu_online; struct udevice *dev, *pdev; - struct cpu_platdata *plat; + struct cpu_plat *plat; char *cpu; /* first we need to find '/cpus' */ @@ -67,7 +67,7 @@ int qemu_cpu_fixup(void) printf("binding cpu@%d failed: %d\n", cpu_num, ret); return ret; } - plat = dev_get_parent_platdata(dev); + plat = dev_get_parent_plat(dev); plat->cpu_id = cpu_num; } return 0; diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c index 9813f7977b..772a94c31c 100644 --- a/arch/x86/cpu/slimbootloader/serial.c +++ b/arch/x86/cpu/slimbootloader/serial.c @@ -14,11 +14,11 @@ * The serial port info hob is generated by Slim Bootloader, so eligible for * Slim Bootloader based boards only. */ -static int slimbootloader_serial_ofdata_to_platdata(struct udevice *dev) +static int slimbootloader_serial_of_to_plat(struct udevice *dev) { const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID; struct sbl_serial_port_info *data; - struct ns16550_platdata *plat = dev->platdata; + struct ns16550_plat *plat = dev_get_plat(dev); if (!gd->arch.hob_list) panic("hob list not found!"); @@ -57,9 +57,9 @@ U_BOOT_DRIVER(serial_slimbootloader) = { .name = "serial_slimbootloader", .id = UCLASS_SERIAL, .of_match = slimbootloader_serial_ids, - .ofdata_to_platdata = slimbootloader_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), + .of_to_plat = slimbootloader_serial_of_to_plat, + .plat_auto = sizeof(struct ns16550_plat), + .priv_auto = sizeof(struct ns16550), .probe = ns16550_serial_probe, .ops = &ns16550_serial_ops, }; diff --git a/arch/x86/cpu/tangier/pinmux.c b/arch/x86/cpu/tangier/pinmux.c index 5b0e106011..acf97e3af5 100644 --- a/arch/x86/cpu/tangier/pinmux.c +++ b/arch/x86/cpu/tangier/pinmux.c @@ -191,5 +191,5 @@ U_BOOT_DRIVER(tangier_pinctrl) = { .id = UCLASS_SYSCON, .of_match = tangier_pinctrl_match, .probe = tangier_pinctrl_probe, - .priv_auto_alloc_size = sizeof(struct mrfld_pinctrl), + .priv_auto = sizeof(struct mrfld_pinctrl), }; diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c index f8d85d5a33..4a73cb240d 100644 --- a/arch/x86/cpu/turbo.c +++ b/arch/x86/cpu/turbo.c @@ -35,12 +35,15 @@ static inline void set_global_turbo_state(int state) } #endif +/* gcc 7.3 does not wwant to drop strings, so use #ifdef */ +#ifndef CONFIG_TPL_BUILD static const char *const turbo_state_desc[] = { [TURBO_UNKNOWN] = "unknown", [TURBO_UNAVAILABLE] = "unavailable", [TURBO_DISABLED] = "available but hidden", [TURBO_ENABLED] = "available and visible" }; +#endif /* * Determine the current state of Turbo and cache it for later. @@ -76,7 +79,9 @@ int turbo_get_state(void) } set_global_turbo_state(turbo_state); +#ifndef CONFIG_TPL_BUILD debug("Turbo is %s\n", turbo_state_desc[turbo_state]); +#endif return turbo_state; } diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index d66e128ae6..a846022095 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -102,12 +102,13 @@ }; cpus { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; #address-cells = <1>; #size-cells = <0>; cpu_0: cpu@0 { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; + u-boot,dm-spl; device_type = "cpu"; compatible = "intel,apl-cpu"; reg = <0>; @@ -174,6 +175,9 @@ */ fsp_s: fsp-s { }; + fsp_m: fsp-m { + u-boot,dm-spl; + }; nhlt { intel,dmic-channels = <4>; @@ -181,12 +185,14 @@ }; punit@0,1 { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; + u-boot,dm-spl; reg = <0x00000800 0 0 0 0>; compatible = "intel,apl-punit"; }; gma@2,0 { + u-boot,dm-pre-proper; reg = <0x00001000 0 0 0 0>; compatible = "fsp-fb"; }; @@ -321,7 +327,8 @@ }; spi: fast-spi@d,2 { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; + u-boot,dm-spl; reg = <0x02006a10 0 0 0 0>; #address-cells = <1>; #size-cells = <0>; @@ -332,7 +339,8 @@ fwstore_spi: spi-flash@0 { #size-cells = <1>; #address-cells = <1>; - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; + u-boot,dm-spl; reg = <0>; compatible = "winbond,w25q128fw", "jedec,spi-nor"; @@ -574,7 +582,7 @@ #size-cells = <0>; u-boot,dm-pre-reloc; cros_ec: cros-ec { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; compatible = "google,cros-ec-lpc"; reg = <0x204 1 0x200 1 0x880 0x80>; @@ -650,7 +658,9 @@ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ >; +}; +&fsp_m { fspm,package = <PACKAGE_BGA>; fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; fspm,memory-down = <MEMORY_DOWN_YES>; diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi index d0bbd84e50..942cc937dc 100644 --- a/arch/x86/dts/rtc.dtsi +++ b/arch/x86/dts/rtc.dtsi @@ -1,7 +1,7 @@ / { rtc: rtc { compatible = "motorola,mc146818"; - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; reg = <0x70 2>; }; }; diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h index ab5860c0fd..762160da88 100644 --- a/arch/x86/include/asm/arch-apollolake/gpio.h +++ b/arch/x86/include/asm/arch-apollolake/gpio.h @@ -485,4 +485,22 @@ /* This is needed by ACPI */ #define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ +#ifndef __ASSEMBLY__ + +#include <dt-structs.h> + +/** + * struct apl_gpio_plat - platform data for each device + * + * @dtplat: of-platdata data from C struct + */ +struct apl_gpio_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* Put this first since driver model will copy the data here */ + struct dtd_intel_apl_pinctrl dtplat; +#endif +}; + +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-apollolake/hostbridge.h b/arch/x86/include/asm/arch-apollolake/hostbridge.h new file mode 100644 index 0000000000..f4dce0d522 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/hostbridge.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + */ + +#ifndef _ASM_ARCH_HOSTBRIDGE_H_ +#define _ASM_ARCH_HOSTBRIDGE_H_ + +/** + * struct apl_hostbridge_plat - platform data for hostbridge + * + * @dtplat: Platform data for of-platdata + * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1) + * @early_pads_count: Number of pads to process + * @pciex_region_size: BAR length in bytes + * @bdf: Bus/device/function of hostbridge + */ +struct apl_hostbridge_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_hostbridge dtplat; +#endif + u32 *early_pads; + int early_pads_count; + uint pciex_region_size; + pci_dev_t bdf; +}; + +#endif /* _ASM_ARCH_HOSTBRIDGE_H_ */ diff --git a/arch/x86/include/asm/arch-apollolake/pmc.h b/arch/x86/include/asm/arch-apollolake/pmc.h new file mode 100644 index 0000000000..23ac8fe7e2 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/pmc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + */ + +#ifndef ASM_ARCH_PMC_H +#define ASM_ARCH_PMC_H + +struct apl_pmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_pmc dtplat; +#endif + pci_dev_t bdf; +}; + +#endif /* ASM_ARCH_PMC_H */ diff --git a/arch/x86/include/asm/arch-apollolake/uart.h b/arch/x86/include/asm/arch-apollolake/uart.h index d4fffe6525..38335b0490 100644 --- a/arch/x86/include/asm/arch-apollolake/uart.h +++ b/arch/x86/include/asm/arch-apollolake/uart.h @@ -6,6 +6,23 @@ #ifndef _ASM_ARCH_UART_H #define _ASM_ARCH_UART_H +#include <ns16550.h> + +/** + * struct apl_ns16550_plat - platform data for the APL UART + * + * Note that when of-platdata is in use, apl_ns16550_of_to_plat() actually + * copies the ns16550_plat contents to the start of this struct, meaning that + * dtplat is no-longer valid. This is done so that the ns16550 driver can use + * dev_get_plat() without any offsets or adjustments. + */ +struct apl_ns16550_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_ns16550 dtplat; +#endif + struct ns16550_plat ns16550; +}; + /** * apl_uart_init() - Set up the APL UART device and clock * @@ -15,6 +32,6 @@ * The UART won't actually work unless the GPIO settings are correct and the * signals actually exit the SoC. See board_debug_uart_init() for that. */ -int apl_uart_init(pci_dev_t bdf, ulong base); +void apl_uart_init(pci_dev_t bdf, ulong base); #endif diff --git a/arch/x86/include/asm/arch-broadwell/gpio.h b/arch/x86/include/asm/arch-broadwell/gpio.h index a32e2db47e..393230e52b 100644 --- a/arch/x86/include/asm/arch-broadwell/gpio.h +++ b/arch/x86/include/asm/arch-broadwell/gpio.h @@ -11,7 +11,7 @@ #define GPIO_PER_BANK 32 #define GPIO_BANKS 3 -struct broadwell_bank_platdata { +struct broadwell_bank_plat { uint16_t base_addr; const char *bank_name; int bank; diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 29e511415c..3cd3e4fcf5 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -7,11 +7,12 @@ #ifndef __FSP_SUPPORT_H__ #define __FSP_SUPPORT_H__ +#include <signatures.h> + #include <asm/fsp/fsp_bootmode.h> #include <asm/fsp/fsp_fv.h> #include <asm/fsp/fsp_hob.h> #include <asm/fsp/fsp_infoheader.h> -#include <asm/fsp/fsp_types.h> #include <asm/fsp_arch.h> #include <asm/fsp/fsp_azalia.h> diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h deleted file mode 100644 index 3d5b17ecf1..0000000000 --- a/arch/x86/include/asm/fsp/fsp_types.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - */ - -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ - -/** - * Returns a 16-bit signature built from 2 ASCII characters. - * - * This macro returns a 16-bit value built from the two ASCII characters - * specified by A and B. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * - * @return: A 16-bit value built from the two ASCII characters specified by - * A and B. - */ -#define SIGNATURE_16(A, B) ((A) | (B << 8)) - -/** - * Returns a 32-bit signature built from 4 ASCII characters. - * - * This macro returns a 32-bit value built from the four ASCII characters - * specified by A, B, C, and D. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * @C: The third ASCII character. - * @D: The fourth ASCII character. - * - * @return: A 32-bit value built from the two ASCII characters specified by - * A, B, C and D. - */ -#define SIGNATURE_32(A, B, C, D) \ - (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) - -/** - * Returns a 64-bit signature built from 8 ASCII characters. - * - * This macro returns a 64-bit value built from the eight ASCII characters - * specified by A, B, C, D, E, F, G,and H. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * @C: The third ASCII character. - * @D: The fourth ASCII character. - * @E: The fifth ASCII character. - * @F: The sixth ASCII character. - * @G: The seventh ASCII character. - * @H: The eighth ASCII character. - * - * @return: A 64-bit value built from the two ASCII characters specified by - * A, B, C, D, E, F, G and H. - */ -#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ - (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) - -#endif diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 58e4d7b831..a45ae3463c 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -8,7 +8,7 @@ #include <asm-generic/gpio.h> -struct ich6_bank_platdata { +struct ich6_bank_plat { uint16_t base_addr; const char *bank_name; int offset; diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h index 00868d1725..44eedc205c 100644 --- a/arch/x86/include/asm/intel_pinctrl.h +++ b/arch/x86/include/asm/intel_pinctrl.h @@ -162,16 +162,15 @@ extern const struct pinctrl_ops intel_pinctrl_ops; int intel_pinctrl_probe(struct udevice *dev); /** - * intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup + * intel_pinctrl_of_to_plat() - Handle common plat setup * * @dev: Pinctrl device * @comm: Pad community for this device * @num_cfgs: Number of configuration words for each pad * @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error */ -int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, - const struct pad_community *comm, - int num_cfgs); +int intel_pinctrl_of_to_plat(struct udevice *dev, + const struct pad_community *comm, int num_cfgs); /** * pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h index f7d3240384..6d4793277e 100644 --- a/arch/x86/include/asm/itss.h +++ b/arch/x86/include/asm/itss.h @@ -11,6 +11,8 @@ #ifndef _ASM_ARCH_ITSS_H #define _ASM_ARCH_ITSS_H +#include <irq.h> + #define GPIO_IRQ_START 50 #define GPIO_IRQ_END ITSS_MAX_IRQ @@ -42,4 +44,23 @@ /* ITSS Power reduction control */ #define PCR_ITSS_ITSSPRC 0x3300 +struct itss_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* Put this first since driver model will copy the data here */ + struct dtd_intel_itss dtplat; +#endif +}; + +/* struct pmc_route - Routing for PMC to GPIO */ +struct pmc_route { + u32 pmc; + u32 gpio; +}; + +struct itss_priv { + struct pmc_route *route; + uint route_count; + u32 irq_snapshot[NUM_IPC_REGS]; +}; + #endif /* _ASM_ARCH_ITSS_H */ diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 5f9b8c6564..1e4e35321d 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -114,7 +114,7 @@ typedef void (*mp_run_func)(void *arg); * Running on anything other than the boot CPU is only supported if * CONFIG_SMP_AP_WORK is enabled * - * @cpu_select: CPU to run on (its dev->req_seq value), or MP_SELECT_ALL for + * @cpu_select: CPU to run on (its dev_seq() value), or MP_SELECT_ALL for * all, or MP_SELECT_BSP for BSP * @func: Function to run * @arg: Argument to pass to the function diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h new file mode 100644 index 0000000000..6f63eae8e2 --- /dev/null +++ b/arch/x86/include/asm/p2sb.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + */ + +#ifndef ASM_P2SB_H +#define ASM_P2SB_H + +/* Platform data for the P2SB */ +struct p2sb_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_p2sb dtplat; +#endif + ulong mmio_base; + pci_dev_t bdf; +}; + +#endif /* ASM_P2SB_H */ diff --git a/arch/x86/include/asm/pmu.h b/arch/x86/include/asm/pmu.h index b76bdf64a3..818e80881e 100644 --- a/arch/x86/include/asm/pmu.h +++ b/arch/x86/include/asm/pmu.h @@ -2,9 +2,9 @@ /* * Copyright (c) 2017 Intel Corporation */ -#ifndef _X86_ASM_PMU_IPC_H_ -#define _X86_ASM_PMU_IPC_H_ +#ifndef _X86_ASM_PMU_H_ +#define _X86_ASM_PMU_H_ int pmu_turn_power(unsigned int lss, bool on); -#endif /* _X86_ASM_PMU_IPC_H_ */ +#endif /* _X86_ASM_PMU_H_ */ diff --git a/arch/x86/include/asm/sysreset.h b/arch/x86/include/asm/sysreset.h new file mode 100644 index 0000000000..5e586f51c0 --- /dev/null +++ b/arch/x86/include/asm/sysreset.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + */ +#ifndef _X86_ASM_SYSRESET_H_ +#define _X86_ASM_SYSRESET_H_ + +#include <dt-structs.h> + +struct x86_sysreset_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_x86_reset dtplat; +#endif + + struct udevice *pch; +}; + +#endif /* _X86_ASM_SYSRESET_H_ */ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 4fd8dc8ad9..9a41ecb587 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -74,7 +74,7 @@ int acpi_create_madt_lapics(u32 current) for (uclass_find_first_device(UCLASS_CPU, &dev); dev; uclass_find_next_device(&dev)) { - struct cpu_platdata *plat = dev_get_parent_platdata(dev); + struct cpu_plat *plat = dev_get_parent_plat(dev); int length; length = acpi_create_madt_lapic( diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 6534b6690b..a029237d08 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -80,7 +80,7 @@ static int save_vesa_mode(struct vesa_mode_info *vesa) static int fsp_video_probe(struct udevice *dev) { - struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct vesa_mode_info *vesa = &mode_info.vesa; int ret; @@ -124,7 +124,7 @@ err: static int fsp_video_bind(struct udevice *dev) { - struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); /* Set the maximum supported resolution */ plat->size = 2560 * 1600 * 4; diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 1c49c41b31..562a27c557 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -81,7 +81,7 @@ void mp_write_processor(struct mp_config_table *mc) for (uclass_find_first_device(UCLASS_CPU, &dev); dev; uclass_find_next_device(&dev)) { - struct cpu_platdata *plat = dev_get_parent_platdata(dev); + struct cpu_plat *plat = dev_get_parent_plat(dev); u8 cpuflag = MPC_CPU_EN; if (!device_active(dev)) diff --git a/arch/x86/lib/pmu.c b/arch/x86/lib/pmu.c index 3cd7b1f536..083aec8d8d 100644 --- a/arch/x86/lib/pmu.c +++ b/arch/x86/lib/pmu.c @@ -113,5 +113,5 @@ U_BOOT_DRIVER(intel_mid_pmu) = { .id = UCLASS_SYSCON, .of_match = pmu_mid_match, .probe = pmu_mid_probe, - .priv_auto_alloc_size = sizeof(struct pmu_mid), + .priv_auto = sizeof(struct pmu_mid), }; diff --git a/arch/x86/lib/scu.c b/arch/x86/lib/scu.c index d29d701631..90ef239bcd 100644 --- a/arch/x86/lib/scu.c +++ b/arch/x86/lib/scu.c @@ -227,5 +227,5 @@ U_BOOT_DRIVER(scu_ipc) = { .id = UCLASS_SYSCON, .of_match = scu_ipc_match, .probe = scu_ipc_probe, - .priv_auto_alloc_size = sizeof(struct scu), + .priv_auto = sizeof(struct scu), }; diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c index b48bd5d8f3..85e963b634 100644 --- a/arch/x86/lib/sfi.c +++ b/arch/x86/lib/sfi.c @@ -84,7 +84,7 @@ static int sfi_write_cpus(struct table_info *tab) for (uclass_find_first_device(UCLASS_CPU, &dev); dev; uclass_find_next_device(&dev)) { - struct cpu_platdata *plat = dev_get_parent_platdata(dev); + struct cpu_plat *plat = dev_get_parent_plat(dev); if (!device_active(dev)) continue; diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 15b0212d19..04ff32277f 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -133,14 +133,16 @@ void spl_board_init(void) * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does * the auto allocation (after relocation). */ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static const struct udevice_id tpl_fake_pci_ids[] = { { .compatible = "pci-x86" }, { } }; +#endif U_BOOT_DRIVER(pci_x86) = { .name = "pci_x86", .id = UCLASS_SIMPLE_BUS, - .of_match = tpl_fake_pci_ids, + .of_match = of_match_ptr(tpl_fake_pci_ids), }; #endif diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 24a503d011..708025b207 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -15,6 +15,7 @@ #define LOG_CATEGORY LOGC_BOOT #include <common.h> +#include <bootm.h> #include <command.h> #include <env.h> #include <irq_func.h> @@ -330,7 +331,12 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, } if (cmd_line) { + int max_size = 0xff; + int ret; + log_debug("Setup cmdline\n"); + if (bootproto >= 0x0206) + max_size = hdr->cmdline_size; if (bootproto >= 0x0202) { hdr->cmd_line_ptr = (uintptr_t)cmd_line; } else if (bootproto >= 0x0200) { @@ -346,6 +352,14 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, strcpy(cmd_line, (char *)cmdline_force); else build_command_line(cmd_line, auto_boot); + ret = bootm_process_cmdline(cmd_line, max_size, BOOTM_CL_ALL); + if (ret) { + printf("Cmdline setup failed (err=%d)\n", ret); + return ret; + } + printf("Kernel command line: \""); + puts(cmd_line); + printf("\"\n"); } if (IS_ENABLED(CONFIG_INTEL_MID) && bootproto >= 0x0207) diff --git a/arch/xtensa/include/asm/spl.h b/arch/xtensa/include/asm/spl.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/arch/xtensa/include/asm/spl.h |