diff options
Diffstat (limited to 'arch')
45 files changed, 922 insertions, 89 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index d30676ae81..55b9a5eb8a 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -67,6 +67,7 @@ config ARM config M68K bool "M68000 architecture" select HAVE_PRIVATE_LIBGCC + select USE_PRIVATE_LIBGCC select NEEDS_MANUAL_RELOC select SYS_BOOT_GET_CMDLINE select SYS_BOOT_GET_KBD diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c51f15fcf4..f0118e2254 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1956,7 +1956,8 @@ config ARCH_ROCKCHIP imply ADC imply CMD_DM imply DEBUG_UART_BOARD_INIT - imply DISTRO_DEFAULTS + imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399 + imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS imply FAT_WRITE imply SARADC_ROCKCHIP imply SPL_SYSRESET diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi index 578ef368e2..a6b4b87f18 100644 --- a/arch/arm/dts/axp803.dtsi +++ b/arch/arm/dts/axp803.dtsi @@ -25,16 +25,6 @@ compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; gpio-controller; #gpio-cells = <2>; - - gpio0_ldo: gpio0-ldo-pin { - pins = "GPIO0"; - function = "ldo"; - }; - - gpio1_ldo: gpio1-ldo-pin { - pins = "GPIO1"; - function = "ldo"; - }; }; battery_power_supply: battery-power { diff --git a/arch/arm/dts/meson-g12b-odroid-go-ultra-u-boot.dtsi b/arch/arm/dts/meson-g12b-odroid-go-ultra-u-boot.dtsi index 00852f5e54..1c0f9765eb 100644 --- a/arch/arm/dts/meson-g12b-odroid-go-ultra-u-boot.dtsi +++ b/arch/arm/dts/meson-g12b-odroid-go-ultra-u-boot.dtsi @@ -14,3 +14,11 @@ &usb3_pcie_phy { /delete-property/ phy-supply; }; + +&vcc_2v3 { + regulator-init-microvolt = <2400000>; +}; + +&vdd_ee { + regulator-init-microvolt = <875000>; +}; diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi index fe6aba70d1..7bcbc2967a 100644 --- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi +++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi @@ -52,7 +52,6 @@ }; &timer3 { - compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; clock-frequency = <24000000>; bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index a27a3adc08..27735c49dd 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -11,7 +11,7 @@ }; &uart0 { - bootph-all; + u-boot,dm-pre-reloc; clock-frequency = <24000000>; status = "okay"; }; diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index 4e79173833..589332503e 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -13,6 +13,6 @@ &uart2 { clock-frequency = <24000000>; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index ed47efa44b..04bbb01b5d 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -9,16 +9,20 @@ / { chosen { stdout-path = &uart2; - u-boot,spl-boot-order = "same-as-spl", &sdmmc0; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; }; }; -&sdmmc0 { - status = "okay"; +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "disabled"; }; &uart2 { clock-frequency = <24000000>; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts index a2f2baa4ea..917f5b2b8a 100644 --- a/arch/arm/dts/rk3568-rock-3a.dts +++ b/arch/arm/dts/rk3568-rock-3a.dts @@ -1,22 +1,37 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 Akash Gajjar <gajjar04akash@gmail.com> - */ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3568.dtsi" / { model = "Radxa ROCK3 Model A"; compatible = "radxa,rock3a", "rockchip,rk3568"; + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + chosen: chosen { stdout-path = "serial2:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + gmac1_clkin: external-gmac1-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -24,13 +39,93 @@ #clock-cells = <0>; }; + leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c_03"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_sys: vcc3v3-sys-regulator { @@ -91,6 +186,7 @@ enable-active-high; gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; regulator-name = "vcc5v0_usb_otg"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -164,7 +260,43 @@ clock_in_out = "input"; phy-handle = <&rgmii_phy1>; phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; pinctrl-names = "default"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { status = "okay"; }; @@ -441,6 +573,13 @@ }; &i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&i2s2_2ch { rockchip,trcm-sync-tx-only; status = "okay"; }; @@ -457,6 +596,27 @@ }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie30phy { + phy-supply = <&vcc3v3_pi6c_03>; + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { cam { vcc_cam_en: vcc_cam_en { @@ -551,6 +711,78 @@ status = "okay"; }; +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + /* vddio comes from regulator on module, use IO bank voltage instead */ + }; +}; + &uart2 { status = "okay"; }; @@ -607,3 +839,20 @@ phy-supply = <&vcc5v0_usb_host>; status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index ecf88e0841..0a764ce511 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -12,7 +12,7 @@ }; chosen { - u-boot,spl-boot-order = &sdhci, &sdmmc0; + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0; }; dmc: dmc { @@ -34,11 +34,6 @@ }; }; -&combphy1 { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; -}; - &cru { bootph-all; status = "okay"; diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi index 3235bd36e4..612966492b 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi @@ -18,7 +18,7 @@ &sdmmc { bus-width = <4>; - bootph-all; + u-boot,dm-pre-reloc; u-boot,spl-fifo-mode; status = "okay"; }; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 1e225d71ef..f880f4a167 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -8,12 +8,12 @@ / { dmc { compatible = "rockchip,rk3588-dmc"; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; pmu1_grf: syscon@fd58a000 { - bootph-all; + u-boot,dm-pre-reloc; compatible = "rockchip,rk3588-pmu1-grf", "syscon"; reg = <0x0 0xfd58a000 0x0 0x2000>; }; @@ -46,26 +46,26 @@ }; &xin24m { - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; &cru { - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &sys_grf { - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &uart2 { clock-frequency = <24000000>; - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &ioc { - bootph-pre-ram; + u-boot,dm-spl; }; diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts index c00c4c1e9e..576eae1322 100644 --- a/arch/arm/dts/sun50i-a64-pinebook.dts +++ b/arch/arm/dts/sun50i-a64-pinebook.dts @@ -406,6 +406,20 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723cs-bt"; + device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ + enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; +}; + &usb_otg { dr_mode = "host"; }; diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts index 649b146dff..d6897ec979 100644 --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -5,6 +5,7 @@ #include "sun50i-h6.dtsi" #include "sun50i-h6-cpu-opp.dtsi" +#include "sun50i-h6-gpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/sun50i-h6-gpu-opp.dtsi b/arch/arm/dts/sun50i-h6-gpu-opp.dtsi new file mode 100644 index 0000000000..b48049c4fc --- /dev/null +++ b/arch/arm/dts/sun50i-h6-gpu-opp.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2022 Clément Péron <peron.clem@gmail.com> + +/ { + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <810000 810000 1200000>; + }; + + opp-264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-microvolt = <810000 810000 1200000>; + }; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <810000 810000 1200000>; + }; + + opp-336000000 { + opp-hz = /bits/ 64 <336000000>; + opp-microvolt = <810000 810000 1200000>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + opp-microvolt = <820000 820000 1200000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <830000 830000 1200000>; + }; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <840000 840000 1200000>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <850000 850000 1200000>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <860000 860000 1200000>; + }; + + opp-456000000 { + opp-hz = /bits/ 64 <456000000>; + opp-microvolt = <870000 870000 1200000>; + }; + + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <890000 890000 1200000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <910000 910000 1200000>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-microvolt = <930000 930000 1200000>; + }; + + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <950000 950000 1200000>; + }; + + opp-756000000 { + opp-hz = /bits/ 64 <756000000>; + opp-microvolt = <1040000 1040000 1200000>; + }; + }; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index afbbfc2526..3c85c8cc8e 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -161,6 +161,7 @@ clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; clock-names = "bus", "mod"; resets = <&ccu RST_BUS_VP9>; + iommus = <&iommu 5>; }; video-codec@1c0e000 { @@ -186,6 +187,7 @@ clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; clock-names = "core", "bus"; resets = <&ccu RST_BUS_GPU>; + #cooling-cells = <2>; status = "disabled"; }; @@ -1070,9 +1072,55 @@ }; gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; + polling-delay-passive = <1000>; + polling-delay = <2000>; thermal-sensors = <&ths 1>; + + trips { + gpu_alert0: gpu-alert-0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert1: gpu-alert-1 { + temperature = <100000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert2: gpu-alert-2 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + // Forbid the GPU to go over 756MHz + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu 1 THERMAL_NO_LIMIT>; + }; + + // Forbid the GPU to go over 624MHz + map1 { + trip = <&gpu_alert1>; + cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; + }; + + // Forbid the GPU to go over 576MHz + map2 { + trip = <&gpu_alert2>; + cooling-device = <&gpu 3 THERMAL_NO_LIMIT>; + }; + }; }; }; }; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index 02893f3ac9..cb8600d0ea 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -49,8 +49,24 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + }; }; +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + &emac0 { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; @@ -76,6 +92,10 @@ status = "okay"; }; +&ohci1 { + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -211,3 +231,24 @@ pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts index 6619db3471..07424c28b6 100644 --- a/arch/arm/dts/sun50i-h616-x96-mate.dts +++ b/arch/arm/dts/sun50i-h616-x96-mate.dts @@ -32,6 +32,14 @@ }; }; +&ehci0 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + &ir { status = "okay"; }; @@ -54,6 +62,14 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -175,3 +191,12 @@ pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; + +&usbotg { + dr_mode = "host"; /* USB A type receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi index 622a1f7d16..74aed0d232 100644 --- a/arch/arm/dts/sun50i-h616.dtsi +++ b/arch/arm/dts/sun50i-h616.dtsi @@ -504,6 +504,166 @@ }; }; + usbotg: usb@5100000 { + compatible = "allwinner,sun50i-h616-musb", + "allwinner,sun8i-h3-musb"; + reg = <0x05100000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@5100400 { + compatible = "allwinner,sun50i-h616-usb-phy"; + reg = <0x05100400 0x24>, + <0x05101800 0x14>, + <0x05200800 0x14>, + <0x05310800 0x14>, + <0x05311800 0x14>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>, + <&ccu CLK_USB_PHY3>, + <&ccu CLK_BUS_EHCI2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy", + "pmu2_clk"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>, + <&ccu RST_USB_PHY3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@5101000 { + compatible = "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg = <0x05101000 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@5101400 { + compatible = "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg = <0x05101400 0x100>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@5200000 { + compatible = "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg = <0x05200000 0x100>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@5200400 { + compatible = "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg = <0x05200400 0x100>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@5310000 { + compatible = "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg = <0x05310000 0x100>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_BUS_EHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>, + <&ccu RST_BUS_EHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@5310400 { + compatible = "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg = <0x05310400 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci3: usb@5311000 { + compatible = "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg = <0x05311000 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_BUS_EHCI3>, + <&ccu CLK_USB_OHCI3>; + resets = <&ccu RST_BUS_OHCI3>, + <&ccu RST_BUS_EHCI3>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@5311400 { + compatible = "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg = <0x05311400 0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_USB_OHCI3>; + resets = <&ccu RST_BUS_OHCI3>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + rtc: rtc@7000000 { compatible = "allwinner,sun50i-h616-rtc"; reg = <0x07000000 0x400>; diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi index 0edc172440..9455d27e51 100644 --- a/arch/arm/dts/suniv-f1c100s.dtsi +++ b/arch/arm/dts/suniv-f1c100s.dtsi @@ -166,6 +166,12 @@ drive-strength = <30>; }; + /omit-if-no-ref/ + i2c0_pd_pins: i2c0-pd-pins { + pins = "PD0", "PD12"; + function = "i2c0"; + }; + spi0_pc_pins: spi0-pc-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; @@ -177,6 +183,42 @@ }; }; + i2c0: i2c@1c27000 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27000 0x400>; + interrupts = <7>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@1c27400 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27400 0x400>; + interrupts = <8>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@1c27800 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27800 0x400>; + interrupts = <9>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer@1c20c00 { compatible = "allwinner,suniv-f1c100s-timer"; reg = <0x01c20c00 0x90>; @@ -192,6 +234,34 @@ clocks = <&osc32k>; }; + pwm: pwm@1c21000 { + compatible = "allwinner,suniv-f1c100s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21000 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@1c22c00 { + compatible = "allwinner,suniv-f1c100s-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c22c00 0x400>; + clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR>; + interrupts = <6>; + status = "disabled"; + }; + + lradc: lradc@1c23400 { + compatible = "allwinner,suniv-f1c100s-lradc", + "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01c23400 0x400>; + interrupts = <22>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>; diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi index e899d14f38..1d1d127cf3 100644 --- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi @@ -89,13 +89,13 @@ }; reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; }; wifi_pwrseq: wifi_pwrseq { diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi index 6439141860..fc1af9b608 100644 --- a/arch/arm/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/dts/sunxi-h3-h5.dtsi @@ -302,6 +302,8 @@ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; status = "disabled"; }; @@ -312,6 +314,8 @@ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 95169bae1c..3e051e36f1 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -25,6 +25,7 @@ #include <cpu_func.h> #include <irq_func.h> #include <linux/delay.h> +#include <stdio.h> __weak void reset_misc(void) { @@ -33,8 +34,7 @@ __weak void reset_misc(void) int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { puts ("resetting ...\n"); - - mdelay(50); /* wait 50 ms */ + flush(); disable_interrupts(); diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 2ae2d3d97c..490664f878 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -224,6 +224,8 @@ struct bcm2835_mbox_tag_set_power_state { }; #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 +#define BCM2835_MBOX_TAG_GET_MAX_CLOCK_RATE 0x00030004 +#define BCM2835_MBOX_TAG_GET_MIN_CLOCK_RATE 0x00030007 #define BCM2835_MBOX_CLOCK_ID_EMMC 1 #define BCM2835_MBOX_CLOCK_ID_UART 2 @@ -250,6 +252,22 @@ struct bcm2835_mbox_tag_get_clock_rate { } body; }; +#define BCM2835_MBOX_TAG_SET_SDHOST_CLOCK 0x00038042 + +struct bcm2835_mbox_tag_set_sdhost_clock { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 rate_hz; + } req; + struct { + u32 rate_hz; + u32 rate_1; + u32 rate_2; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001 struct bcm2835_mbox_tag_allocate_buffer { diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h index eb3da93cc2..e54da86e35 100644 --- a/arch/arm/mach-bcm283x/include/mach/msg.h +++ b/arch/arm/mach-bcm283x/include/mach/msg.h @@ -23,6 +23,16 @@ int bcm2835_power_on_module(u32 module); int bcm2835_get_mmc_clock(u32 clock_id); /** + * bcm2835_set_sdhost_clock() - determine if firmware controls sdhost cdiv + * + * @rate_hz: Input clock frequency + * @rate_1: Returns a clock frequency + * @rate_2: Returns a clock frequency + * @return 0 of OK, -EIO on error + */ +int bcm2835_set_sdhost_clock(u32 rate_hz, u32 *rate_1, u32 *rate_2); + +/** * bcm2835_get_video_size() - get the current display size * * @widthp: Returns the width in pixels diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c index fe243e2dca..2188b38d84 100644 --- a/arch/arm/mach-bcm283x/msg.c +++ b/arch/arm/mach-bcm283x/msg.c @@ -21,6 +21,12 @@ struct msg_get_clock_rate { u32 end_tag; }; +struct msg_set_sdhost_clock { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_set_sdhost_clock set_sdhost_clock; + u32 end_tag; +}; + struct msg_query { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_physical_w_h physical_w_h; @@ -75,6 +81,7 @@ int bcm2835_get_mmc_clock(u32 clock_id) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1); int ret; + u32 clock_rate = 0; ret = bcm2835_power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI); if (ret) @@ -90,7 +97,45 @@ int bcm2835_get_mmc_clock(u32 clock_id) return -EIO; } - return msg_clk->get_clock_rate.body.resp.rate_hz; + clock_rate = msg_clk->get_clock_rate.body.resp.rate_hz; + + if (clock_rate == 0) { + BCM2835_MBOX_INIT_HDR(msg_clk); + BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_MAX_CLOCK_RATE); + msg_clk->get_clock_rate.body.req.clock_id = clock_id; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr); + if (ret) { + printf("bcm2835: Could not query max eMMC clock rate\n"); + return -EIO; + } + + clock_rate = msg_clk->get_clock_rate.body.resp.rate_hz; + } + + return clock_rate; +} + +int bcm2835_set_sdhost_clock(u32 rate_hz, u32 *rate_1, u32 *rate_2) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_sdhost_clock, msg_sdhost_clk, 1); + int ret; + + BCM2835_MBOX_INIT_HDR(msg_sdhost_clk); + BCM2835_MBOX_INIT_TAG(&msg_sdhost_clk->set_sdhost_clock, SET_SDHOST_CLOCK); + + msg_sdhost_clk->set_sdhost_clock.body.req.rate_hz = rate_hz; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_sdhost_clk->hdr); + if (ret) { + printf("bcm2835: Could not query sdhost clock rate\n"); + return -EIO; + } + + *rate_1 = msg_sdhost_clk->set_sdhost_clock.body.resp.rate_1; + *rate_2 = msg_sdhost_clk->set_sdhost_clock.body.resp.rate_2; + + return 0; } int bcm2835_get_video_size(int *widthp, int *heightp) diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 17d3228cba..db4a32cd46 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -55,7 +55,6 @@ #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0 -/* Use Last 2K as Scratch pad */ -#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000000 +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 #endif /* __ASM_ARCH_AM62_HARDWARE_H */ diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 4a08820a09..69ef19cc85 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -82,7 +82,7 @@ static struct mm_region rk3568_mem_map[] = { }; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000", [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000", }; diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 2ee1db4767..18e67b5ca9 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -8,6 +8,7 @@ #include <spl.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/ioc_rk3588.h> @@ -36,6 +37,12 @@ DECLARE_GLOBAL_DATA_PTR; #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0", + [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000", +}; + static struct mm_region rk3588_mem_map[] = { { .virt = 0x0UL, diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c index 331288e006..b02ea29f63 100644 --- a/arch/m68k/cpu/mcf523x/interrupts.c +++ b/arch/m68k/cpu/mcf523x/interrupts.c @@ -22,7 +22,7 @@ int interrupt_init(void) return 0; } -#if defined(CONFIG_MCFTMR) +#if defined(CFG_MCFTMR) void dtimer_intr_setup(void) { int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c index e8a1e132d2..e787c7605f 100644 --- a/arch/m68k/cpu/mcf52x2/interrupts.c +++ b/arch/m68k/cpu/mcf52x2/interrupts.c @@ -34,7 +34,7 @@ int interrupt_init(void) return 0; } -#if defined(CONFIG_MCFTMR) +#if defined(CFG_MCFTMR) void dtimer_intr_setup(void) { intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE); @@ -42,7 +42,7 @@ void dtimer_intr_setup(void) clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI); } -#endif /* CONFIG_MCFTMR */ +#endif /* CFG_MCFTMR */ #endif /* CONFIG_M5272 */ #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \ @@ -63,7 +63,7 @@ int interrupt_init(void) return 0; } -#if defined(CONFIG_MCFTMR) +#if defined(CFG_MCFTMR) void dtimer_intr_setup(void) { int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); @@ -72,7 +72,7 @@ void dtimer_intr_setup(void) clrbits_be32(&intp->imrl0, 0x00000001); clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK); } -#endif /* CONFIG_MCFTMR */ +#endif /* CFG_MCFTMR */ #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ #if defined(CONFIG_M5249) || defined(CONFIG_M5253) @@ -83,11 +83,11 @@ int interrupt_init(void) return 0; } -#if defined(CONFIG_MCFTMR) +#if defined(CFG_MCFTMR) void dtimer_intr_setup(void) { mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI); } -#endif /* CONFIG_MCFTMR */ +#endif /* CFG_MCFTMR */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index dbe2b54e41..cef8d79aad 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -132,7 +132,8 @@ _start: * then (and always) gd struct space will be reserved */ move.l %sp, -(%sp) - bsr board_init_f_alloc_reserve + move.l #board_init_f_alloc_reserve, %a1 + jsr (%a1) /* update stack and frame-pointers */ move.l %d0, %sp @@ -140,14 +141,17 @@ _start: /* initialize reserved area */ move.l %d0, -(%sp) - bsr board_init_f_init_reserve + move.l #board_init_f_init_reserve, %a1 + jsr (%a1) /* run low-level CPU init code (from flash) */ - bsr cpu_init_f + move.l #cpu_init_f, %a1 + jsr (%a1) /* run low-level board init code (from flash) */ clr.l %sp@- - bsr board_init_f + move.l #board_init_f, %a1 + jsr (%a1) /* board_init_f() does not return */ @@ -239,7 +243,8 @@ _fault: _exc_handler: SAVE_ALL movel %sp,%sp@- - bsr exc_handler + move.l #exc_handler, %a1 + jsr (%a1) addql #4,%sp RESTORE_ALL @@ -247,7 +252,8 @@ _exc_handler: _int_handler: SAVE_ALL movel %sp,%sp@- - bsr int_handler + move.l #int_handler, %a1 + jsr (%a1) addql #4,%sp RESTORE_ALL diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c index 64e04664a5..bbe823c0cf 100644 --- a/arch/m68k/cpu/mcf532x/interrupts.c +++ b/arch/m68k/cpu/mcf532x/interrupts.c @@ -23,7 +23,7 @@ int interrupt_init(void) return 0; } -#if defined(CONFIG_MCFTMR) +#if defined(CFG_MCFTMR) void dtimer_intr_setup(void) { int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c index ea0cf87990..fb80a879c7 100644 --- a/arch/m68k/cpu/mcf5445x/interrupts.c +++ b/arch/m68k/cpu/mcf5445x/interrupts.c @@ -26,7 +26,7 @@ int interrupt_init(void) return 0; } -#if defined(CONFIG_MCFTMR) +#if defined(CFG_MCFTMR) void dtimer_intr_setup(void) { int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts index 56c328ff0c..ebe8580a0a 100644 --- a/arch/m68k/dts/stmark2.dts +++ b/arch/m68k/dts/stmark2.dts @@ -27,7 +27,7 @@ flash: is25lp128@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <60000000>; reg = <1>; }; diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 273e843c4a..5f576ba16f 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -23,6 +23,9 @@ struct arch_global_data { #ifdef CONFIG_MCF5441x unsigned long sdhc_clk; #endif +#if defined(CONFIG_FSL_ESDHC) + u32 sdhc_per_clk; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 8207c8d5b7..74516cc621 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -16,7 +16,7 @@ #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) @@ -38,7 +38,7 @@ #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR3) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) @@ -63,7 +63,7 @@ #define CFG_SYS_NUM_IRQS (64) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) @@ -86,7 +86,7 @@ #define CFG_SYS_NUM_IRQS (64) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) @@ -105,7 +105,7 @@ #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR3) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) @@ -130,7 +130,7 @@ #define CFG_SYS_NUM_IRQS (64) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_TMR0) #define CFG_SYS_TMR_BASE (MMAP_TMR3) #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr) @@ -152,7 +152,7 @@ #define CFG_SYS_NUM_IRQS (192) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR3) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) @@ -174,7 +174,7 @@ #define CFG_SYS_NUM_IRQS (128) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR3) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) @@ -196,7 +196,7 @@ #define CFG_SYS_NUM_IRQS (64) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \ @@ -217,7 +217,7 @@ #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) @@ -239,7 +239,7 @@ #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) @@ -269,7 +269,7 @@ #define MMAP_DSPI MMAP_DSPI0 /* Timer */ -#ifdef CONFIG_MCFTMR +#ifdef CFG_MCFTMR #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) #define CFG_SYS_TMR_BASE (MMAP_DTMR1) #define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0) diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index b66d66afd2..6e1fd938f5 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -5,7 +5,7 @@ ## Build a couple of necessary functions into a private libgcc ## if the user asked for it -lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o ashrdi3.o obj-y += bdinfo.o obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/m68k/lib/ashrdi3.c b/arch/m68k/lib/ashrdi3.c new file mode 100644 index 0000000000..e144378b7f --- /dev/null +++ b/arch/m68k/lib/ashrdi3.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ashrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: + * Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. + */ + +#define BITS_PER_UNIT 8 + +typedef int SItype __attribute__((mode(SI))); +typedef unsigned int USItype __attribute__((mode(SI))); +typedef int DItype __attribute__((mode(DI))); +typedef int word_type __attribute__((mode(__word__))); + +struct DIstruct { + SItype high, low; +}; + +typedef union { + struct DIstruct s; + DItype ll; +} di_union; + +DItype __ashrdi3(DItype u, word_type b) +{ + di_union w; + word_type bm; + di_union uu; + + if (b == 0) + return u; + + uu.ll = u; + + bm = (sizeof(SItype) * BITS_PER_UNIT) - b; + if (bm <= 0) { + /* w.s.high = 1..1 or 0..0 */ + w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1); + w.s.low = uu.s.high >> -bm; + } else { + USItype carries = (USItype)uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((USItype)uu.s.low >> b) | carries; + } + + return w.ll; +} + diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c index 2ce69088d9..ca8c039623 100644 --- a/arch/m68k/lib/time.c +++ b/arch/m68k/lib/time.c @@ -25,7 +25,7 @@ static volatile ulong timestamp = 0; #define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) #endif -#if defined(CONFIG_MCFTMR) +#if defined(CFG_MCFTMR) #ifndef CFG_SYS_UDELAY_BASE # error "uDelay base not defined!" #endif @@ -111,7 +111,7 @@ ulong get_timer(ulong base) return (timestamp - base); } -#endif /* CONFIG_MCFTMR */ +#endif /* CFG_MCFTMR */ /* * This function is derived from PowerPC code (read timebase as long long). diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index b197e4b6b9..59403f40ce 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -182,7 +182,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006e0000 0x00010000>; + reg = <0x005e0000 0x00010000>; }; }; }; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index 4380dde6a0..4e12c4a40c 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -206,7 +206,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 823063969d..c6577b30c8 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -193,7 +193,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index 9193e51dc4..868cea4d18 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -204,7 +204,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 1182b4b635..f44b9bbc53 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -206,7 +206,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; |