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-rw-r--r--arch/arm/Kconfig52
-rw-r--r--arch/arm/cpu/armv7/sunxi/psci.c16
-rw-r--r--arch/arm/dts/Makefile6
-rw-r--r--arch/arm/dts/am335x-brsmarc1.dts2
-rw-r--r--arch/arm/dts/am335x-brxre1.dts2
-rw-r--r--arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi6
-rw-r--r--arch/arm/dts/px30-firefly-u-boot.dtsi84
-rw-r--r--arch/arm/dts/px30-firefly.dts531
-rw-r--r--arch/arm/dts/rk3328-u-boot.dtsi6
-rw-r--r--arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts139
-rw-r--r--arch/arm/include/asm/arch-sunxi/prcm.h2
-rw-r--r--arch/arm/mach-imx/Kconfig11
-rw-r--r--arch/arm/mach-imx/mx6/Kconfig1
-rw-r--r--arch/arm/mach-k3/am6_init.c1
-rw-r--r--arch/arm/mach-k3/common.c25
-rw-r--r--arch/arm/mach-k3/common.h1
-rw-r--r--arch/arm/mach-k3/j721e_init.c1
-rw-r--r--arch/arm/mach-rockchip/Kconfig2
-rwxr-xr-xarch/arm/mach-rockchip/fit_spl_optee.sh12
-rwxr-xr-xarch/arm/mach-rockchip/make_fit_atf.py2
-rw-r--r--arch/arm/mach-stm32mp/Kconfig3
21 files changed, 861 insertions, 44 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f9dab073ea..36c9c2fecd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -17,7 +17,7 @@ config POSITION_INDEPENDENT
be loaded to and run from that address. This option lifts that
restriction, thus allowing the code to be loaded to and executed
from almost any address. This logic relies on the relocation
- information that is embedded into the binary to support U-Boot
+ information that is embedded in the binary to support U-Boot
relocating itself to the top-of-RAM later during execution.
config INIT_SP_RELATIVE
@@ -26,7 +26,7 @@ config INIT_SP_RELATIVE
U-Boot typically uses a hard-coded value for the stack pointer
before relocation. Enable this option to instead calculate the
initial SP at run-time. This is useful to avoid hard-coding addresses
- into U-Boot, so that can be loaded and executed at arbitrary
+ into U-Boot, so that it can be loaded and executed at arbitrary
addresses and thus avoid using arbitrary addresses at runtime.
If this option is enabled, the early stack pointer is set to
@@ -57,7 +57,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
hex
help
The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
- TEXT_OFFSET value written in to the Linux kernel image header.
+ TEXT_OFFSET value written to the Linux kernel image header.
endif
endif
@@ -121,7 +121,7 @@ config SYS_ARM_MMU
select SYS_ARM_CACHE_CP15
help
Select if you want MMU-based virtualised addressing space
- support by paged memory management.
+ support via paged memory management.
config SYS_ARM_MPU
bool 'Use the ARM v7 PMSA Compliant MPU'
@@ -136,8 +136,8 @@ config SYS_ARM_MPU
# startup. Note that in general these options force the workarounds to be
# applied; no CPU-type/version detection exists, unlike the similar options in
# the Linux kernel. Do not set these options unless they apply! Also note that
-# the following can be machine specific errata. These do have ability to
-# provide rudimentary version and machine specific checks, but expect no
+# the following can be machine-specific errata. These do have ability to
+# provide rudimentary version and machine-specific checks, but expect no
# product checks:
# CONFIG_ARM_ERRATA_430973
# CONFIG_ARM_ERRATA_454179
@@ -332,7 +332,7 @@ config SYS_CACHELINE_SIZE
config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help
- Some architectures require a call to arch_cpu_init()
+ Some architectures require a call to arch_cpu_init().
Say Y here to enable it
config SYS_ARCH_TIMER
@@ -342,7 +342,7 @@ config SYS_ARCH_TIMER
help
The ARM Generic Timer (aka arch-timer) provides an architected
interface to a timer source on an SoC.
- It is mandantory for ARMv8 implementation and widely available
+ It is mandatory for ARMv8 implementation and widely available
on ARMv7 systems.
config ARM_SMCCC
@@ -385,7 +385,7 @@ config TPL_SYS_THUMB_BUILD
default y if SYS_THUMB_BUILD
depends on TPL && !ARM64
help
- Use this flag to build SPL using the Thumb instruction set for
+ Use this flag to build TPL using the Thumb instruction set for
ARM architectures. Thumb instruction set provides better code
density. For ARM architectures that support Thumb2 this flag will
result in Thumb2 code generated by GCC.
@@ -394,7 +394,7 @@ config TPL_SYS_THUMB_BUILD
config SYS_L2CACHE_OFF
bool "L2cache off"
help
- If SoC does not support L2CACHE or one do not want to enable
+ If SoC does not support L2CACHE or one does not want to enable
L2CACHE, choose this option.
config ENABLE_ARM_SOC_BOOT0_HOOK
@@ -414,7 +414,7 @@ config USE_ARCH_MEMCPY
depends on !ARM64
help
Enable the generation of an optimized version of memcpy.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMCPY
@@ -423,7 +423,7 @@ config SPL_USE_ARCH_MEMCPY
depends on !ARM64 && SPL
help
Enable the generation of an optimized version of memcpy.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMCPY
@@ -432,7 +432,7 @@ config TPL_USE_ARCH_MEMCPY
depends on !ARM64 && TPL
help
Enable the generation of an optimized version of memcpy.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMSET
@@ -441,7 +441,7 @@ config USE_ARCH_MEMSET
depends on !ARM64
help
Enable the generation of an optimized version of memset.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMSET
@@ -450,7 +450,7 @@ config SPL_USE_ARCH_MEMSET
depends on !ARM64 && SPL
help
Enable the generation of an optimized version of memset.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMSET
@@ -459,7 +459,7 @@ config TPL_USE_ARCH_MEMSET
depends on !ARM64 && TPL
help
Enable the generation of an optimized version of memset.
- Such implementation may be faster under some conditions
+ Such an implementation may be faster under some conditions
but may increase the binary size.
config SET_STACK_SIZE
@@ -467,14 +467,14 @@ config SET_STACK_SIZE
default y if ARCH_VERSAL || ARCH_ZYNQMP
help
This will enable an option to set max stack size that can be
- used by u-boot.
+ used by U-Boot.
config STACK_SIZE
- hex "Define max stack size that can be used by u-boot"
+ hex "Define max stack size that can be used by U-Boot"
depends on SET_STACK_SIZE
default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
help
- Defines Max stack size that can be used by u-boot so that the
+ Define Max stack size that can be used by U-Boot so that the
initrd_high will be calculated as base stack pointer minus this
stack size.
@@ -689,7 +689,7 @@ config TARGET_BCMNS2
help
Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
ARMv8 Cortex-A57 processors targeting a broad range of networking
- applications
+ applications.
config ARCH_EXYNOS
bool "Samsung EXYNOS"
@@ -1101,8 +1101,8 @@ config TARGET_LS2080A_EMU
select ARMV8_MULTIENTRY
select FSL_DDR_SYNC_REFRESH
help
- Support for Freescale LS2080A_EMU platform
- The LS2080A Development System (EMULATOR) is a pre silicon
+ Support for Freescale LS2080A_EMU platform.
+ The LS2080A Development System (EMULATOR) is a pre-silicon
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
@@ -1114,7 +1114,7 @@ config TARGET_LS2080A_SIMU
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
help
- Support for Freescale LS2080A_SIMU platform
+ Support for Freescale LS2080A_SIMU platform.
The LS2080A Development System (QDS) is a pre silicon
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
@@ -1130,7 +1130,7 @@ config TARGET_LS1088AQDS
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
help
- Support for NXP LS1088AQDS platform
+ Support for NXP LS1088AQDS platform.
The LS1088A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS1088A
Layerscape Architecture processor.
@@ -1149,7 +1149,7 @@ config TARGET_LS2080AQDS
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
help
- Support for Freescale LS2080AQDS platform
+ Support for Freescale LS2080AQDS platform.
The LS2080A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
@@ -1649,7 +1649,7 @@ config TFABOOT
default n
help
Enabling this will make a U-Boot binary that is capable of being
- booted via TF-A.
+ booted via TF-A (Trusted Firmware for Cortex-A).
config TI_SECURE_DEVICE
bool "HS Device Type Support"
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 2c5d99e9ac..5b689004e8 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -75,7 +75,7 @@ static void __secure __mdelay(u32 ms)
isb();
}
-static void __secure clamp_release(u32 __maybe_unused *clamp)
+static void __secure clamp_release(void __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3) || \
@@ -90,7 +90,7 @@ static void __secure clamp_release(u32 __maybe_unused *clamp)
#endif
}
-static void __secure clamp_set(u32 __maybe_unused *clamp)
+static void __secure clamp_set(void __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3) || \
@@ -99,22 +99,28 @@ static void __secure clamp_set(u32 __maybe_unused *clamp)
#endif
}
-static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
+static void __secure sunxi_power_switch(void *clamp, void *pwroff_ptr, bool on,
int cpu)
{
+ u32 pwroff;
+
+ memcpy(&pwroff, pwroff_ptr, sizeof(u32));
+
if (on) {
/* Release power clamp */
clamp_release(clamp);
/* Clear power gating */
- clrbits_le32(pwroff, BIT(cpu));
+ clrbits_le32(&pwroff, BIT(cpu));
} else {
/* Set power gating */
- setbits_le32(pwroff, BIT(cpu));
+ setbits_le32(&pwroff, BIT(cpu));
/* Activate power clamp */
clamp_set(clamp);
}
+
+ memcpy(pwroff_ptr, &pwroff, sizeof(u32));
}
#ifdef CONFIG_MACH_SUN8I_R40
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3dc9c4d41c..0127a91a82 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -68,7 +68,8 @@ dtb-$(CONFIG_ARCH_OWL) += \
bubblegum_96.dtb
dtb-$(CONFIG_ROCKCHIP_PX30) += \
- px30-evb.dtb
+ px30-evb.dtb \
+ px30-firefly.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
@@ -522,7 +523,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
- sun8i-h3-orangepi-plus2e.dtb
+ sun8i-h3-orangepi-plus2e.dtb \
+ sun8i-h3-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v40-bananapi-m2-berry.dtb
diff --git a/arch/arm/dts/am335x-brsmarc1.dts b/arch/arm/dts/am335x-brsmarc1.dts
index e1738b6dde..a63fc2da22 100644
--- a/arch/arm/dts/am335x-brsmarc1.dts
+++ b/arch/arm/dts/am335x-brsmarc1.dts
@@ -266,12 +266,14 @@
};
&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
ti,ledcr = <0x0480>;
};
&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
phy-handle = <&ethphy1>;
phy-mode = "rmii";
ti,ledcr = <0x0480>;
diff --git a/arch/arm/dts/am335x-brxre1.dts b/arch/arm/dts/am335x-brxre1.dts
index a0d046d07a..33d8ab78d8 100644
--- a/arch/arm/dts/am335x-brxre1.dts
+++ b/arch/arm/dts/am335x-brxre1.dts
@@ -221,11 +221,13 @@
};
&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
phy-handle = <&ethphy0>;
phy-mode = "mii";
};
&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <2>;
phy-handle = <&ethphy1>;
phy-mode = "mii";
};
diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
index 135b6193a9..5ac32a0ffa 100644
--- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.1.0
- * This file was generated on 09/06/2019
+ * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.2.0
+ * This file was generated on 10/09/2019
*/
#define DDRSS_PLL_FHS_CNT 10
@@ -283,7 +283,7 @@
#define DDRSS_CTL_271_DATA 0x1FFF1000
#define DDRSS_CTL_272_DATA 0x01FF0000
#define DDRSS_CTL_273_DATA 0x000101FF
-#define DDRSS_CTL_274_DATA 0xFFFF0B00
+#define DDRSS_CTL_274_DATA 0x0FFF0B00
#define DDRSS_CTL_275_DATA 0x01010001
#define DDRSS_CTL_276_DATA 0x01010101
#define DDRSS_CTL_277_DATA 0x01180101
diff --git a/arch/arm/dts/px30-firefly-u-boot.dtsi b/arch/arm/dts/px30-firefly-u-boot.dtsi
new file mode 100644
index 0000000000..bb782b4e2d
--- /dev/null
+++ b/arch/arm/dts/px30-firefly-u-boot.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+/ {
+ aliases {
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = &emmc, &sdmmc;
+ };
+};
+
+&dmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart5 {
+ clock-frequency = <24000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&pmugrf {
+ u-boot,dm-pre-reloc;
+};
+
+&xin24m {
+ u-boot,dm-pre-reloc;
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&pmucru {
+ u-boot,dm-pre-reloc;
+};
+
+&saradc {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio0 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio2 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/px30-firefly.dts b/arch/arm/dts/px30-firefly.dts
new file mode 100644
index 0000000000..c0a8e3009a
--- /dev/null
+++ b/arch/arm/dts/px30-firefly.dts
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "px30.dtsi"
+
+/ {
+ model = "Firefly Core-PX30-JD4";
+ compatible = "rockchip,px30-firefly", "rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ esc-key {
+ label = "esc";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1310000>;
+ };
+
+ home-key {
+ label = "home";
+ linux,code = <KEY_HOME>;
+ press-threshold-microvolt = <624000>;
+ };
+
+ menu-key {
+ label = "menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <987000>;
+ };
+
+ vol-down-key {
+ label = "volume down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <300000>;
+ };
+
+ vol-up-key {
+ label = "volume up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17000>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 25000 0>;
+ power-supply = <&vcc3v3_lcd>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-0 = <&emmc_reset>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
+ };
+
+ vcc5v0_sys: vccsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi {
+ status = "okay";
+
+ ports {
+ mipi_out: port@1 {
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "sitronix,st7703";
+ reg = <0>;
+ backlight = <&backlight>;
+ iovcc-supply = <&vcc_1v8>;
+ vci-supply = <&vcc3v3_lcd>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+ };
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ non-removable;
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v0>;
+ vqmmc-supply = <&vccio_flash>;
+ status = "okay";
+};
+
+&gmac {
+ clock_in_out = "output";
+ phy-supply = <&vcc_rmii>;
+ snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 50000 50000>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <0>;
+ clock-output-names = "xin32k";
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v0: vcc_rmii: DCDC_REG4 {
+ regulator-name = "vcc_3v0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG5 {
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v0: LDO_REG1 {
+ regulator-name = "vcc_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_1v0: LDO_REG3 {
+ regulator-name = "vdd_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc3v0_pmu: LDO_REG4 {
+ regulator-name = "vcc3v0_pmu";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_sd: LDO_REG6 {
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG7 {
+ regulator-name = "vcc2v8_dvp";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <2800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v5_dvp: LDO_REG9 {
+ regulator-name = "vcc1v5_dvp";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcc3v3_lcd: SWITCH_REG1 {
+ regulator-name = "vcc3v3_lcd";
+ regulator-boot-on;
+ };
+
+ vcc5v0_host: SWITCH_REG2 {
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&i2s1_2ch {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vccio_sdio>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_3v0>;
+ vccio4-supply = <&vcc3v0_pmu>;
+ vccio5-supply = <&vcc_3v0>;
+ vccio6-supply = <&vccio_flash>;
+};
+
+&pinctrl {
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins =
+ <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ emmc {
+ emmc_reset: emmc-reset {
+ rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ soc_slppin_gpio: soc_slppin_gpio {
+ rockchip,pins =
+ <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+
+ soc_slppin_slp: soc_slppin_slp {
+ rockchip,pins =
+ <0 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ soc_slppin_rst: soc_slppin_rst {
+ rockchip,pins =
+ <0 RK_PA4 2 &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins =
+ <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+
+ pmuio1-supply = <&vcc3v0_pmu>;
+ pmuio2-supply = <&vcc3v0_pmu>;
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <800>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ non-removable;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index ffbd657e31..6d5b3ec06e 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -51,8 +51,14 @@
&emmc {
u-boot,dm-pre-reloc;
+
+ /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
+ u-boot,spl-fifo-mode;
};
&sdmmc {
u-boot,dm-pre-reloc;
+
+ /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
+ u-boot,spl-fifo-mode;
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts
new file mode 100644
index 0000000000..f2f7b7a925
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ * Copyright (C) 2018 Diego Rondini <diego.rondini@kynetics.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi Zero Plus2 H3";
+ compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 58a36895e6..767d1ff98d 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -202,7 +202,7 @@
#ifndef __ASSEMBLY__
#include <linux/compiler.h>
-struct __packed sunxi_prcm_reg {
+struct sunxi_prcm_reg {
u32 cpus_cfg; /* 0x000 */
u8 res0[0x8]; /* 0x004 */
u32 apb0_ratio; /* 0x00c */
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index fee6d56c4d..4ce2799b72 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -113,3 +113,14 @@ config DDRMC_VF610_CALIBRATION
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
depends on IMX8MN
+
+config IMX_DCD_ADDR
+ hex "DCD Blocks location on the image"
+ default 0x00910000 if !ARCH_MX7ULP
+ default 0x2f010000 if ARCH_MX7ULP
+ help
+ Indicates where the Device Configuration Data, a binary table used by
+ the ROM code to configure the device at early boot stage, is located.
+ This information is shared with the user via mkimage -l just so the
+ image can be signed.
+
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ef816a24ff..1e5df9ae44 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -424,6 +424,7 @@ config TARGET_NITROGEN6X
imply USB_ETHER_MCS7830
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
+ select MX6QDL
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 99edcd9a24..a78ffbb674 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -82,6 +82,7 @@ void board_init_f(ulong dummy)
ctrl_mmr_unlock();
#ifdef CONFIG_CPU_V7R
+ disable_linefill_optimization();
setup_k3_mpu_regions();
#endif
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index bf631b74f8..50f5b81dfe 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -244,3 +244,28 @@ void board_prep_linux(bootm_headers_t *images)
CONFIG_SYS_CACHELINE_SIZE));
}
#endif
+
+#ifdef CONFIG_CPU_V7R
+void disable_linefill_optimization(void)
+{
+ u32 actlr;
+
+ /*
+ * On K3 devices there are 2 conditions where R5F can deadlock:
+ * 1.When software is performing series of store operations to
+ * cacheable write back/write allocate memory region and later
+ * on software execute barrier operation (DSB or DMB). R5F may
+ * hang at the barrier instruction.
+ * 2.When software is performing a mix of load and store operations
+ * within a tight loop and store operations are all writing to
+ * cacheable write back/write allocates memory regions, R5F may
+ * hang at one of the load instruction.
+ *
+ * To avoid the above two conditions disable linefill optimization
+ * inside Cortex R5F.
+ */
+ asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
+ actlr |= (1 << 13); /* Set DLFO bit */
+ asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
+}
+#endif
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 8f9a023921..35d1609cdc 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -16,3 +16,4 @@
void setup_k3_mpu_regions(void);
int early_console_init(void);
+void disable_linefill_optimization(void);
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index d0bf86abeb..4758739266 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -87,6 +87,7 @@ void board_init_f(ulong dummy)
ctrl_mmr_unlock();
#ifdef CONFIG_CPU_V7R
+ disable_linefill_optimization();
setup_k3_mpu_regions();
#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d8d68ba447..b689a420bd 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -306,7 +306,7 @@ config SPL_ROCKCHIP_COMMON_BOARD
no TPL for the board.
config TPL_ROCKCHIP_COMMON_BOARD
- bool ""
+ bool "Rockchip TPL common board file"
depends on TPL
help
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
diff --git a/arch/arm/mach-rockchip/fit_spl_optee.sh b/arch/arm/mach-rockchip/fit_spl_optee.sh
index 89ef04312c..4118472d9f 100755
--- a/arch/arm/mach-rockchip/fit_spl_optee.sh
+++ b/arch/arm/mach-rockchip/fit_spl_optee.sh
@@ -17,6 +17,12 @@ if [ ! -f $TEE ]; then
fi
dtname=$1
+text_base=`sed -n "/SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" .config \
+ |tr -d '\r'`
+dram_base=`sed -n "/SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" \
+ include/autoconf.mk|tr -d '\r'`
+tee_base=`echo "obase=16;$(($dram_base+0x8400000))"|bc`
+tee_base='0x'$tee_base
cat << __HEADER_EOF
/*
@@ -39,7 +45,7 @@ cat << __HEADER_EOF
os = "U-Boot";
arch = "arm";
compression = "none";
- load = <0x61000000>;
+ load = <$text_base>;
};
optee {
description = "OP-TEE";
@@ -48,8 +54,8 @@ cat << __HEADER_EOF
arch = "arm";
os = "tee";
compression = "none";
- load = <0x68400000>;
- entry = <0x68400000>;
+ load = <$tee_base>;
+ entry = <$tee_base>;
};
fdt {
description = "$(basename $dtname .dtb)";
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py
index 3c045a5e17..c79317d6c5 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python3
"""
# SPDX-License-Identifier: GPL-2.0+
#
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index c9bc084194..ae28f6e206 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -46,9 +46,8 @@ config TARGET_STM32MP1
select STM32_SERIAL
select SYS_ARCH_TIMER
imply BOOTCOUNT_LIMIT
- imply BOOTSTAGE
imply CMD_BOOTCOUNT
- imply CMD_BOOTSTAGE
+ imply CMD_CLS if CMD_BMP
imply DISABLE_CONSOLE
imply PRE_CONSOLE_BUFFER
imply SILENT_CONSOLE
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-01 19:15:26 +0000