aboutsummaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/imx6ull-colibri-emmc.dts49
-rw-r--r--arch/arm/dts/imx6ull-colibri.dts34
-rw-r--r--arch/arm/dts/imx6ull-colibri.dtsi32
-rw-r--r--arch/arm/dts/imx8mm-evk-u-boot.dtsi19
-rw-r--r--arch/arm/dts/imx8mm-verdin-u-boot.dtsi147
-rw-r--r--arch/arm/dts/imx8mm-verdin.dts18
-rw-r--r--arch/arm/dts/imx8mp-evk-u-boot.dtsi13
-rw-r--r--arch/arm/dts/imx8mp-evk.dts40
-rw-r--r--arch/arm/dts/imx8mp-u-boot.dtsi3
-rw-r--r--arch/arm/dts/phycore-imx8mm-u-boot.dtsi126
-rw-r--r--arch/arm/dts/phycore-imx8mm.dts30
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig22
-rw-r--r--arch/arm/mach-imx/mac.c2
-rw-r--r--arch/arm/mach-imx/mx7ulp/soc.c23
16 files changed, 508 insertions, 52 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b549f3c8b8..a88aecc5bd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -829,6 +829,7 @@ dtb-$(CONFIG_MX6UL) += \
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+ imx6ull-colibri-emmc.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-seeed-npi-imx6ull-dev-board.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
diff --git a/arch/arm/dts/imx6ull-colibri-emmc.dts b/arch/arm/dts/imx6ull-colibri-emmc.dts
new file mode 100644
index 0000000000..cbb561ffb4
--- /dev/null
+++ b/arch/arm/dts/imx6ull-colibri-emmc.dts
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Toradex AG
+ */
+
+#include "imx6ull-colibri.dtsi"
+#include "imx6ull-colibri-u-boot.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC)";
+ compatible = "toradex,colibri-imx6ull-emmc", "toradex,colibri-imx6ull", "fsl,imx6ull";
+
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc1;
+ };
+};
+
+/* eMMC */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2emmc>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+ bus-width = <8>;
+ keep-power-in-suspend;
+ no-1-8-v;
+ non-removable;
+ vmmc-supply = <&reg_module_3v3>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_usdhc2emmc: usdhc2emmcgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 15338a1ae3..dbe3e0206e 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2018-2019 Toradex AG
+ * Copyright 2018-2021 Toradex AG
*/
#include "imx6ull-colibri.dtsi"
@@ -10,3 +10,35 @@
model = "Toradex Colibri iMX6ULL";
compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
};
+
+/* NAND */
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpmi_nand: gpmi-nand-grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6ull-colibri.dtsi b/arch/arm/dts/imx6ull-colibri.dtsi
index b7bf79f28c..1fa9d10412 100644
--- a/arch/arm/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/dts/imx6ull-colibri.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2019 Toradex AG
+ * Copyright 2019-2021 Toradex AG
*/
/dts-v1/;
@@ -92,17 +92,6 @@
};
};
-/* NAND */
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
- nand-ecc-mode = "hw";
- nand-ecc-strength = <8>;
- nand-ecc-step-size = <512>;
- status = "okay";
-};
-
/*
* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
@@ -340,25 +329,6 @@
>;
};
- pinctrl_gpmi_nand: gpmi-nand-grp {
- fsl,pins = <
- MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
- MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
- MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
- MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
- MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
- MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
- MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
- MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
- MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
- MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
- MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
- MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
- MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
- MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
- >;
- };
-
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index f200afac9f..3c75415e8f 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -150,7 +150,9 @@
};
- flash {
+ spl {
+ filename = "spl.bin";
+
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
@@ -217,4 +219,19 @@
};
};
};
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x57c00>;
+ filename = "u-boot.itb";
+ };
+ };
};
diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
index 67c31c49b6..9fb4d8aa8c 100644
--- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
@@ -1,18 +1,37 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2020 Toradex
+ * Copyright 2020-2021 Toradex
*/
#include "imx8mm-u-boot.dtsi"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
- wdt = <&wdog1>;
u-boot,dm-spl;
+ wdt = <&wdog1>;
};
};
+&{/soc@0/bus@30800000/i2c@30a20000/pmic} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic/regulators} {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
@@ -57,11 +76,7 @@
u-boot,dm-spl;
};
-&{/soc@0/bus@30800000/i2c@30a20000/pmic} {
- u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic/regulators} {
+&pinctrl_wdog {
u-boot,dm-spl;
};
@@ -84,3 +99,121 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl.bin";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x5fc00>;
+ filename = "u-boot.itb";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts
index ac2a4b69d3..a2331627d7 100644
--- a/arch/arm/dts/imx8mm-verdin.dts
+++ b/arch/arm/dts/imx8mm-verdin.dts
@@ -196,6 +196,18 @@
};
};
+&gpio5 {
+ ctrl_sleep_moci {
+ gpio-hog;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ line-name = "CTRL_SLEEP_MOCI#";
+ output-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+ };
+};
+
/* On-module I2C */
&i2c1 {
clock-frequency = <400000>;
@@ -548,6 +560,12 @@
>;
};
+ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* SODIMM 256 */
+ >;
+ };
+
pinctrl_dsi_bkl_en: dsi_bkl_en {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 2abcf1f03d..ab849ebaac 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -111,6 +111,19 @@
u-boot,dm-spl;
};
+&eqos {
+ compatible = "fsl,imx-eqos";
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&ethphy0 {
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <15000>;
+ reset-post-delay-us = <100000>;
+};
+
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index b10dce8767..f846d69dac 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -74,6 +74,26 @@
status = "okay";
};
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ };
+ };
+};
+
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
@@ -160,6 +180,26 @@
};
&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ >;
+ };
+
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index afb3995482..120c4c4dbb 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -18,6 +18,9 @@
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
};
&osc_32k {
diff --git a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
index 91515b8df9..f842e02c77 100644
--- a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
@@ -7,6 +7,10 @@
#include "imx8mm-u-boot.dtsi"
/ {
+ binman: binman {
+ multiple-images;
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -30,6 +34,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
@@ -65,3 +73,121 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ filename = "spl.bin";
+ offset = <0x0>;
+ };
+
+ uboot: blob-ext@2 {
+ filename = "u-boot.itb";
+ offset = <0x57c00>;
+ };
+ };
+};
diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts
index c46d3c72ce..e57dfd368d 100644
--- a/arch/arm/dts/phycore-imx8mm.dts
+++ b/arch/arm/dts/phycore-imx8mm.dts
@@ -14,7 +14,7 @@
compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
- stdout-patch = &uart3;
+ stdout-path = &uart3;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -54,6 +54,23 @@
};
};
+/* SPI nor flash */
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash0: norflash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
/* i2c eeprom */
&i2c1 {
clock-frequency = <400000>;
@@ -140,6 +157,17 @@
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index bfff79f88c..07954bc201 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
+obj-$(CONFIG_DWC_ETH_QOS) += mac.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
obj-$(CONFIG_IMX_HAB) += hab.o
obj-y += cpu.o
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 41088a2dcd..276b8bd974 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -25,14 +25,14 @@ config SYS_SOC
default "imx8m"
choice
- prompt "NXP i.MX8M board select"
+ prompt "NXP i.MX8M board select"
optional
config TARGET_IMX8MQ_CM
- bool "Ronetix iMX8MQ-CM SoM"
+ bool "Ronetix iMX8MQ-CM SoM"
select BINMAN
- select IMX8MQ
- select IMX8M_LPDDR4
+ select IMX8MQ
+ select IMX8M_LPDDR4
config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
@@ -109,10 +109,11 @@ config TARGET_PICO_IMX8MQ
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MM
- bool "Support Toradex Verdin iMX8M Mini module"
- select IMX8MM
- select SUPPORT_SPL
- select IMX8M_LPDDR4
+ bool "Support Toradex Verdin iMX8M Mini module"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
config TARGET_IMX8MM_BEACON
bool "imx8mm Beacon Embedded devkit"
@@ -128,15 +129,16 @@ config TARGET_IMX8MN_BEACON
config TARGET_PHYCORE_IMX8MM
bool "PHYTEC PHYCORE i.MX8MM"
+ select BINMAN
select IMX8MM
- select SUPPORT_SPL
+ select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_PHYCORE_IMX8MP
bool "PHYTEC PHYCORE i.MX8MP"
select BINMAN
select IMX8MP
- select SUPPORT_SPL
+ select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_CL_IOT_GATE
diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
index 3b1496b203..9bb63d25b4 100644
--- a/arch/arm/mach-imx/mac.c
+++ b/arch/arm/mach-imx/mac.c
@@ -31,7 +31,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
- has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
+ has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull() || is_imx8mp();
if (has_second_mac && dev_id == 1) {
u32 value = readl(&fuse->mac_addr2);
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 7f097d6850..c90ce22404 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -13,6 +13,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/hab.h>
+#include <asm/setup.h>
#include <linux/bitops.h>
#define PMC0_BASE_ADDR 0x410a1000
@@ -380,3 +381,25 @@ enum boot_device get_boot_device(void)
return boot_dev;
}
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/*
+ * OCOTP_CFG (SJC CHALLENGE, Unique ID)
+ * i.MX 7ULP Applications Processor Reference Manual, Rev. 0, 09/2020
+ *
+ * OCOTP_CFG0 offset 0x4B0: 15:0 -> 15:0 bits of Unique ID
+ * OCOTP_CFG1 offset 0x4C0: 15:0 -> 31:16 bits of Unique ID
+ * OCOTP_CFG2 offset 0x4D0: 15:0 -> 47:32 bits of Unique ID
+ * OCOTP_CFG3 offset 0x4E0: 15:0 -> 63:48 bits of Unique ID
+ */
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ serialnr->low = (fuse->cfg0 & 0xFFFF) + ((fuse->cfg1 & 0xFFFF) << 16);
+ serialnr->high = (fuse->cfg2 & 0xFFFF) + ((fuse->cfg3 & 0xFFFF) << 16);
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-30 15:42:01 +0000