diff options
Diffstat (limited to 'arch')
23 files changed, 210 insertions, 30 deletions
diff --git a/arch/arm/dts/armada-388-helios4-u-boot.dtsi b/arch/arm/dts/armada-388-helios4-u-boot.dtsi index f0da9f42de..0753889854 100644 --- a/arch/arm/dts/armada-388-helios4-u-boot.dtsi +++ b/arch/arm/dts/armada-388-helios4-u-boot.dtsi @@ -14,6 +14,9 @@ &spi1 { u-boot,dm-spl; + spi-flash@0 { + u-boot,dm-spl; + }; }; &w25q32 { @@ -21,6 +24,18 @@ u-boot,dm-spl; }; +&gpio0 { + u-boot,dm-spl; +}; + +&ahci0 { + u-boot,dm-spl; +}; + +&ahci1 { + u-boot,dm-spl; +}; + &sdhci { u-boot,dm-spl; }; diff --git a/arch/arm/dts/armada-388-helios4.dts b/arch/arm/dts/armada-388-helios4.dts index a154e0f4f4..fb49df2a3b 100644 --- a/arch/arm/dts/armada-388-helios4.dts +++ b/arch/arm/dts/armada-388-helios4.dts @@ -140,11 +140,6 @@ soc { internal-regs { i2c@11000 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - /* * PCA9655 GPIO expander, up to 1MHz clock. * 0-Board Revision bit 0 # @@ -187,8 +182,7 @@ gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; input; - line-name = - "usb-overcurrent-status"; + line-name = "usb-overcurrent-status"; }; }; @@ -248,7 +242,7 @@ bus-width = <4>; cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; no-1-8-v; - pinctrl-0 = <µsom_sdhci_pins + pinctrl-0 = <&helios_sdhci_pins &helios_sdhci_cd_pins>; pinctrl-names = "default"; status = "okay"; @@ -286,6 +280,12 @@ marvell,pins = "mpp20"; marvell,function = "gpio"; }; + helios_sdhci_pins: helios-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; helios_led_pins: helios-led-pins { marvell,pins = "mpp24", "mpp25", "mpp49", "mpp50", diff --git a/arch/arm/dts/kirkwood-d2net-u-boot.dtsi b/arch/arm/dts/kirkwood-d2net-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-d2net-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-is2-u-boot.dtsi b/arch/arm/dts/kirkwood-is2-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-is2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-net2big-u-boot.dtsi b/arch/arm/dts/kirkwood-net2big-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-net2big-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-ns2-u-boot.dtsi b/arch/arm/dts/kirkwood-ns2-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-ns2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi b/arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-ns2max-u-boot.dtsi b/arch/arm/dts/kirkwood-ns2max-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-ns2max-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi b/arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h new file mode 100644 index 0000000000..9ac16f599e --- /dev/null +++ b/arch/arm/include/asm/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARM_MMU_H +#define __ASM_ARM_MMU_H + +void init_addr_map(void); + +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index b8c1b4ea74..37c1bfd726 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -207,7 +207,7 @@ int __asm_invalidate_l3_icache(void); void __asm_switch_ttbr(u64 new_ttbr); /* - * Switch from EL3 to EL2 for ARMv8 + * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8 * * @args: For loading 64-bit OS, fdt address. * For loading 32-bit OS, zero. @@ -222,7 +222,7 @@ void __asm_switch_ttbr(u64 new_ttbr); void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, u64 arg4, u64 entry_point, u64 es_flag); /* - * Switch from EL2 to EL1 for ARMv8 + * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8 * * @args: For loading 64-bit OS, fdt address. * For loading 32-bit OS, zero. @@ -248,11 +248,12 @@ void flush_l3_cache(void); void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); /* - *Issue a secure monitor call in accordance with ARM "SMC Calling convention", + * smc_call() - issue a secure monitor call + * + * Issue a secure monitor call in accordance with ARM "SMC Calling convention", * DEN0028A * * @args: input and output arguments - * */ void smc_call(struct pt_regs *args); @@ -521,10 +522,12 @@ enum { #endif /** + * mmu_page_table_flush() - register an update to page tables + * * Register an update to the page tables, and flush the TLB * - * \param start start address of update in page table - * \param stop stop address of update in page table + * @start: start address of update in page table + * @stop: stop address of update in page table */ void mmu_page_table_flush(unsigned long start, unsigned long stop); @@ -585,11 +588,26 @@ s32 psci_features(u32 function_id, u32 psci_fid); void save_boot_params_ret(void); /** + * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping + * + * Change the virt/phys mapping and cache settings for a region. + * + * @virt: virtual start address of memory region to change + * @phys: physical address for the memory region to set + * @size: size of memory region to change + * @option: dcache option to select + */ +void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, + size_t size, enum dcache_option option); + +/** + * mmu_set_region_dcache_behaviour() - set cache settings + * * Change the cache settings for a region. * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select + * @start: start address of memory region to change + * @size: size of memory region to change + * @option: dcache option to select */ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 1da2e92fe2..39717610d4 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -25,7 +25,8 @@ __weak void arm_init_domains(void) { } -void set_section_dcache(int section, enum dcache_option option) +static void set_section_phys(int section, phys_addr_t phys, + enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option) #endif /* Add the page offset */ - value |= ((u32)section << MMU_SECTION_SHIFT); + value |= phys; /* Add caching bits */ value |= option; @@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } +void set_section_dcache(int section, enum dcache_option option) +{ + set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option); +} + __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) { debug("%s: Warning: not implemented\n", __func__); } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) +void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, + size_t size, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, option); #endif - for (upto = start; upto < end; upto++) - set_section_dcache(upto, option); + for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE) + set_section_phys(upto, phys, option); /* * Make sure range is cache line aligned @@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, mmu_page_table_flush(startpt, stoppt); } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + mmu_set_region_dcache_behaviour_phys(start, start, size, option); +} + __weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index e6eb904e7f..b3287ce8bc 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae39852f..4ccaf69693 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -8,4 +8,12 @@ extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#include <addr_map.h> +#define phys_to_virt addrmap_phys_to_virt +#define virt_to_phys addrmap_virt_to_phys +#endif +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index cf4c5b245d..f2a5411623 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -146,6 +146,27 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL +#include <addr_map.h> +#include <asm/system.h> + +void init_addr_map(void) +{ + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + DCACHE_OFF); + + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */ + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0); + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */ + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1); +} +#endif + void enable_caches(void) { dcache_enable(); diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 67a00cf1cf..2454730e6d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -533,7 +533,7 @@ struct op_params pex_and_usb3_tx_config_params3[] = { struct op_params pex_by4_config_params[] = { /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0}, - /* Lane Alignement enable */ + /* Lane Alignment enable */ {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0}, /* Max PLL phy config */ {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000}, @@ -672,12 +672,29 @@ struct op_params usb2_power_up_params[] = { {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, /* Phy0 register 3 - TX Channel control 0 */ {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, - /* check PLLCAL_DONE is set and IMPCAL_DONE is set */ + /* Decrease the amplitude of the low speed eye to meet the spec */ + {0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + /* Change the High speed impedance threshold */ + {0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */ + {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + {0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + /* Check PLLCAL_DONE is set and IMPCAL_DONE is set */ {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000}, - /* check REG_SQCAL_DONE is set */ + /* Check REG_SQCAL_DONE is set */ {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, - /* check PLL_READY is set */ - {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000} + /* Check PLL_READY is set */ + {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, + /* Start calibrate of high seed impedance */ + {0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0}, + {0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0}, + /* De-assert the calibration signal */ + {0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0}, }; /* diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 0722e4a891..cbf0120adc 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -147,7 +147,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, /* Try bootm for legacy and FIT format image */ if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID) do_bootm(cmdtp, 0, 4, bootm_argv); - else if CONFIG_IS_ENABLED(CMD_BOOTZ) + else if (CONFIG_IS_ENABLED(CMD_BOOTZ)) do_bootz(cmdtp, 0, 4, bootm_argv); } diff --git a/arch/sandbox/include/asm/rtc.h b/arch/sandbox/include/asm/rtc.h index 1fbfea7999..5bb032f59f 100644 --- a/arch/sandbox/include/asm/rtc.h +++ b/arch/sandbox/include/asm/rtc.h @@ -21,6 +21,11 @@ enum { REG_RESET = 0x20, + REG_AUX0 = 0x30, + REG_AUX1, + REG_AUX2, + REG_AUX3, + REG_COUNT = 0x80, }; diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 11621256ae..3aa2a55676 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,6 +3,7 @@ # Copyright 2019 Google LLC obj-$(CONFIG_SPL_BUILD) += cpu_spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o obj-y += cpu_common.o @@ -11,7 +12,6 @@ obj-y += cpu.o obj-y += punit.o obj-y += fsp_bindings.o ifdef CONFIG_SPL_BUILD -obj-y += spl.o obj-y += fsp_m.o endif endif diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 435e50edad..d27324cb4e 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -363,6 +363,11 @@ static void setup_cpu_features(void) : : "i" (em_rst), "i" (mp_ne_set) : "eax"); } +void cpu_reinit_fpu(void) +{ + asm ("fninit\n"); +} + static void setup_identity(void) { /* identify CPU via cpuid and store the decoded info into gd->arch */ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 3e5d56d075..bd3f44014c 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -43,6 +43,14 @@ int x86_cpu_reinit_f(void); */ int x86_cpu_init_tpl(void); +/** + * cpu_reinit_fpu() - Reinit the FPU if something is wrong with it + * + * The FSP-M code can leave registers in use in the FPU. This functions reinits + * it so that the FPU can be used safely + */ +void cpu_reinit_fpu(void); + int cpu_init_f(void); void setup_gdt(struct global_data *id, u64 *gdt_addr); /* diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 6e23f3c95f..e8c1e07af1 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -117,6 +117,16 @@ err: return ret; } +static int fsp_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + + /* Set the maximum supported resolution */ + plat->size = 2560 * 1600 * 4; + + return 0; +} + static const struct udevice_id fsp_video_ids[] = { { .compatible = "fsp-fb" }, { } @@ -126,7 +136,9 @@ U_BOOT_DRIVER(fsp_video) = { .name = "fsp_video", .id = UCLASS_VIDEO, .of_match = fsp_video_ids, + .bind = fsp_video_bind, .probe = fsp_video_probe, + .flags = DM_FLAG_PRE_RELOC, }; static struct pci_device_id fsp_video_supported[] = { diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c index 1a758147b0..faf9c29aef 100644 --- a/arch/x86/lib/fsp2/fsp_meminit.c +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -85,6 +85,7 @@ int fsp_memory_init(bool s3wake, bool use_spi_flash) func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init); ret = func(&upd, &hob); bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M); + cpu_reinit_fpu(); if (ret) return log_msg_ret("SDRAM init fail\n", ret); |