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-rw-r--r--arch/arc/lib/libgcc2.c75
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig17
-rw-r--r--arch/arm/dts/armada-cp110-master.dtsi1
-rw-r--r--arch/arm/dts/armada-cp110-slave.dtsi1
-rw-r--r--arch/arm/include/asm/mach-imx/mxc_i2c.h6
-rw-r--r--arch/arm/mach-bcm283x/Kconfig67
-rw-r--r--arch/arm/mach-bcm283x/include/mach/mbox.h14
-rw-r--r--arch/arm/mach-bcm283x/include/mach/sdhci.h6
-rw-r--r--arch/arm/mach-bcm283x/include/mach/timer.h6
-rw-r--r--arch/arm/mach-bcm283x/include/mach/wdog.h6
-rw-r--r--arch/arm/mach-bcm283x/mbox.c6
-rw-r--r--arch/riscv/cpu/ax25/Kconfig1
-rw-r--r--arch/riscv/cpu/ax25/cache.c39
-rw-r--r--arch/riscv/cpu/start.S10
-rw-r--r--arch/riscv/dts/ae350_32.dts17
-rw-r--r--arch/riscv/dts/ae350_64.dts17
-rw-r--r--arch/riscv/lib/andes_plic.c36
17 files changed, 246 insertions, 79 deletions
diff --git a/arch/arc/lib/libgcc2.c b/arch/arc/lib/libgcc2.c
index b92a841a37..ab1dbe1c13 100644
--- a/arch/arc/lib/libgcc2.c
+++ b/arch/arc/lib/libgcc2.c
@@ -158,3 +158,78 @@ __umodsi3(long a, long b)
{
return udivmodsi4(a, b, 1);
}
+
+UDWtype
+__udivmoddi4(UDWtype n, UDWtype d, UDWtype *rp)
+{
+ UDWtype q = 0, r = n, y = d;
+ UWtype lz1, lz2, i, k;
+
+ /*
+ * Implements align divisor shift dividend method. This algorithm
+ * aligns the divisor under the dividend and then perform number of
+ * test-subtract iterations which shift the dividend left. Number of
+ * iterations is k + 1 where k is the number of bit positions the
+ * divisor must be shifted left to align it under the dividend.
+ * quotient bits can be saved in the rightmost positions of the
+ * dividend as it shifts left on each test-subtract iteration.
+ */
+
+ if (y <= r) {
+ lz1 = __builtin_clzll(d);
+ lz2 = __builtin_clzll(n);
+
+ k = lz1 - lz2;
+ y = (y << k);
+
+ /*
+ * Dividend can exceed 2 ^ (width - 1) - 1 but still be less
+ * than the aligned divisor. Normal iteration can drops the
+ * high order bit of the dividend. Therefore, first
+ * test-subtract iteration is a special case, saving its
+ * quotient bit in a separate location and not shifting
+ * the dividend.
+ */
+
+ if (r >= y) {
+ r = r - y;
+ q = (1ULL << k);
+ }
+
+ if (k > 0) {
+ y = y >> 1;
+
+ /*
+ * k additional iterations where k regular test
+ * subtract shift dividend iterations are done.
+ */
+ i = k;
+ do {
+ if (r >= y)
+ r = ((r - y) << 1) + 1;
+ else
+ r = (r << 1);
+ i = i - 1;
+ } while (i != 0);
+
+ /*
+ * First quotient bit is combined with the quotient
+ * bits resulting from the k regular iterations.
+ */
+ q = q + r;
+ r = r >> k;
+ q = q - (r << k);
+ }
+ }
+
+ if (rp)
+ *rp = r;
+
+ return q;
+}
+
+UDWtype
+__udivdi3(UDWtype n, UDWtype d)
+{
+ return __udivmoddi4(n, d, (UDWtype *)0);
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 42d31fdab0..54d03ae622 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -245,14 +245,6 @@ config FSL_LSCH3
config NXP_LSCH3_2
bool
-config FSL_MC_ENET
- bool "Management Complex network"
- depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
- default y
- select RESV_RAM
- help
- Enable Management Complex (MC) network
-
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
@@ -593,15 +585,6 @@ config SYS_FSL_HAS_RGMII
bool
depends on SYS_FSL_EC1 || SYS_FSL_EC2
-
-config SYS_MC_RSV_MEM_ALIGN
- hex "Management Complex reserved memory alignment"
- depends on RESV_RAM
- default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
- help
- Reserved memory needs to be aligned for MC to use. Default value
- is 512MB.
-
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
index 551d00d774..e4c17e9f4b 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -96,6 +96,7 @@
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
+ device-name = "cpm-mdio";
};
cpm_syscon0: system-controller@440000 {
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
index 2ea9004f1d..2fbd7b5514 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -96,6 +96,7 @@
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
+ device-name = "cps-mdio";
};
cps_syscon0: system-controller@440000 {
diff --git a/arch/arm/include/asm/mach-imx/mxc_i2c.h b/arch/arm/include/asm/mach-imx/mxc_i2c.h
index 8e1ea9af19..81fd981444 100644
--- a/arch/arm/include/asm/mach-imx/mxc_i2c.h
+++ b/arch/arm/include/asm/mach-imx/mxc_i2c.h
@@ -6,6 +6,9 @@
#define __ASM_ARCH_MXC_MXC_I2C_H__
#include <asm-generic/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
+#if CONFIG_IS_ENABLED(CLK)
+#include <clk.h>
+#endif
struct i2c_pin_ctrl {
iomux_v3_cfg_t i2c_mode;
@@ -47,6 +50,9 @@ struct mxc_i2c_bus {
ulong driver_data;
int speed;
struct i2c_pads_info *pads_info;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk per_clk;
+#endif
#ifndef CONFIG_DM_I2C
int (*idle_bus_fn)(void *p);
void *idle_bus_data;
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 3eb5a9a897..b08275f598 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -26,6 +26,23 @@ config BCM2837_64B
select BCM2837
select ARM64
+config BCM2711
+ bool "Broadcom BCM2711 SoC support"
+ depends on ARCH_BCM283X
+
+config BCM2711_32B
+ bool "Broadcom BCM2711 SoC 32-bit support"
+ depends on ARCH_BCM283X
+ select BCM2711
+ select ARMV7_LPAE
+ select CPU_V7A
+
+config BCM2711_64B
+ bool "Broadcom BCM2711 SoC 64-bit support"
+ depends on ARCH_BCM283X
+ select BCM2711
+ select ARM64
+
menu "Broadcom BCM283X family"
depends on ARCH_BCM283X
@@ -127,6 +144,50 @@ config TARGET_RPI_3
This option creates a build targeting the ARMv8/AArch64 ISA.
select BCM2837_64B
+config TARGET_RPI_4_32B
+ bool "Raspberry Pi 4 32-bit build"
+ help
+ Support for all BCM2711-based Raspberry Pi variants, such as
+ the RPi 4 model B, in AArch32 (32-bit) mode.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi 4. To enable the UART console, the following non-
+ default option must be present in config.txt: enable_uart=1. This is
+ required for U-Boot to operate correctly, even if you only care
+ about the HDMI/usbkbd console.
+
+ Due to hardware incompatibilities, this can't be used with
+ BCM283/5/6/7.
+
+ This option creates a build targeting the ARMv7/AArch32 ISA.
+ select BCM2711_32B
+
+config TARGET_RPI_4
+ bool "Raspberry Pi 4 64-bit build"
+ help
+ Support for all BCM2711-based Raspberry Pi variants, such as
+ the RPi 4 model B, in AArch64 (64-bit) mode.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi 4. To enable the UART console, the following non-
+ default option must be present in config.txt: enable_uart=1. This is
+ required for U-Boot to operate correctly, even if you only care
+ about the HDMI/usbkbd console.
+
+ Due to hardware incompatibilities, this can't be used with
+ BCM283/5/6/7.
+
+ Also, due to a bug in firmware, switching to 64bit mode doesn't
+ happen automatically based on the kernel's image filename. See
+ https://github.com/raspberrypi/firmware/issues/1193 for more details.
+ Until that is resolved, the configuration (config.txt) needs to
+ explicitly set: arm_64bit=1.
+
+ This option creates a build targeting the ARMv8/AArch64 ISA.
+ select BCM2711_64B
+
endchoice
config SYS_BOARD
@@ -141,4 +202,10 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "rpi"
+config BCM283x_BASE
+ hex
+ default "0x20000000" if BCM2835
+ default "0x3f000000" if BCM2836 || BCM2837
+ default "0xfe000000" if BCM2711
+
endmenu
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index e3a893e49c..0b6c2543d5 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -37,18 +37,17 @@
/* Raw mailbox HW */
-#ifndef CONFIG_BCM2835
-#define BCM2835_MBOX_PHYSADDR 0x3f00b880
-#else
-#define BCM2835_MBOX_PHYSADDR 0x2000b880
-#endif
+#define BCM2835_MBOX_PHYSADDR (CONFIG_BCM283x_BASE + 0x0000b880)
struct bcm2835_mbox_regs {
u32 read;
u32 rsvd0[5];
- u32 status;
- u32 config;
+ u32 mail0_status;
+ u32 mail0_config;
u32 write;
+ u32 rsvd1[5];
+ u32 mail1_status;
+ u32 mail1_config;
};
#define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
@@ -234,6 +233,7 @@ struct bcm2835_mbox_tag_set_power_state {
#define BCM2835_MBOX_CLOCK_ID_SDRAM 8
#define BCM2835_MBOX_CLOCK_ID_PIXEL 9
#define BCM2835_MBOX_CLOCK_ID_PWM 10
+#define BCM2835_MBOX_CLOCK_ID_EMMC2 12
struct bcm2835_mbox_tag_get_clock_rate {
struct bcm2835_mbox_tag_hdr tag_hdr;
diff --git a/arch/arm/mach-bcm283x/include/mach/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h
index 5cb6ec3340..b443c379d8 100644
--- a/arch/arm/mach-bcm283x/include/mach/sdhci.h
+++ b/arch/arm/mach-bcm283x/include/mach/sdhci.h
@@ -6,11 +6,7 @@
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
-#ifndef CONFIG_BCM2835
-#define BCM2835_SDHCI_BASE 0x3f300000
-#else
-#define BCM2835_SDHCI_BASE 0x20300000
-#endif
+#define BCM2835_SDHCI_BASE (CONFIG_BCM283x_BASE + 0x00300000)
int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
diff --git a/arch/arm/mach-bcm283x/include/mach/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h
index 56b0c356bb..014355e759 100644
--- a/arch/arm/mach-bcm283x/include/mach/timer.h
+++ b/arch/arm/mach-bcm283x/include/mach/timer.h
@@ -6,11 +6,7 @@
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
-#ifndef CONFIG_BCM2835
-#define BCM2835_TIMER_PHYSADDR 0x3f003000
-#else
-#define BCM2835_TIMER_PHYSADDR 0x20003000
-#endif
+#define BCM2835_TIMER_PHYSADDR (CONFIG_BCM283x_BASE + 0x00003000)
#define BCM2835_TIMER_CS_M3 (1 << 3)
#define BCM2835_TIMER_CS_M2 (1 << 2)
diff --git a/arch/arm/mach-bcm283x/include/mach/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h
index 99c88e5df7..8292b3cf1f 100644
--- a/arch/arm/mach-bcm283x/include/mach/wdog.h
+++ b/arch/arm/mach-bcm283x/include/mach/wdog.h
@@ -6,11 +6,7 @@
#ifndef _BCM2835_WDOG_H
#define _BCM2835_WDOG_H
-#ifndef CONFIG_BCM2835
-#define BCM2835_WDOG_PHYSADDR 0x3f100000
-#else
-#define BCM2835_WDOG_PHYSADDR 0x20100000
-#endif
+#define BCM2835_WDOG_PHYSADDR (CONFIG_BCM283x_BASE + 0x00100000)
struct bcm2835_wdog_regs {
u32 unknown0[7];
diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c
index 1642ebd103..3c67f68c17 100644
--- a/arch/arm/mach-bcm283x/mbox.c
+++ b/arch/arm/mach-bcm283x/mbox.c
@@ -27,7 +27,7 @@ int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
/* Drain any stale responses */
for (;;) {
- val = readl(&regs->status);
+ val = readl(&regs->mail0_status);
if (val & BCM2835_MBOX_STATUS_RD_EMPTY)
break;
if (get_timer(0) >= endtime) {
@@ -40,7 +40,7 @@ int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
/* Wait for space to send */
for (;;) {
- val = readl(&regs->status);
+ val = readl(&regs->mail1_status);
if (!(val & BCM2835_MBOX_STATUS_WR_FULL))
break;
if (get_timer(0) >= endtime) {
@@ -58,7 +58,7 @@ int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
/* Wait for the response */
for (;;) {
- val = readl(&regs->status);
+ val = readl(&regs->mail0_status);
if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY))
break;
if (get_timer(0) >= endtime) {
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index f4b59cb71d..d411a79c21 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -6,6 +6,7 @@ config RISCV_NDS
imply RISCV_TIMER
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply V5L2_CACHE
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index cd95058d9d..41de30cc02 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -5,17 +5,24 @@
*/
#include <common.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <cache.h>
+#include <asm/csr.h>
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL 6
+#endif
void flush_dcache_all(void)
{
- /*
- * Andes' AX25 does not have a coherence agent. U-Boot must use data
- * cache flush and invalidate functions to keep data in the system
- * coherent.
- * The implementation of the fence instruction in the AX25 flushes the
- * data cache and is used for this purpose.
- */
- asm volatile ("fence" ::: "memory");
+#ifdef CONFIG_RISCV_NDS_CACHE
+ csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
}
void flush_dcache_range(unsigned long start, unsigned long end)
@@ -59,11 +66,18 @@ void dcache_enable(void)
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
+ struct udevice *dev = NULL;
+
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+ uclass_find_first_device(UCLASS_CACHE, &dev);
+
+ if (dev)
+ cache_enable(dev);
#endif
#endif
}
@@ -72,12 +86,19 @@ void dcache_disable(void)
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
+ struct udevice *dev = NULL;
+
+ csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
- "fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+ uclass_find_first_device(UCLASS_CACHE, &dev);
+
+ if (dev)
+ cache_disable(dev);
#endif
#endif
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index b15209d623..0a2ce6d691 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -269,7 +269,7 @@ fix_rela_dyn:
/*
* skip first reserved entry: address, type, addend
*/
- bne t1, t2, 7f
+ j 10f
6:
LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
@@ -280,9 +280,7 @@ fix_rela_dyn:
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
-7:
- addi t1, t1, (REGBYTES*3)
- ble t1, t2, 6b
+ j 10f
8:
la t4, __dyn_sym_start
@@ -299,13 +297,15 @@ fix_rela_dyn:
li t5, SYM_SIZE
mul t0, t0, t5
add s5, t4, t0
+ LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */
LREG t5, REGBYTES(s5)
+ add t5, t5, t0
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
10:
addi t1, t1, (REGBYTES*3)
- ble t1, t2, 9b
+ ble t1, t2, 6b
/*
* trap update
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13f16..97b7cee983 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+ };
- L2: l2-cache@e0500000 {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x40000>;
- reg = <0x0 0xe0500000 0x0 0x40000>;
- };
+ L2: l2-cache@e0500000 {
+ compatible = "v5l2cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0xe0500000 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is <XRAMOCTL XRAMICTL> */
+ andes,tag-ram-ctl = <0 0>;
+ andes,data-ram-ctl = <0 0>;
};
memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a8e4..d8f00f8d3a 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+ };
- L2: l2-cache@e0500000 {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x40000>;
- reg = <0x0 0xe0500000 0x0 0x40000>;
- };
+ L2: l2-cache@e0500000 {
+ compatible = "v5l2cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0x0 0xe0500000 0x0 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is <XRAMOCTL XRAMICTL> */
+ andes,tag-ram-ctl = <0 0>;
+ andes,data-ram-ctl = <0 0>;
};
memory@0 {
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 2ffe49ac90..28568e4e2b 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -44,15 +44,12 @@ static int init_plic(void);
} \
} while (0)
-static int enable_ipi(int harts)
+static int enable_ipi(int hart)
{
- int i;
- int en = ENABLE_HART_IPI;
+ int en;
- for (i = 0; i < harts; i++) {
- en = en >> i;
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
- }
+ en = ENABLE_HART_IPI >> hart;
+ writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
return 0;
}
@@ -60,18 +57,35 @@ static int enable_ipi(int harts)
static int init_plic(void)
{
struct udevice *dev;
+ ofnode node;
int ret;
+ u32 reg;
ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret)
return ret;
if (ret == 0 && dev) {
- ret = cpu_get_count(dev);
- if (ret < 0)
- return ret;
+ ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+ const char *device_type;
+
+ device_type = ofnode_read_string(node, "device_type");
+ if (!device_type)
+ continue;
+
+ if (strcmp(device_type, "cpu"))
+ continue;
+
+ /* skip if hart is marked as not available */
+ if (!ofnode_is_available(node))
+ continue;
+
+ /* read hart ID of CPU */
+ ret = ofnode_read_u32(node, "reg", &reg);
+ if (ret == 0)
+ enable_ipi(reg);
+ }
- enable_ipi(ret);
return 0;
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-28 12:22:34 +0000