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-rw-r--r--arch/arm/dts/sama5d3xcm.dtsi32
-rw-r--r--arch/arm/dts/sama5d3xcm_cmp.dtsi32
-rw-r--r--arch/arm/dts/socfpga_arria5_socdk.dts4
-rw-r--r--arch/arm/dts/socfpga_cyclone5_is1.dts4
-rw-r--r--arch/arm/dts/socfpga_cyclone5_socdk.dts4
-rw-r--r--arch/arm/dts/socfpga_cyclone5_sockit.dts4
-rw-r--r--arch/arm/dts/socfpga_cyclone5_vining_fpga.dts4
-rw-r--r--arch/arm/include/asm/arch-meson/usb.h12
-rw-r--r--arch/arm/mach-meson/board-g12a.c126
-rw-r--r--arch/riscv/Kconfig7
-rw-r--r--arch/riscv/cpu/cpu.c4
-rw-r--r--arch/riscv/cpu/start.S8
-rw-r--r--arch/riscv/include/asm/global_data.h2
-rw-r--r--arch/riscv/lib/Makefile1
-rw-r--r--arch/riscv/lib/asm-offsets.c2
-rw-r--r--arch/riscv/lib/image.c55
-rw-r--r--arch/riscv/lib/smp.c2
17 files changed, 261 insertions, 42 deletions
diff --git a/arch/arm/dts/sama5d3xcm.dtsi b/arch/arm/dts/sama5d3xcm.dtsi
index 2cf9c3611d..d123057f30 100644
--- a/arch/arm/dts/sama5d3xcm.dtsi
+++ b/arch/arm/dts/sama5d3xcm.dtsi
@@ -44,28 +44,28 @@
reg = <0x1>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- txen-skew-ps = <800>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <400>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <400>;
- rxd1-skew-ps = <400>;
- rxd2-skew-ps = <400>;
- rxd3-skew-ps = <400>;
+ txen-skew-ps = <480>;
+ txc-skew-ps = <1800>;
+ rxdv-skew-ps = <240>;
+ rxc-skew-ps = <1800>;
+ rxd0-skew-ps = <240>;
+ rxd1-skew-ps = <240>;
+ rxd2-skew-ps = <240>;
+ rxd3-skew-ps = <240>;
};
ethernet-phy@7 {
reg = <0x7>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- txen-skew-ps = <800>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <400>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <400>;
- rxd1-skew-ps = <400>;
- rxd2-skew-ps = <400>;
- rxd3-skew-ps = <400>;
+ txen-skew-ps = <480>;
+ txc-skew-ps = <1800>;
+ rxdv-skew-ps = <240>;
+ rxc-skew-ps = <1800>;
+ rxd0-skew-ps = <240>;
+ rxd1-skew-ps = <240>;
+ rxd2-skew-ps = <240>;
+ rxd3-skew-ps = <240>;
};
};
};
diff --git a/arch/arm/dts/sama5d3xcm_cmp.dtsi b/arch/arm/dts/sama5d3xcm_cmp.dtsi
index 77638c3cbe..332b057e0a 100644
--- a/arch/arm/dts/sama5d3xcm_cmp.dtsi
+++ b/arch/arm/dts/sama5d3xcm_cmp.dtsi
@@ -43,28 +43,28 @@
reg = <0x1>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- txen-skew-ps = <800>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <400>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <400>;
- rxd1-skew-ps = <400>;
- rxd2-skew-ps = <400>;
- rxd3-skew-ps = <400>;
+ txen-skew-ps = <480>;
+ txc-skew-ps = <1800>;
+ rxdv-skew-ps = <240>;
+ rxc-skew-ps = <1800>;
+ rxd0-skew-ps = <240>;
+ rxd1-skew-ps = <240>;
+ rxd2-skew-ps = <240>;
+ rxd3-skew-ps = <240>;
};
ethernet-phy@7 {
reg = <0x7>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- txen-skew-ps = <800>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <400>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <400>;
- rxd1-skew-ps = <400>;
- rxd2-skew-ps = <400>;
- rxd3-skew-ps = <400>;
+ txen-skew-ps = <480>;
+ txc-skew-ps = <1800>;
+ rxdv-skew-ps = <240>;
+ rxc-skew-ps = <1800>;
+ rxd0-skew-ps = <240>;
+ rxd1-skew-ps = <240>;
+ rxd2-skew-ps = <240>;
+ rxd3-skew-ps = <240>;
};
};
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 90e676e701..fa972e287f 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -67,9 +67,9 @@
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 2d31412923..a769498791 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -43,9 +43,9 @@
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio1 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 6f138b2b26..95c7619b8d 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -71,9 +71,9 @@
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio0 {
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index c155ff02eb..90669cde45 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -128,9 +128,9 @@
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio0 { /* GPIO 0..29 */
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
index 355b3dbf43..ac57f41cb5 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
@@ -85,9 +85,9 @@
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
};
};
diff --git a/arch/arm/include/asm/arch-meson/usb.h b/arch/arm/include/asm/arch-meson/usb.h
new file mode 100644
index 0000000000..b794b5ce77
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/usb.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_USB_H__
+#define __MESON_USB_H__
+
+int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode);
+
+#endif /* __MESON_USB_H__ */
diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c
index fc3764b960..1652970fbd 100644
--- a/arch/arm/mach-meson/board-g12a.c
+++ b/arch/arm/mach-meson/board-g12a.c
@@ -12,7 +12,12 @@
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
+#include <usb.h>
+#include <linux/usb/otg.h>
+#include <asm/arch/usb.h>
+#include <usb/dwc2_udc.h>
#include <phy.h>
+#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -148,3 +153,124 @@ void meson_eth_init(phy_interface_t mode, unsigned int flags)
/* Enable power gate */
clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
}
+
+#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
+ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
+static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ struct fdtdec_phandle_args args;
+ const void *blob = gd->fdt_blob;
+ int node, dwc2_node;
+ struct udevice *dev, *clk_dev;
+ struct clk clk;
+ int ret;
+
+ /* find the usb glue node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "amlogic,meson-g12a-usb-ctrl");
+ if (node < 0) {
+ debug("Not found usb-control node\n");
+ return -ENODEV;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, node)) {
+ debug("usb is disabled in the device tree\n");
+ return -ENODEV;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
+ if (ret) {
+ debug("Not found usb-control device\n");
+ return ret;
+ }
+
+ /* find the dwc2 node */
+ dwc2_node = fdt_node_offset_by_compatible(blob, node,
+ "amlogic,meson-g12a-usb");
+ if (dwc2_node < 0) {
+ debug("Not found dwc2 node\n");
+ return -ENODEV;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
+ debug("dwc2 is disabled in the device tree\n");
+ return -ENODEV;
+ }
+
+ meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
+ if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
+ debug("usbotg: can't get base address\n");
+ return -ENODATA;
+ }
+
+ /* Enable clock */
+ ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
+ "#clock-cells", 0, 0, &args);
+ if (ret) {
+ debug("usbotg has no clocks defined in the device tree\n");
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
+ if (ret)
+ return ret;
+
+ if (args.args_count != 1) {
+ debug("Can't find clock ID in the device tree\n");
+ return -ENODATA;
+ }
+
+ clk.dev = clk_dev;
+ clk.id = args.args[0];
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ debug("Failed to enable usbotg clock\n");
+ return ret;
+ }
+
+ meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-rx-fifo-size", 0);
+ meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-np-tx-fifo-size", 0);
+ meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-tx-fifo-size", 0);
+
+ /* Switch to peripheral mode */
+ ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
+ if (ret)
+ return ret;
+
+ return dwc2_udc_probe(&meson_g12a_dwc2_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ int node;
+ int ret;
+
+ /* find the usb glue node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "amlogic,meson-g12a-usb-ctrl");
+ if (node < 0)
+ return -ENODEV;
+
+ if (!fdtdec_get_is_enabled(blob, node))
+ return -ENODEV;
+
+ ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
+ if (ret)
+ return ret;
+
+ /* Switch to OTG mode */
+ ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b765..362f3cdc65 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,13 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
+config XIP
+ bool "XIP mode"
+ help
+ XIP (eXecute In Place) is a method for executing code directly
+ from a NOR flash memory without copying the code to ram.
+ Say yes here if U-Boot boots from flash directly.
+
config STACK_SIZE_SHIFT
int
default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a4c3..e9a8b437ed 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -15,7 +15,10 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
+#ifdef CONFIG_OF_PRIOR_STAGE
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
+#ifndef CONFIG_XIP
u32 hart_lottery __attribute__((section(".data"))) = 0;
/*
@@ -23,6 +26,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
* finished initialization of global data.
*/
u32 available_harts_lock = 1;
+#endif
static inline bool supports_extension(char ext)
{
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fbd6b..60ac8c621e 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
mv sp, a0
#endif
+#ifndef CONFIG_XIP
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
@@ -106,15 +107,21 @@ call_board_init_f_0:
li s2, 1
amoswap.w s2, t1, 0(t0)
bnez s2, wait_for_gd_init
+#else
+ bnez tp, secondary_hart_loop
+#endif
+#ifdef CONFIG_OF_PRIOR_STAGE
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
+#endif
jal board_init_f_init_reserve
/* save the boot hart id to global_data */
SREG tp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP
la t0, available_harts_lock
fence rw, w
amoswap.w zero, zero, 0(t0)
@@ -141,6 +148,7 @@ wait_for_gd_init:
* secondary_hart_loop.
*/
bnez s2, secondary_hart_loop
+#endif
/* Enable cache */
jal icache_enable
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index dffcd45bf0..b74bd7e738 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
#ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
+#ifndef CONFIG_XIP
ulong available_harts;
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 1c332db436..6ae6ebbeaf 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -7,6 +7,7 @@
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402bd1..4fa4fd3714 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
return 0;
}
diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
new file mode 100644
index 0000000000..d063beb7df
--- /dev/null
+++ b/arch/riscv/lib/image.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ * Authors:
+ * Atish Patra <atish.patra@wdc.com>
+ * Based on arm/lib/image.c
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <errno.h>
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ASCII version of "RISCV" defined in Linux kernel */
+#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952
+
+struct linux_image_h {
+ uint32_t code0; /* Executable code */
+ uint32_t code1; /* Executable code */
+ uint64_t text_offset; /* Image load offset */
+ uint64_t image_size; /* Effective Image size */
+ uint64_t res1; /* reserved */
+ uint64_t res2; /* reserved */
+ uint64_t res3; /* reserved */
+ uint64_t magic; /* Magic number */
+ uint32_t res4; /* reserved */
+ uint32_t res5; /* reserved */
+};
+
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
+ bool force_reloc)
+{
+ struct linux_image_h *lhdr;
+
+ lhdr = (struct linux_image_h *)map_sysmem(image, 0);
+
+ if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
+ puts("Bad Linux RISCV Image magic!\n");
+ return -EINVAL;
+ }
+
+ if (lhdr->image_size == 0) {
+ puts("Image lacks image_size field, error!\n");
+ return -EINVAL;
+ }
+ *size = lhdr->image_size;
+ *relocated_addr = gd->ram_base + lhdr->text_offset;
+
+ unmap_sysmem(lhdr);
+
+ return 0;
+}
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292ccd2..cc66f15567 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
continue;
}
+#ifndef CONFIG_XIP
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
+#endif
gd->arch.ipi[reg].addr = ipi->addr;
gd->arch.ipi[reg].arg0 = ipi->arg0;
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-24 01:23:11 +0000