diff options
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/acpi/vbnv_layout.h | 38 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/cpu.h | 14 | ||||
| -rw-r--r-- | arch/x86/include/asm/cpu_common.h | 9 | ||||
| -rw-r--r-- | arch/x86/include/asm/intel_gnvs.h | 54 | ||||
| -rw-r--r-- | arch/x86/include/asm/interrupt.h | 17 | ||||
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 20 | ||||
| -rw-r--r-- | arch/x86/include/asm/tables.h | 4 |
7 files changed, 150 insertions, 6 deletions
diff --git a/arch/x86/include/asm/acpi/vbnv_layout.h b/arch/x86/include/asm/acpi/vbnv_layout.h new file mode 100644 index 0000000000..89065524d3 --- /dev/null +++ b/arch/x86/include/asm/acpi/vbnv_layout.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020 Google LLC + */ + +#ifndef __ASM_ACPI_VBNV_LAYOUT_H__ +#define __ASM_ACPI_VBNV_LAYOUT_H__ + +#define VBOOT_VBNV_BLOCK_SIZE 16 /* Size of NV storage block in bytes */ + +/* Constants for NV storage, for use with ACPI */ +#define HEADER_OFFSET 0 +#define HEADER_MASK 0xc0 +#define HEADER_SIGNATURE 0x40 +#define HEADER_FIRMWARE_SETTINGS_RESET 0x20 +#define HEADER_KERNEL_SETTINGS_RESET 0x10 + +#define BOOT_OFFSET 1 +#define BOOT_DEBUG_RESET_MODE 0x80 +#define BOOT_DISABLE_DEV_REQUEST 0x40 +#define BOOT_DISPLAY_REQUEST 0x20 +#define BOOT_TRY_B_COUNT_MASK 0x0f + +#define RECOVERY_OFFSET 2 +#define LOCALIZATION_OFFSET 3 + +#define DEV_FLAGS_OFFSET 4 +#define DEV_BOOT_USB_MASK 0x01 +#define DEV_BOOT_SIGNED_ONLY_MASK 0x02 +#define DEV_ENABLE_UDC 0x40 + +#define MISC_FLAGS_OFFSET 8 +#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 + +#define KERNEL_FIELD_OFFSET 11 +#define CRC_OFFSET 15 + +#endif /* __ASM_ACPI_VBNV_LAYOUT_H__ */ diff --git a/arch/x86/include/asm/arch-apollolake/cpu.h b/arch/x86/include/asm/arch-apollolake/cpu.h index 5e906c5e7d..67d48c6109 100644 --- a/arch/x86/include/asm/arch-apollolake/cpu.h +++ b/arch/x86/include/asm/arch-apollolake/cpu.h @@ -15,6 +15,20 @@ #ifndef __ASSEMBLY__ /* Flush L1D to L2 */ void cpu_flush_l1d_to_l2(void); + +/** + * Enable emulation of the PM timer + * + * Some legacy OSes cannot tolerate the ACPI timer stoping during idle states, + * and this results in higher power consumption. ACPI timer emulation allows + * disabling of the ACPI Timer (PM1_TMR) to have no impact on the system, with + * the exception that TMR_STS will not be set on an overflow condition. All + * aligned 32-bit reads from the ACPI Timer port are valid and will behave as if + * the ACPI timer remains enabled. + * + * @pmc: PMC device + */ +void enable_pm_timer_emulation(const struct udevice *pmc); #endif #endif /* _ASM_ARCH_CPU_H */ diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index 48f56c2aad..2a5779a8e1 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -184,4 +184,13 @@ int cpu_get_max_turbo_ratio(void); */ int cpu_get_cores_per_package(void); +/** + * cpu_mca_configure() - Set up machine-check exceptions ready for use + * + * These allow the SoC to report errors while running. See here for details: + * + * https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/machine-check-exceptions-debug-paper.pdf + */ +void cpu_mca_configure(void); + #endif diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h index c1e9d65779..7f9f101371 100644 --- a/arch/x86/include/asm/intel_gnvs.h +++ b/arch/x86/include/asm/intel_gnvs.h @@ -9,6 +9,55 @@ #ifndef _INTEL_GNVS_H_ #define _INTEL_GNVS_H_ +/* + * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset + * 0x100 - 0x1000. When defining acpi_global_nvs, use check_member + * to ensure that it is properly aligned: + * + * check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + */ +#define GNVS_CHROMEOS_ACPI_OFFSET 0x100 + +enum { + CHSW_RECOVERY_X86 = BIT(1), + CHSW_RECOVERY_EC = BIT(2), + CHSW_DEVELOPER_SWITCH = BIT(5), + CHSW_FIRMWARE_WP = BIT(9), +}; + +enum { + FIRMWARE_TYPE_AUTO_DETECT = -1, + FIRMWARE_TYPE_RECOVERY = 0, + FIRMWARE_TYPE_NORMAL = 1, + FIRMWARE_TYPE_DEVELOPER = 2, + FIRMWARE_TYPE_NETBOOT = 3, + FIRMWARE_TYPE_LEGACY = 4, +}; + +struct __packed chromeos_acpi_gnvs { + /* ChromeOS-specific */ + u32 boot_reason; /* 00 boot reason */ + u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */ + u32 activeec_fw; /* 08 (0=RO, 1=RW) */ + u16 switches; /* 0c CHSW */ + u8 vbt4[256]; /* 0e HWID */ + u8 vbt5[64]; /* 10e FWID */ + u8 vbt6[64]; /* 14e FRID - 275 */ + u32 main_fw_type; /* 18e (2 = developer mode) */ + u32 vbt8; /* 192 recovery reason */ + u32 vbt9; /* 196 fmap base address */ + u8 vdat[3072]; /* 19a VDAT space filled by verified boot */ + u32 vbt10; /* d9a smbios bios version */ + u32 mehh[8]; /* d9e management engine hash */ + u32 ramoops_base; /* dbe ramoops base address */ + u32 ramoops_len; /* dc2 ramoops length */ + u32 vpd_ro_base; /* dc6 pointer to RO_VPD */ + u32 vpd_ro_size; /* dca size of RO_VPD */ + u32 vpd_rw_base; /* dce pointer to RW_VPD */ + u32 vpd_rw_size; /* dd2 size of RW_VPD */ + u8 pad[298]; /* dd6-eff */ +}; + struct __packed acpi_global_nvs { /* Miscellaneous */ u8 pcnt; /* 0x00 - Processor Count */ @@ -31,14 +80,11 @@ struct __packed acpi_global_nvs { u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ #ifdef CONFIG_CHROMEOS /* ChromeOS-specific (0x100 - 0xfff) */ - struct chromeos_acpi chromeos; + struct chromeos_acpi_gnvs chromeos; #else u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ #endif }; - -#ifdef CONFIG_CHROMEOS check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif #endif /* _INTEL_GNVS_H_ */ diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index fdeb857113..e23fb2c8e7 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -38,6 +38,16 @@ enum x86_exception { EXC_VE }; +/** + * struct idt_ptr - Holds the IDT (Interrupt Descriptor Table) + * + * @size: Size of IDT in bytes + */ +struct idt_ptr { + unsigned short size; + unsigned long address; +} __packed; + /* arch/x86/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); @@ -61,4 +71,11 @@ void configure_irq_trigger(int int_num, bool is_level_triggered); void *x86_get_idt(void); +/** + * interrupt_read_idt() - Read the IDT + * + * @ptr: Place to put IDT contents + */ +void interrupt_read_idt(struct idt_ptr *ptr); + #endif diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 94e6b18e21..c49b4225ac 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -68,7 +68,18 @@ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 -#define SINGLE_PCTL (1 << 11) +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK BIT(1) +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK BIT(10) +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK BIT(15) +#define SINGLE_PCTL BIT(11) + +/* ACPI PMIO Offset to C-state register */ +#define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 @@ -83,6 +94,10 @@ #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_VALUE 0x13 +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) + #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 #define MSR_IA32_SYSENTER_EIP 0x00000176 @@ -453,6 +468,9 @@ #define MSR_AMD_PERF_CTL 0xc0010062 #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 +/* CST Range (R/W) IO port block size */ +#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 + #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 #define MSR_IA32_MPERF 0x000000e7 #define MSR_IA32_APERF 0x000000e8 diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index f7c72ed3db..bf66e79018 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -49,8 +49,10 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad); * This writes x86 configuration tables, including PIRQ routing table, * Multi-Processor table and ACPI table. Whether a specific type of * configuration table is written is controlled by a Kconfig option. + * + * @return 0 if OK, -ENOSPC if table too large */ -void write_tables(void); +int write_tables(void); /** * write_pirq_routing_table() - Write PIRQ routing table |