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-rw-r--r--arch/x86/dts/chromebook_coral.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index 965d9f387d..a17a9c2800 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -117,6 +117,7 @@
reg = <0x00000000 0 0 0 0>;
compatible = "intel,apl-hostbridge";
pciex-region-size = <0x10000000>;
+ fspm,training-delay = <21>;
/*
* Parameters used by the FSP-S binary blob. This is
* really unfortunate since these parameters mostly