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-rw-r--r--arch/riscv/Kconfig8
-rw-r--r--arch/riscv/cpu/fu540/dram.c2
-rw-r--r--arch/riscv/cpu/fu740/dram.c2
-rw-r--r--arch/riscv/cpu/generic/dram.c2
-rw-r--r--arch/riscv/cpu/jh7110/Kconfig2
-rw-r--r--arch/riscv/cpu/jh7110/dram.c2
-rw-r--r--arch/riscv/cpu/jh7110/spl.c25
-rw-r--r--arch/riscv/cpu/start.S12
-rw-r--r--arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi11
-rw-r--r--arch/riscv/dts/jh7110.dtsi74
-rw-r--r--arch/riscv/include/asm/acpi_table.h11
-rw-r--r--arch/riscv/include/asm/sbi.h2
12 files changed, 124 insertions, 29 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 867cbcbe74..6771d8d919 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
+config SPL_ZERO_MEM_BEFORE_USE
+ bool "Zero memory before use"
+ depends on SPL
+ default n
+ help
+ Zero stack/GD/malloc area in SPL before using them, this is needed for
+ Sifive core devices that uses L2 cache to store SPL.
+
# board-specific options below
source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
index 44e11bd56c..94d8018407 100644
--- a/arch/riscv/cpu/fu540/dram.c
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -21,7 +21,7 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c
index d6d4a41d25..8657fcd165 100644
--- a/arch/riscv/cpu/fu740/dram.c
+++ b/arch/riscv/cpu/fu740/dram.c
@@ -20,7 +20,7 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_64BIT
/*
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 44e11bd56c..94d8018407 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -21,7 +21,7 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d9581165b..8469ee7de5 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -13,6 +13,8 @@ config STARFIVE_JH7110
select SUPPORT_SPL
select SPL_RAM if SPL
select SPL_STARFIVE_DDR
+ select SYS_CACHE_SHIFT_6
+ select SPL_ZERO_MEM_BEFORE_USE
select PINCTRL_STARFIVE_JH7110
imply MMC
imply MMC_BROKEN_CD
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
index 2ad3f2044a..1a9fa46d14 100644
--- a/arch/riscv/cpu/jh7110/dram.c
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -21,7 +21,7 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 72adcefa0e..4047b10efe 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -13,7 +13,6 @@
#include <init.h>
#define CSR_U74_FEATURE_DISABLE 0x7c1
-#define L2_LIM_MEM_END 0x81FFFFFUL
DECLARE_GLOBAL_DATA_PTR;
@@ -59,9 +58,6 @@ int spl_soc_init(void)
void harts_early_init(void)
{
- ulong *ptr;
- u8 *tmp;
- ulong len, remain;
/*
* Feature Disable CSR
*
@@ -70,25 +66,4 @@ void harts_early_init(void)
*/
if (CONFIG_IS_ENABLED(RISCV_MMODE))
csr_write(CSR_U74_FEATURE_DISABLE, 0);
-
- /* clear L2 LIM memory
- * set __bss_end to 0x81FFFFF region to zero
- * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
- * If it is not cleared, the ECC part is invalid, and an ECC error
- * will be reported when reading data.
- */
- ptr = (ulong *)&__bss_end;
- len = L2_LIM_MEM_END - (ulong)&__bss_end;
- remain = len % sizeof(ulong);
- len /= sizeof(ulong);
-
- while (len--)
- *ptr++ = 0;
-
- /* clear the remain bytes */
- if (remain) {
- tmp = (u8 *)ptr;
- while (remain--)
- *tmp++ = 0;
- }
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 59d58a5a57..30cf674370 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,6 +111,18 @@ call_board_init_f:
* It's essential before any function call, otherwise, we get data-race.
*/
+/* clear stack if necessary */
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+clear_stack:
+ li t1, 1
+ slli t1, t1, CONFIG_STACK_SIZE_SHIFT
+ sub t1, sp, t1
+clear_stack_loop:
+ SREG zero, 0(t1) /* t1 is always 16 byte aligned */
+ addi t1, t1, REGBYTES
+ blt t1, sp, clear_stack_loop
+#endif
+
call_board_init_f_0:
/* find top of reserve space */
#if CONFIG_IS_ENABLED(SMP)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index b90e7f8995..e40f57a150 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
#include "jh7110.dtsi"
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
serial0 = &uart0;
@@ -308,6 +309,16 @@
};
};
+&pcie0 {
+ reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie1 {
+ reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 825fbb7198..081b833331 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -648,5 +648,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ pcie0: pcie@2b000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x0 0x2b000000 0x0 0x1000000
+ 0x9 0x40000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ interrupts = <56>;
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ msi-parent = <&plic>;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+ clock-names = "noc", "tl", "axi", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE0_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+ };
+
+ pcie1: pcie@2c000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x0 0x2c000000 0x0 0x1000000
+ 0x9 0xc0000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ interrupts = <57>;
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ msi-parent = <&plic>;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+ clock-names = "noc", "tl", "axi", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE1_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+ };
};
};
diff --git a/arch/riscv/include/asm/acpi_table.h b/arch/riscv/include/asm/acpi_table.h
new file mode 100644
index 0000000000..cd851998b2
--- /dev/null
+++ b/arch/riscv/include/asm/acpi_table.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+/*
+ * This file is needed by some drivers.
+ * We will fill it when adding ACPI support for RISC-V.
+ */
+
+#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 769369997d..009a26885c 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -31,6 +31,8 @@ enum sbi_ext_id {
SBI_EXT_DBCN = 0x4442434E,
SBI_EXT_SUSP = 0x53555350,
SBI_EXT_CPPC = 0x43505043,
+ SBI_EXT_NACL = 0x4E41434C,
+ SBI_EXT_STA = 0x535441,
};
enum sbi_ext_base_fid {
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 09:08:35 +0000