diff options
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 36512a8995..ae8ff7b765 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -109,6 +109,24 @@ config SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config ANDES_PLIC + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The Andes PLIC block holds memory-mapped claim and pending registers + associated with software interrupt. + +config ANDES_PLMT + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The Andes PLMT block holds memory-mapped mtime register + associated with timer tick. + config RISCV_RDTIME bool default y if RISCV_SMODE @@ -120,4 +138,32 @@ config RISCV_RDTIME config SYS_MALLOC_F_LEN default 0x1000 +config SMP + bool "Symmetric Multi-Processing" + help + This enables support for systems with more than one CPU. If + you say N here, U-Boot will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor + machine. If you say Y here, U-Boot will run on many, but not + all, single processor machines. + +config NR_CPUS + int "Maximum number of CPUs (2-32)" + range 2 32 + depends on SMP + default 8 + help + On multiprocessor machines, U-Boot sets up a stack for each CPU. + Stack memory is pre-allocated. U-Boot must therefore know the + maximum number of CPUs that may be present. + +config SBI_IPI + bool + default y if RISCV_SMODE + depends on SMP + +config STACK_SIZE_SHIFT + int + default 13 + endmenu |