diff options
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 30 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 1 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c | 67 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 33 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/arch-mpc85xx/gpio.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 10 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 10 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/io.h | 15 |
11 files changed, 25 insertions, 149 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 870ab800e8..124c22f58a 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -51,23 +51,22 @@ config TARGET_P5040DS config TARGET_MPC8541CDS bool "Support MPC8541CDS" select ARCH_MPC8541 + select FSL_VIA config TARGET_MPC8548CDS bool "Support MPC8548CDS" select ARCH_MPC8548 + select FSL_VIA config TARGET_MPC8555CDS bool "Support MPC8555CDS" select ARCH_MPC8555 + select FSL_VIA config TARGET_MPC8568MDS bool "Support MPC8568MDS" select ARCH_MPC8568 -config TARGET_MPC8569MDS - bool "Support MPC8569MDS" - select ARCH_MPC8569 - config TARGET_P1010RDB_PA bool "Support P1010RDB_PA" select ARCH_P1010 @@ -473,19 +472,6 @@ config ARCH_MPC8568 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 -config ARCH_MPC8569 - bool - select FSL_LAW - select SYS_FSL_ERRATUM_A004508 - select SYS_FSL_ERRATUM_A005125 - select FSL_PCIE_RESET - select SYS_FSL_HAS_DDR3 - select SYS_FSL_HAS_SEC - select SYS_FSL_SEC_BE - select SYS_FSL_SEC_COMPAT_2 - select FSL_ELBC - imply CMD_NAND - config ARCH_MPC8572 bool select FSL_LAW @@ -1102,7 +1088,6 @@ config SYS_CCSRBAR_DEFAULT ARCH_MPC8555 || \ ARCH_MPC8560 || \ ARCH_MPC8568 || \ - ARCH_MPC8569 || \ ARCH_MPC8572 || \ ARCH_P1010 || \ ARCH_P1011 || \ @@ -1335,8 +1320,7 @@ config SYS_FSL_NUM_LAWS ARCH_P2020 default 10 if ARCH_MPC8544 || \ ARCH_MPC8548 || \ - ARCH_MPC8568 || \ - ARCH_MPC8569 + ARCH_MPC8568 default 8 if ARCH_MPC8540 || \ ARCH_MPC8541 || \ ARCH_MPC8555 || \ @@ -1428,16 +1412,18 @@ config SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). +config FSL_VIA + bool + +source "board/emulation/qemu-ppce500/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8541cds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" source "board/freescale/mpc8555cds/Kconfig" source "board/freescale/mpc8568mds/Kconfig" -source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/p1010rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" source "board/freescale/p2041rdb/Kconfig" -source "board/freescale/qemu-ppce500/Kconfig" source "board/freescale/t102xrdb/Kconfig" source "board/freescale/t104xrdb/Kconfig" source "board/freescale/t208xqds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 019fce6314..14e46626f3 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -65,7 +65,6 @@ obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o -obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 5170610f04..fc25bb28ad 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -395,7 +395,9 @@ int cpu_mmc_init(struct bd_info *bis) void print_reginfo(void) { print_tlbcam(); +#ifdef CONFIG_FSL_LAW print_laws(); +#endif #if defined(CONFIG_FSL_LBC) print_lbc_regs(); #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 4195ecc5c9..5a0d33b1b3 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -123,7 +123,9 @@ void cpu_init_early_f(void *fdt) setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); #endif +#ifdef CONFIG_FSL_LAW init_laws(); +#endif /* * Work Around for IFC Erratum A003399, issue will hit only when execution diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c deleted file mode 100644 index eb54b8252b..0000000000 --- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_serdes.h> - -#define SRDS1_MAX_LANES 4 - -static u32 serdes1_prtcl_map; - -static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { - [0x0] = {PCIE1, NONE, NONE, NONE}, - [0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2}, - [0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2}, - [0x3] = {SRIO1, SRIO2, NONE, NONE}, - [0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2}, - [0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, - [0x6] = {PCIE1, NONE, SRIO1, SRIO2}, - [0x7] = {PCIE1, PCIE1, SRIO1, SRIO2}, - [0x8] = {PCIE1, PCIE1, SRIO1, SRIO2}, - [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1}, - [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1}, - [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1}, - [0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2}, - [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1}, -}; - -int is_serdes_configured(enum srds_prtcl prtcl) -{ - if (!(serdes1_prtcl_map & (1 << NONE))) - fsl_serdes_init(); - - return (1 << prtcl) & serdes1_prtcl_map; -} - -void fsl_serdes_init(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; - int lane; - - if (serdes1_prtcl_map & (1 << NONE)) - return; - - debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); - - if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); - return; - } - - for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { - enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; - serdes1_prtcl_map |= (1 << lane_prtcl); - } - - /* Set the first bit to indicate serdes has been initialized */ - serdes1_prtcl_map |= (1 << NONE); -} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 09653c7012..9c89ce5d70 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -630,7 +630,7 @@ int get_clocks(void) gd->arch.i2c2_clk = gd->arch.i2c1_clk; #if defined(CONFIG_FSL_ESDHC) -#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) +#if defined(CONFIG_ARCH_P1010) gd->arch.sdhc_clk = gd->bus_clk; #else gd->arch.sdhc_clk = gd->bus_clk / 2; diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index dd784e7e30..f41e82ad18 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -344,39 +344,6 @@ l2_disabled: mtspr DBCR0,r0 #endif -#ifdef CONFIG_ARCH_MPC8569 -#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) -#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) - - /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to - * use address space which is more than 12bits, and it must be done in - * the 4K boot page. So we set this bit here. - */ - - /* create a temp mapping TLB0[0] for LBCR */ - create_tlb0_entry 0, \ - 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \ - CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \ - 0, r6 - - /* Set LBCR register */ - lis r4,CONFIG_SYS_LBCR_ADDR@h - ori r4,r4,CONFIG_SYS_LBCR_ADDR@l - - lis r5,CONFIG_SYS_LBC_LBCR@h - ori r5,r5,CONFIG_SYS_LBC_LBCR@l - stw r5,0(r4) - isync - - /* invalidate this temp TLB */ - lis r4,CONFIG_SYS_LBC_ADDR@h - ori r4,r4,CONFIG_SYS_LBC_ADDR@l - tlbivax 0,r4 - isync - -#endif /* CONFIG_ARCH_MPC8569 */ - /* * Search for the TLB that covers the code we're executing, and shrink it * so that it covers only this 4K page. That will ensure that any other diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h index c7086a8361..79ba7868c2 100644 --- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h @@ -18,7 +18,7 @@ #endif struct mpc8xxx_gpio_plat { - ulong addr; + phys_addr_t addr; unsigned long size; uint ngpios; }; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index f25ba1af09..4d70259f09 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -38,16 +38,6 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#elif defined(CONFIG_ARCH_MPC8569) -#define QE_MURAM_SIZE 0x20000UL -#define MAX_QE_RISC 4 -#define QE_NUM_OF_SNUM 46 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_RMU -#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 - #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index bfa601e91b..905613fa31 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -272,6 +272,7 @@ typedef struct ccsr_gpio { u32 gpier; u32 gpimr; u32 gpicr; + u32 gpibe; } ccsr_gpio_t; #endif @@ -2204,15 +2205,8 @@ typedef struct ccsr_gur { u32 gpiocr; /* GPIO control */ #endif u8 res3[12]; -#if defined(CONFIG_ARCH_MPC8569) - u32 plppar1; /* Platform port pin assignment 1 */ - u32 plppar2; /* Platform port pin assignment 2 */ - u32 plpdir1; /* Platform port pin direction 1 */ - u32 plpdir2; /* Platform port pin direction 2 */ -#else u32 gpoutdr; /* General-purpose output data */ u8 res4[12]; -#endif u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ @@ -2478,7 +2472,7 @@ typedef struct ccsr_gur { u32 svr; /* System version */ u8 res10[8]; u32 rstcr; /* Reset control */ -#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569) +#if defined(CONFIG_ARCH_MPC8568) u8 res11a[76]; par_io_t qe_par_io[7]; u8 res11b[1600]; diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 6d76e3e99c..998a82aa0d 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -10,7 +10,10 @@ #include <asm/byteorder.h> #ifdef CONFIG_ADDR_MAP +#include <asm/global_data.h> #include <addr_map.h> + +DECLARE_GLOBAL_DATA_PTR; #endif #define SIO_CONFIG_RA 0x398 @@ -303,20 +306,20 @@ static inline void out_be32(volatile unsigned __iomem *addr, u32 val) static inline void *phys_to_virt(phys_addr_t paddr) { #ifdef CONFIG_ADDR_MAP - return addrmap_phys_to_virt(paddr); -#else - return (void *)((unsigned long)paddr); + if (gd->flags & GD_FLG_RELOC) + return addrmap_phys_to_virt(paddr); #endif + return (void *)((unsigned long)paddr); } #define phys_to_virt phys_to_virt static inline phys_addr_t virt_to_phys(void * vaddr) { #ifdef CONFIG_ADDR_MAP - return addrmap_virt_to_phys(vaddr); -#else - return (phys_addr_t)((unsigned long)vaddr); + if (gd->flags & GD_FLG_RELOC) + return addrmap_virt_to_phys(vaddr); #endif + return (phys_addr_t)((unsigned long)vaddr); } #define virt_to_phys virt_to_phys |