diff options
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc83xx/Kconfig | 6 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc83xx/cpu_init.c | 13 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 86 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 7 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 19 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/u-boot.lds | 26 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/fdt.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/dts/p2020-post.dtsi | 77 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 45 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_secure_boot.h | 63 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_83xx.h | 22 |
12 files changed, 133 insertions, 237 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index d1b9ae4c3c..9a31604ba3 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -11,6 +11,11 @@ config E300 config SYS_CPU default "mpc83xx" +config SYS_83XX_DDR_USES_CS0 + bool + help + DDR should be configured using CS0 and CS1 instead of CS2 and CS3. + choice prompt "Target select" optional @@ -19,6 +24,7 @@ config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X select BOARD_EARLY_INIT_F + select SYS_83XX_DDR_USES_CS0 config TARGET_IDS8313 bool "Support ids8313" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index e3e1bfd65a..33835eeec2 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -251,19 +251,6 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif -#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X) - uint32_t temp; - struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - - /* Configure interface. */ - setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); - - /* Wait for clock to stabilize */ - do { - temp = __raw_readl(&ehci->control); - udelay(1000); - } while (!(temp & PHY_CLK_VALID)); -#endif } int cpu_init_r (void) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c1b4e94d91..915e28e110 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -109,6 +109,7 @@ config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" select ARCH_QEMU_E500 select PHYS_64BIT + select SYS_RAMBOOT imply OF_HAS_PRIOR_STAGE config TARGET_T1024RDB @@ -187,6 +188,7 @@ config ARCH_B4420 select E500MC select E6500 select FSL_LAW + select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 @@ -195,7 +197,7 @@ config ARCH_B4420 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 @@ -214,6 +216,7 @@ config ARCH_B4860 select E500MC select E6500 select FSL_LAW + select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 @@ -222,7 +225,7 @@ config ARCH_B4860 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 @@ -733,7 +736,7 @@ config ARCH_T2080 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -766,7 +769,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007798 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -822,11 +825,8 @@ config FSL_LAW help Use Freescale common code for Local Access Window -config NXP_ESBC - bool "NXP_ESBC" - help - Enable Freescale Secure Boot feature. Normally selected - by defconfig. If unsure, do not change. +config HETROGENOUS_CLUSTERS + bool config MAX_CPUS int "Maximum number of CPUs permitted for MPC85xx" @@ -1121,6 +1121,35 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs. +if HETROGENOUS_CLUSTERS + +config SYS_MAPLE + def_bool y + +config SYS_CPRI + def_bool y + +config PPC_CLUSTER_START + int + default 0 + +config DSP_CLUSTER_START + int + default 1 + +config SYS_CPRI_CLK + int + default 3 + +config SYS_ULB_CLK + int + default 4 + +config SYS_ETVPE_CLK + int + default 1 +endif + config BACKSIDE_L2_CACHE bool @@ -1185,6 +1214,45 @@ config SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). +config ENABLE_36BIT_PHYS + bool "Enable 36bit physical address space support" + +config SYS_BOOK3E_HV + bool "Category E.HV is supported" + depends on BOOKE + +config SYS_CPC_REINIT_F + bool + help + The CPC is configured as SRAM at the time of U-Boot entry and is + required to be re-initialized. + +config SYS_FSL_CPC + bool "Corenet Platform Cache support" + +config SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up" + depends on MPC85xx + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section. + +config SPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in SPL" + depends on MPC85xx && SPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + +config TPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in TPL" + depends on MPC85xx && TPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + config FSL_VIA bool diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9a28269020..8a6340d800 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1126,9 +1126,8 @@ switch_as: #else /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h - ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l - addi r3,r3,_start_cont - _start_cont + lis r3,_start_cont@h + ori r3,r3,_start_cont@l mtlr r3 blr #endif @@ -1600,7 +1599,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0,r10,in_ram - _start_cont + addi r0,r10,in_ram - CONFIG_VAL(SYS_MONITOR_BASE) /* * As IVPR is going to point RAM address, diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 06a70ff2af..62c3c51dea 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -9,24 +9,15 @@ #include "config.h" OUTPUT_ARCH(powerpc) -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} -#endif + SECTIONS { + . = IMAGE_TEXT_BASE; + .text : { /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg IMAGE_TEXT_BASE - 0x1000 : - { +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) KEEP(*(.bootpg)) - } :text = 0xffff #endif - . = IMAGE_TEXT_BASE; - .text : { *(.text*) } _etext = .; @@ -75,7 +66,7 @@ SECTIONS #endif /* For nor and nand is needed the SPL with section .resetvec */ -#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC +#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ #ifndef BOOT_PAGE_OFFSET #define BOOT_PAGE_OFFSET 0x1000 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 8bbe319b3e..8fba712655 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -14,32 +14,22 @@ OUTPUT_ARCH(powerpc) ENTRY(_start) -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - SECTIONS { /* Read-only sections, merged into text segment: */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 : + .text : { +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - . = CONFIG_SYS_TEXT_BASE; #endif - .text : - { *(.text*) - } :text + } _etext = .; PROVIDE (etext = .); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text + } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -84,16 +74,16 @@ SECTIONS __init_end = .; _end = .; -#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC +#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) .bootpg RESET_VECTOR_ADDRESS - 0xffc : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) - } :text = 0xffff + } = 0xffff .resetvec RESET_VECTOR_ADDRESS : { KEEP(*(.resetvec)) - } :text = 0xffff + } = 0xffff . = RESET_VECTOR_ADDRESS + 0x4; @@ -115,7 +105,7 @@ SECTIONS *(.sbss*) *(.bss*) *(COMMON) - } :bss + } . = ALIGN(4); __bss_end = . ; diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 67f8b10001..871554a7f4 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -17,10 +17,6 @@ #include <phy.h> #include <hwconfig.h> -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) { diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 0d0cd2273c..ea215ab075 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -13,49 +13,6 @@ compatible = "fsl,p2020-immr", "simple-bus"; bus-frequency = <0x0>; - usb@22000 { - compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; - reg = <0x22000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <28 0x2 0 0>; - phy_type = "ulpi"; - }; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic"; - device_type = "open-pic"; - big-endian; - single-cpu-affinity; - last-interrupt-source = <255>; - }; - - esdhc: sdhc@2e000 { - compatible = "fsl,p2020-esdhc", "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <72 0x2 0 0>; - /* Filled in by U-Boot */ - clock-frequency = <0>; - }; - - espi0: spi@7000 { - compatible = "fsl,mpc8536-espi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7000 0x1000>; - interrupts = < 0x3b 0x02 0x00 0x00 >; - fsl,espi-num-chipselects = <4>; - }; - -/include/ "pq3-i2c-0.dtsi" -/include/ "pq3-i2c-1.dtsi" -/include/ "pq3-duart-0.dtsi" -/include/ "pq3-gpio-0.dtsi" - ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; @@ -74,6 +31,22 @@ interrupts = <18 2 0 0>; }; +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" +/include/ "pq3-duart-0.dtsi" + + espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + interrupts = < 0x3b 0x02 0x00 0x00 >; + fsl,espi-num-chipselects = <4>; + }; + +/include/ "pq3-dma-1.dtsi" +/include/ "pq3-gpio-0.dtsi" + L2: l2-cache-controller@20000 { compatible = "fsl,p2020-l2-cache-controller"; reg = <0x20000 0x1000>; @@ -83,7 +56,15 @@ }; /include/ "pq3-dma-0.dtsi" -/include/ "pq3-dma-1.dtsi" + + usb@22000 { + compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; + reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <28 0x2 0 0>; + phy_type = "ulpi"; + }; /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" @@ -95,6 +76,14 @@ /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" + esdhc: sdhc@2e000 { + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2 0 0>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; + /include/ "pq3-sec3.1-0.dtsi" /include/ "pq3-mpic.dtsi" /include/ "pq3-mpic-timer-B.dtsi" diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 059ffe1fd4..79fe567b58 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -14,8 +14,6 @@ #define HWCONFIG_BUFFER_SIZE 256 #endif -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #ifndef CONFIG_MAX_MEM_MAPPED #if defined(CONFIG_E500) || \ defined(CONFIG_MPC86xx) || \ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 47bfcc7244..a43e6e5e53 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -18,8 +18,6 @@ /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SEC_MON_BE #if defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 @@ -31,35 +29,27 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_ESDHC_HC_BLK_ADDR /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -68,11 +58,9 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -84,7 +72,6 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -92,9 +79,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -118,7 +102,6 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -132,7 +115,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" @@ -151,7 +133,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" @@ -163,16 +144,13 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 @@ -180,7 +158,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_T4240) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -204,7 +181,6 @@ #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 @@ -219,33 +195,21 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SFP_VER_3_0 -#define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ -#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ -#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_MAPLE -#define CONFIG_SYS_CPRI #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FM1_CLK 0 -#define CONFIG_SYS_CPRI_CLK 3 -#define CONFIG_SYS_ULB_CLK 4 -#define CONFIG_SYS_ETVPE_CLK 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_SFP_VER_3_0 #ifdef CONFIG_ARCH_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 @@ -255,7 +219,6 @@ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -278,7 +241,6 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -295,7 +257,6 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T1024) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -309,7 +270,6 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 @@ -323,7 +283,6 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T2080) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -333,7 +292,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_PCI_VER_3_X #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 4 @@ -343,7 +301,6 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK 0 @@ -354,10 +311,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_C29X) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3a1d858ec6..3e707600f2 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,28 +10,17 @@ #ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 -#elif defined(CONFIG_TARGET_BSC9132QDS) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 -#elif defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 -#if defined(CONFIG_TARGET_B4860QDS) || \ - defined(CONFIG_TARGET_B4420QDS) || \ - defined(CONFIG_TARGET_T4240QDS) || \ - defined(CONFIG_TARGET_T2080QDS) || \ +#if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ defined(CONFIG_TARGET_T1042RDB) || \ defined(CONFIG_TARGET_T1042D4RDB) || \ defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_CPC_REINIT_F -#endif -#define CONFIG_KEY_REVOCATION #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 #endif @@ -47,10 +36,6 @@ #endif #endif -#if defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_KEY_REVOCATION -#endif - #if defined(CONFIG_ARCH_P3041) || \ defined(CONFIG_ARCH_P4080) || \ defined(CONFIG_ARCH_P5040) || \ @@ -80,55 +65,9 @@ #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 #define CONFIG_SPL_JR0_LIODN_S 454 #define CONFIG_SPL_JR0_LIODN_NS 458 -/* - * Define the key hash for U-Boot here if public/private key pair used to - * sign U-boot are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_SPL_UBOOT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - * else leave it defined as NULL - */ - -#define CONFIG_SPL_UBOOT_KEY_HASH NULL #endif /* ifdef CONFIG_SPL_BUILD */ -#define CONFIG_FSL_SEC_MON - #ifndef CONFIG_SPL_BUILD -/* - * fsl_setenv_chain_of_trust() must be called from - * board_late_init() - */ - -/* If Boot Script is not on NOR and is required to be copied on RAM */ -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_HDR_ADDR_RAM 0x00010000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#define CONFIG_BS_ADDR_RAM 0x00012000 -#define CONFIG_BS_ADDR_DEVICE 0x00802000 -#define CONFIG_BS_SIZE 0x00001000 - -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#else - -/* The bootscript header address is different for B4860 because the NOR - * mapping is different on B4 due to reduced NOR size. - */ -#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 -#elif defined(CONFIG_FSL_CORENET) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 -#elif defined(CONFIG_TARGET_BSC9132QDS) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 -#elif defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 -#else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 -#endif - -#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ - #include <config_fsl_chain_trust.h> #endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index d2443dc90d..6d1ddbcd27 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -666,19 +666,6 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#ifndef CONFIG_ARCH_MPC834X -#ifdef CONFIG_HAS_FSL_MPH_USB -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 -#else -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ -#endif -#else -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 -#endif - #elif defined(CONFIG_ARCH_MPC8313) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ @@ -944,15 +931,6 @@ struct ccsr_gpio { #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) -#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000 -#endif -#define CONFIG_SYS_MPC83xx_USB1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) -#if defined(CONFIG_ARCH_MPC834X) -#define CONFIG_SYS_MPC83xx_USB2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) -#endif #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |