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-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig6
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu_init.c13
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig86
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S7
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-spl.lds19
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot.lds26
-rw-r--r--arch/powerpc/cpu/mpc8xxx/fdt.c4
7 files changed, 99 insertions, 62 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index d1b9ae4c3c..9a31604ba3 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -11,6 +11,11 @@ config E300
config SYS_CPU
default "mpc83xx"
+config SYS_83XX_DDR_USES_CS0
+ bool
+ help
+ DDR should be configured using CS0 and CS1 instead of CS2 and CS3.
+
choice
prompt "Target select"
optional
@@ -19,6 +24,7 @@ config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
select ARCH_MPC837X
select BOARD_EARLY_INIT_F
+ select SYS_83XX_DDR_USES_CS0
config TARGET_IDS8313
bool "Support ids8313"
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index e3e1bfd65a..33835eeec2 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -251,19 +251,6 @@ void cpu_init_f (volatile immap_t * im)
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
-#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
- uint32_t temp;
- struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
-
- /* Configure interface. */
- setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
-
- /* Wait for clock to stabilize */
- do {
- temp = __raw_readl(&ehci->control);
- udelay(1000);
- } while (!(temp & PHY_CLK_VALID));
-#endif
}
int cpu_init_r (void)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index c1b4e94d91..915e28e110 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -109,6 +109,7 @@ config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
select ARCH_QEMU_E500
select PHYS_64BIT
+ select SYS_RAMBOOT
imply OF_HAS_PRIOR_STAGE
config TARGET_T1024RDB
@@ -187,6 +188,7 @@ config ARCH_B4420
select E500MC
select E6500
select FSL_LAW
+ select HETROGENOUS_CLUSTERS
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A005871
@@ -195,7 +197,7 @@ config ARCH_B4420
select SYS_FSL_ERRATUM_A006475
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007075
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
@@ -214,6 +216,7 @@ config ARCH_B4860
select E500MC
select E6500
select FSL_LAW
+ select HETROGENOUS_CLUSTERS
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A005871
@@ -222,7 +225,7 @@ config ARCH_B4860
select SYS_FSL_ERRATUM_A006475
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007075
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
@@ -733,7 +736,7 @@ config ARCH_T2080
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
@@ -766,7 +769,7 @@ config ARCH_T4240
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007798
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
@@ -822,11 +825,8 @@ config FSL_LAW
help
Use Freescale common code for Local Access Window
-config NXP_ESBC
- bool "NXP_ESBC"
- help
- Enable Freescale Secure Boot feature. Normally selected
- by defconfig. If unsure, do not change.
+config HETROGENOUS_CLUSTERS
+ bool
config MAX_CPUS
int "Maximum number of CPUs permitted for MPC85xx"
@@ -1121,6 +1121,35 @@ config SYS_NUM_TLBCAMS
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
+if HETROGENOUS_CLUSTERS
+
+config SYS_MAPLE
+ def_bool y
+
+config SYS_CPRI
+ def_bool y
+
+config PPC_CLUSTER_START
+ int
+ default 0
+
+config DSP_CLUSTER_START
+ int
+ default 1
+
+config SYS_CPRI_CLK
+ int
+ default 3
+
+config SYS_ULB_CLK
+ int
+ default 4
+
+config SYS_ETVPE_CLK
+ int
+ default 1
+endif
+
config BACKSIDE_L2_CACHE
bool
@@ -1185,6 +1214,45 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
+config ENABLE_36BIT_PHYS
+ bool "Enable 36bit physical address space support"
+
+config SYS_BOOK3E_HV
+ bool "Category E.HV is supported"
+ depends on BOOKE
+
+config SYS_CPC_REINIT_F
+ bool
+ help
+ The CPC is configured as SRAM at the time of U-Boot entry and is
+ required to be re-initialized.
+
+config SYS_FSL_CPC
+ bool "Corenet Platform Cache support"
+
+config SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up"
+ depends on MPC85xx
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section.
+
+config SPL_SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up, in SPL"
+ depends on MPC85xx && SPL
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section,
+ of the SPL portion of the binary.
+
+config TPL_SYS_MPC85XX_NO_RESETVEC
+ bool "Discard resetvec section and move bootpg section up, in TPL"
+ depends on MPC85xx && TPL
+ help
+ If this variable is specified, the section .resetvec is not kept and
+ the section .bootpg is placed in the previous 4k of the .text section,
+ of the SPL portion of the binary.
+
config FSL_VIA
bool
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 9a28269020..8a6340d800 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1126,9 +1126,8 @@ switch_as:
#else
/* Calculate absolute address in FLASH and jump there */
/*--------------------------------------------------------------*/
- lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h
- ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l
- addi r3,r3,_start_cont - _start_cont
+ lis r3,_start_cont@h
+ ori r3,r3,_start_cont@l
mtlr r3
blr
#endif
@@ -1600,7 +1599,7 @@ relocate_code:
* initialization, now running from RAM.
*/
- addi r0,r10,in_ram - _start_cont
+ addi r0,r10,in_ram - CONFIG_VAL(SYS_MONITOR_BASE)
/*
* As IVPR is going to point RAM address,
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 06a70ff2af..62c3c51dea 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -9,24 +9,15 @@
#include "config.h"
OUTPUT_ARCH(powerpc)
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
-PHDRS
-{
- text PT_LOAD;
- bss PT_LOAD;
-}
-#endif
+
SECTIONS
{
+ . = IMAGE_TEXT_BASE;
+ .text : {
/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg IMAGE_TEXT_BASE - 0x1000 :
- {
+#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
KEEP(*(.bootpg))
- } :text = 0xffff
#endif
- . = IMAGE_TEXT_BASE;
- .text : {
*(.text*)
}
_etext = .;
@@ -75,7 +66,7 @@ SECTIONS
#endif
/* For nor and nand is needed the SPL with section .resetvec */
-#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC
+#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
#ifndef BOOT_PAGE_OFFSET
#define BOOT_PAGE_OFFSET 0x1000
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 8bbe319b3e..8fba712655 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -14,32 +14,22 @@
OUTPUT_ARCH(powerpc)
ENTRY(_start)
-PHDRS
-{
- text PT_LOAD;
- bss PT_LOAD;
-}
-
SECTIONS
{
/* Read-only sections, merged into text segment: */
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
- .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 :
+ .text :
{
+#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
- } :text = 0xffff
- . = CONFIG_SYS_TEXT_BASE;
#endif
- .text :
- {
*(.text*)
- } :text
+ }
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- } :text
+ }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
@@ -84,16 +74,16 @@ SECTIONS
__init_end = .;
_end = .;
-#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC
+#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
- } :text = 0xffff
+ } = 0xffff
.resetvec RESET_VECTOR_ADDRESS :
{
KEEP(*(.resetvec))
- } :text = 0xffff
+ } = 0xffff
. = RESET_VECTOR_ADDRESS + 0x4;
@@ -115,7 +105,7 @@ SECTIONS
*(.sbss*)
*(.bss*)
*(COMMON)
- } :bss
+ }
. = ALIGN(4);
__bss_end = . ;
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 67f8b10001..871554a7f4 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -17,10 +17,6 @@
#include <phy.h>
#include <hwconfig.h>
-#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
{
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-28 08:15:53 +0000