diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
22 files changed, 58 insertions, 58 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c index b972cf3b5e..7921334827 100644 --- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -76,7 +76,7 @@ int is_serdes_configured(enum srds_prtcl prtcl) void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c index 34b58bb7f9..e53dd43f31 100644 --- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device) void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 14d5c560bf..432d4b11dc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -59,7 +59,7 @@ int checkcpu (void) #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \ defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif /* @@ -124,7 +124,7 @@ int checkcpu (void) puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); @@ -319,7 +319,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) val |= 0x70000000; mtspr(DBCR0,val); #else - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); /* Call board-specific preparation for reset */ board_reset_prepare(); @@ -436,7 +436,7 @@ int dram_init(void) #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); unsigned int x = 10; unsigned int i; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 90f024d0a7..9fb7802f9e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -302,7 +302,7 @@ static void corenet_tb_init(void) volatile ccsr_rcpm_t *rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); volatile ccsr_pic_t *pic = - (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); u32 whoami = in_be32(&pic->whoami); /* Enable the timebase register for this core */ @@ -313,7 +313,7 @@ static void corenet_tb_init(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 void fsl_erratum_a007212_workaround(void) { - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_pll_ratio; u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); @@ -379,13 +379,13 @@ ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif #ifdef CONFIG_ARCH_MPC8548 - ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); /* @@ -455,7 +455,7 @@ int enable_cluster_l2(void) { int i = 0; u32 cluster, svr = get_svr(); - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache; /* only the L2 of first cluster should be enabled as expected on T4080, @@ -516,7 +516,7 @@ int l2cache_init(void) { __maybe_unused u32 svr = get_svr(); #ifdef CONFIG_L2_CACHE - ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR; #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif @@ -821,7 +821,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE { struct ccsr_usb_phy __iomem *usb_phy1 = - (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) fsl_erratum_a006261_workaround(usb_phy1); @@ -833,7 +833,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE { struct ccsr_usb_phy __iomem *usb_phy2 = - (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; + (void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR; #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) fsl_erratum_a006261_workaround(usb_phy2); @@ -859,7 +859,7 @@ int cpu_init_r(void) #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) struct ccsr_usb_phy __iomem *usb_phy = - (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; setbits_be32(&usb_phy->pllprg[1], CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | @@ -928,11 +928,11 @@ int cpu_init_r(void) fsl_sata_reg_t *reg; /* first SATA controller */ - reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; + reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR; clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); /* second SATA controller */ - reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; + reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR; clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index e6d3058dd5..18bfa2aed1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -85,10 +85,10 @@ void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #ifdef CONFIG_A003399_NOR_WORKAROUND - ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; u32 *dst, *src; void (*setup_ifc_sram)(void); int i; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 61d8aa7f4c..811e6d6ddd 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -222,7 +222,7 @@ static inline void ft_fixup_l2cache_compatible(void *blob, int off) /* return size in kilobytes */ static inline u32 l2cache_size(void) { - volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; u32 ver = SVR_SOC_VER(get_svr()); @@ -509,7 +509,7 @@ static void ft_fixup_qe_snum(void *blob) #if defined(CONFIG_ARCH_P4080) static void fdt_fixup_usb(void *fdt) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]); int off; @@ -532,7 +532,7 @@ void fdt_fixup_dma3(void *blob) { /* the 3rd DMA is not functional if SRIO2 is chosen */ int nodeoff; - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) #if defined(CONFIG_ARCH_T2080) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index da8e0b6555..1a30395256 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -122,7 +122,7 @@ int is_serdes_configured(enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { - const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 cfg = in_be32(&gur->rcwsr[4]); int i; @@ -193,7 +193,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 cfg; int lane; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 2b4912bea0..1d35733c01 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -108,7 +108,7 @@ int serdes_get_bank_by_lane(int lane) int serdes_lane_enabled(int lane) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; int bank = lanes[lane].bank; @@ -133,7 +133,7 @@ int serdes_lane_enabled(int lane) int is_serdes_configured(enum srds_prtcl device) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -169,7 +169,7 @@ int serdes_get_first_lane(enum srds_prtcl device) u32 prtcl; const ccsr_gur_t *gur; - gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR; /* Is serdes enabled at all? */ if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) @@ -251,7 +251,7 @@ void serdes_reset_rx(enum srds_prtcl device) if (unlikely(device == NONE)) return; - gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR; /* Is serdes enabled at all? */ if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) @@ -491,7 +491,7 @@ void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init"))); void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; #ifdef CONFIG_ARCH_P5040 diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index 4ad762683f..bcbdfac027 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -25,7 +25,7 @@ void interrupt_init_cpu(unsigned *decrementer_count) { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR; #ifdef CONFIG_POST /* diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 84eb8b466b..e1469eb296 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -50,7 +50,7 @@ int hold_cores_in_reset(int verbose) int cpu_reset(u32 nr) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); /* the dummy read works around an errata on early 85xx MP PICs */ (void)in_be32(&pic->pir); @@ -87,7 +87,7 @@ int cpu_status(u32 nr) #ifdef CONFIG_FSL_CORENET int cpu_disable(u32 nr) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); setbits_be32(&gur->coredisrl, 1 << nr); @@ -95,7 +95,7 @@ int cpu_disable(u32 nr) } int is_core_disabled(int nr) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 coredisrl = in_be32(&gur->coredisrl); return (coredisrl & (1 << nr)); @@ -103,7 +103,7 @@ int is_core_disabled(int nr) { #else int cpu_disable(u32 nr) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); switch (nr) { case 0: @@ -121,7 +121,7 @@ int cpu_disable(u32 nr) } int is_core_disabled(int nr) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr = in_be32(&gur->devdisr); switch (nr) { @@ -264,10 +264,10 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) u32 mask = cpu_mask(); struct law_entry e; - gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); - pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); whoami = in_be32(&pic->whoami); cpu_up_mask = 1 << whoami; @@ -336,9 +336,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)&__spin_table; volatile u32 bpcr; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); u32 devdisr; int timeout = 10; diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index 111692f15d..cbcb57fe3a 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -89,8 +89,8 @@ int is_serdes_configured(enum srds_prtcl device) void fsl_serdes_init(void) { - void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR; + void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR; u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); u32 srds1_io_sel, srds2_io_sel; u32 tmp; diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c index f3b5450ad5..a48f3c1512 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -52,7 +52,7 @@ int is_serdes_configured(enum srds_prtcl device) void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c index 38f30afdfc..479ee085d3 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -32,7 +32,7 @@ int is_serdes_configured(enum srds_prtcl prtcl) void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index 8cba4222c4..56e5ef6468 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -51,7 +51,7 @@ int is_serdes_configured(enum srds_prtcl device) void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index 6b8e447e94..47f13e3c1c 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -50,8 +50,8 @@ int is_serdes_configured(enum srds_prtcl prtcl) void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR; + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c index bf5cac6199..7a8f653727 100644 --- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device) void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c index f36b1b64ed..8c5d82ae8a 100644 --- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl prtcl) void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index c5b1443058..3cf41ca76d 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -20,7 +20,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) &(gur->qe_par_io); diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 6686b7c93c..a7004a670b 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(sys_info_t *sys_info) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; @@ -575,7 +575,7 @@ int get_clocks(void) { sys_info_t sys_info; #ifdef CONFIG_ARCH_MPC8544 - volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; + volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR; #endif get_sys_info (&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index bdd73389d9..47df3c2ce1 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR; ulong cpu_init_f(void) { #ifdef CONFIG_SYS_INIT_L2_ADDR - ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9d44fa4158..024414e9ff 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -80,7 +80,7 @@ /* Definitions from C header file asm/immap_85xx.h */ -#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 +#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000 #define MPC85xx_L2CTL 0x000 #define MPC85xx_L2CTL_L2E 0x80000000 @@ -127,13 +127,13 @@ bootsect: .org 0x80 /* Start of configuration */ .Lconf_pair_start: - .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ .long CONFIG_SYS_INIT_L2_ADDR - .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC - .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */ + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */ .long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE .long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */ diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 97ed24a6eb..8f451b4862 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -260,7 +260,7 @@ void UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); uint vect; |