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-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig14
-rw-r--r--arch/powerpc/cpu/mpc83xx/elbc/elbc.h170
-rw-r--r--arch/powerpc/cpu/mpc83xx/pcie.c3
-rw-r--r--arch/powerpc/cpu/mpc83xx/speed.c4
-rw-r--r--arch/powerpc/cpu/mpc83xx/spl_minimal.c2
-rw-r--r--arch/powerpc/cpu/mpc83xx/start.S5
6 files changed, 12 insertions, 186 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index cff98f7599..bcd8375087 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -179,13 +179,6 @@ config ARCH_MPC837X
select SYS_CACHE_SHIFT_5
select FSL_ELBC
-config SYS_IMMR
- hex "Value for IMMR"
- default 0xE0000000
- help
- Address for the Internal Memory-Mapped Registers (IMMR) window used
- to configure the features of the SoC.
-
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
@@ -195,6 +188,13 @@ source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
+config 83XX_PCICLK
+ hex "PCI clock frequency"
+ default 0xDEADBEEF
+ help
+ If required, the PCI clock frequency to use when configuring
+ the host bridge.
+
config FSL_ELBC
bool
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
index 245fe7c6fb..e795cd10cb 100644
--- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
+++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
@@ -1,173 +1,3 @@
-#ifdef CONFIG_ELBC_BR0_OR0
-#define CONFIG_SYS_BR0_PRELIM (\
- CONFIG_BR0_OR0_BASE |\
- CONFIG_BR0_PORTSIZE |\
- CONFIG_BR0_ERRORCHECKING |\
- CONFIG_BR0_WRITE_PROTECT_BIT |\
- CONFIG_BR0_MACHINE |\
- CONFIG_BR0_ATOMIC |\
- CONFIG_BR0_VALID_BIT \
-)
-#define CONFIG_SYS_OR0_PRELIM (\
- CONFIG_OR0_AM |\
- CONFIG_OR0_XAM |\
- CONFIG_OR0_BCTLD |\
- CONFIG_OR0_BI |\
- CONFIG_OR0_COLS |\
- CONFIG_OR0_ROWS |\
- CONFIG_OR0_PMSEL |\
- CONFIG_OR0_SCY |\
- CONFIG_OR0_PGS |\
- CONFIG_OR0_CSCT |\
- CONFIG_OR0_CST |\
- CONFIG_OR0_CHT |\
- CONFIG_OR0_RST |\
- CONFIG_OR0_CSNT |\
- CONFIG_OR0_ACS |\
- CONFIG_OR0_XACS |\
- CONFIG_OR0_SETA |\
- CONFIG_OR0_TRLX |\
- CONFIG_OR0_EHTR |\
- CONFIG_OR0_EAD \
-)
-#endif /* CONFIG_ELBC_BR0_OR0 */
-
-#ifdef CONFIG_ELBC_BR1_OR1
-#define CONFIG_SYS_BR1_PRELIM (\
- CONFIG_BR1_OR1_BASE |\
- CONFIG_BR1_PORTSIZE |\
- CONFIG_BR1_ERRORCHECKING |\
- CONFIG_BR1_WRITE_PROTECT_BIT |\
- CONFIG_BR1_MACHINE |\
- CONFIG_BR1_ATOMIC |\
- CONFIG_BR1_VALID_BIT \
-)
-#define CONFIG_SYS_OR1_PRELIM (\
- CONFIG_OR1_AM |\
- CONFIG_OR1_XAM |\
- CONFIG_OR1_BCTLD |\
- CONFIG_OR1_BI |\
- CONFIG_OR1_COLS |\
- CONFIG_OR1_ROWS |\
- CONFIG_OR1_PMSEL |\
- CONFIG_OR1_SCY |\
- CONFIG_OR1_PGS |\
- CONFIG_OR1_CSCT |\
- CONFIG_OR1_CST |\
- CONFIG_OR1_CHT |\
- CONFIG_OR1_RST |\
- CONFIG_OR1_CSNT |\
- CONFIG_OR1_ACS |\
- CONFIG_OR1_XACS |\
- CONFIG_OR1_SETA |\
- CONFIG_OR1_TRLX |\
- CONFIG_OR1_EHTR |\
- CONFIG_OR1_EAD \
-)
-#endif /* CONFIG_ELBC_BR1_OR1 */
-
-#ifdef CONFIG_ELBC_BR2_OR2
-#define CONFIG_SYS_BR2_PRELIM (\
- CONFIG_BR2_OR2_BASE |\
- CONFIG_BR2_PORTSIZE |\
- CONFIG_BR2_ERRORCHECKING |\
- CONFIG_BR2_WRITE_PROTECT_BIT |\
- CONFIG_BR2_MACHINE |\
- CONFIG_BR2_ATOMIC |\
- CONFIG_BR2_VALID_BIT \
-)
-#define CONFIG_SYS_OR2_PRELIM (\
- CONFIG_OR2_AM |\
- CONFIG_OR2_XAM |\
- CONFIG_OR2_BCTLD |\
- CONFIG_OR2_BI |\
- CONFIG_OR2_COLS |\
- CONFIG_OR2_ROWS |\
- CONFIG_OR2_PMSEL |\
- CONFIG_OR2_SCY |\
- CONFIG_OR2_PGS |\
- CONFIG_OR2_CSCT |\
- CONFIG_OR2_CST |\
- CONFIG_OR2_CHT |\
- CONFIG_OR2_RST |\
- CONFIG_OR2_CSNT |\
- CONFIG_OR2_ACS |\
- CONFIG_OR2_XACS |\
- CONFIG_OR2_SETA |\
- CONFIG_OR2_TRLX |\
- CONFIG_OR2_EHTR |\
- CONFIG_OR2_EAD \
-)
-#endif /* CONFIG_ELBC_BR2_OR2 */
-
-#ifdef CONFIG_ELBC_BR3_OR3
-#define CONFIG_SYS_BR3_PRELIM (\
- CONFIG_BR3_OR3_BASE |\
- CONFIG_BR3_PORTSIZE |\
- CONFIG_BR3_ERRORCHECKING |\
- CONFIG_BR3_WRITE_PROTECT_BIT |\
- CONFIG_BR3_MACHINE |\
- CONFIG_BR3_ATOMIC |\
- CONFIG_BR3_VALID_BIT \
-)
-#define CONFIG_SYS_OR3_PRELIM (\
- CONFIG_OR3_AM |\
- CONFIG_OR3_XAM |\
- CONFIG_OR3_BCTLD |\
- CONFIG_OR3_BI |\
- CONFIG_OR3_COLS |\
- CONFIG_OR3_ROWS |\
- CONFIG_OR3_PMSEL |\
- CONFIG_OR3_SCY |\
- CONFIG_OR3_PGS |\
- CONFIG_OR3_CSCT |\
- CONFIG_OR3_CST |\
- CONFIG_OR3_CHT |\
- CONFIG_OR3_RST |\
- CONFIG_OR3_CSNT |\
- CONFIG_OR3_ACS |\
- CONFIG_OR3_XACS |\
- CONFIG_OR3_SETA |\
- CONFIG_OR3_TRLX |\
- CONFIG_OR3_EHTR |\
- CONFIG_OR3_EAD \
-)
-#endif /* CONFIG_ELBC_BR3_OR3 */
-
-#ifdef CONFIG_ELBC_BR4_OR4
-#define CONFIG_SYS_BR4_PRELIM (\
- CONFIG_BR4_OR4_BASE |\
- CONFIG_BR4_PORTSIZE |\
- CONFIG_BR4_ERRORCHECKING |\
- CONFIG_BR4_WRITE_PROTECT_BIT |\
- CONFIG_BR4_MACHINE |\
- CONFIG_BR4_ATOMIC |\
- CONFIG_BR4_VALID_BIT \
-)
-#define CONFIG_SYS_OR4_PRELIM (\
- CONFIG_OR4_AM |\
- CONFIG_OR4_XAM |\
- CONFIG_OR4_BCTLD |\
- CONFIG_OR4_BI |\
- CONFIG_OR4_COLS |\
- CONFIG_OR4_ROWS |\
- CONFIG_OR4_PMSEL |\
- CONFIG_OR4_SCY |\
- CONFIG_OR4_PGS |\
- CONFIG_OR4_CSCT |\
- CONFIG_OR4_CST |\
- CONFIG_OR4_CHT |\
- CONFIG_OR4_RST |\
- CONFIG_OR4_CSNT |\
- CONFIG_OR4_ACS |\
- CONFIG_OR4_XACS |\
- CONFIG_OR4_SETA |\
- CONFIG_OR4_TRLX |\
- CONFIG_OR4_EHTR |\
- CONFIG_OR4_EAD \
-)
-#endif /* CONFIG_ELBC_BR4_OR4 */
-
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index c386e4ed3f..d2b6b05bda 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <clock_legacy.h>
#include <pci.h>
#include <mpc83xx.h>
#include <asm/global_data.h>
@@ -46,7 +47,7 @@ int get_pcie_clk(int index)
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
sccr = im->clk.sccr;
- pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+ pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index e5db96b328..f835263f25 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -137,8 +137,8 @@ int get_clocks(void)
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_SYS_CLK_FREQ)
- pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+#if CONFIG_SYS_CLK_FREQ != 0
+ pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 00cb2bd044..11b1e613fb 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -102,5 +102,5 @@ ulong get_bus_freq(ulong dummy)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
- return CONFIG_SYS_CLK_FREQ * spmf;
+ return get_board_sys_clk() * spmf;
}
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index c4953df4a2..0944d19105 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -14,8 +14,6 @@
#include <config.h>
#include <mpc83xx.h>
-#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@@ -115,9 +113,6 @@ disable_addr_trans:
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
#endif /* CONFIG_DEFAULT_IMMR */
-#ifndef CONFIG_SYS_IMMR
-#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
-#endif /* CONFIG_SYS_IMMR */
/*
* After configuration, a system reset exception is executed using the