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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/cpu/armv8/Makefile2
-rw-r--r--arch/arm/cpu/armv8/fel_utils.S78
-rw-r--r--arch/arm/dts/Makefile4
-rw-r--r--arch/arm/dts/sama7g5.dtsi170
-rw-r--r--arch/arm/dts/sama7g5ek-u-boot.dtsi65
-rw-r--r--arch/arm/dts/sama7g5ek.dts202
-rw-r--r--arch/arm/include/asm/arch-sunxi/boot0.h14
-rw-r--r--arch/arm/include/asm/arch-sunxi/spl.h68
-rw-r--r--arch/arm/mach-at91/Kconfig8
-rw-r--r--arch/arm/mach-sunxi/Kconfig11
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_h6.c100
12 files changed, 613 insertions, 110 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b5235e740..95557d6ed6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1046,6 +1046,7 @@ config ARCH_SUNXI
select SPL_USE_TINY_PRINTF
select USE_PREBOOT
select SYS_RELOC_GD_ENV_ADDR
+ imply BOARD_LATE_INIT
imply CMD_DM
imply CMD_GPT
imply CMD_UBI if MTD_RAW_NAND
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 93d26f9856..f7b4a5ee46 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -27,6 +27,8 @@ obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
+else
+obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
endif
obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
new file mode 100644
index 0000000000..9510dcd9e4
--- /dev/null
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -0,0 +1,78 @@
+/*
+ * Utility functions for FEL mode, when running SPL in AArch64.
+ *
+ * Copyright (c) 2017 Arm Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+/*
+ * We don't overwrite save_boot_params() here, to save the FEL state upon
+ * entry, since this would run *after* the RMR reset, which clobbers that
+ * state.
+ * Instead we store the state _very_ early in the boot0 hook, *before*
+ * resetting to AArch64.
+ */
+
+/*
+ * The FEL routines in BROM run in AArch32.
+ * Reset back into 32-bit mode here and restore the saved FEL state
+ * afterwards.
+ * Resetting back into AArch32/EL3 using the RMR always enters the BROM,
+ * but we can use the CPU hotplug mechanism to branch back to our code
+ * immediately.
+ */
+ENTRY(return_to_fel)
+ /*
+ * the RMR reset will clear all registers, so save the arguments
+ * (LR and SP) in the fel_stash structure, which we read anyways later
+ */
+ adr x2, fel_stash
+ str w0, [x2]
+ str w1, [x2, #4]
+
+ adr x1, fel_stash_addr // to find the fel_stash address in AA32
+ str w2, [x1]
+
+ ldr x0, =0xfa50392f // CPU hotplug magic
+#ifdef CONFIG_MACH_SUN50I_H6
+ ldr x2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG
+ str w0, [x2], #0x4
+#else
+ ldr x2, =(SUNXI_CPUCFG_BASE + 0x1a4) // offset for CPU hotplug base
+ str w0, [x2, #0x8]
+#endif
+ adr x0, back_in_32
+ str w0, [x2]
+
+ dsb sy
+ isb sy
+ mov x0, #2 // RMR reset into AArch32
+ dsb sy
+ msr RMR_EL3, x0
+ isb sy
+1: wfi
+ b 1b
+
+/* AArch32 code to restore the state from fel_stash and return back to FEL. */
+back_in_32:
+ .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
+ .word 0xe5901008 // ldr r1, [r0, #8]
+ .word 0xe129f001 // msr CPSR_fc, r1
+ .word 0xf57ff06f // isb
+ .word 0xe590d000 // ldr sp, [r0]
+ .word 0xe590e004 // ldr lr, [r0, #4]
+ .word 0xe5901010 // ldr r1, [r0, #16]
+ .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
+ .word 0xe590100c // ldr r1, [r0, #12]
+ .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
+ .word 0xf57ff06f // isb
+ .word 0xe12fff1e // bx lr ; return to FEL
+fel_stash_addr:
+ .word 0x00000000 // receives fel_stash addr, by AA64 code above
+ENDPROC(return_to_fel)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd47e408f8..0f738c224f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -590,6 +590,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+ sun8i-s3-pinecube.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-bananapi-m2-plus.dtb \
@@ -889,6 +890,9 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
omap5-uevm.dtb
+dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
+ sama7g5ek.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb
diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
new file mode 100644
index 0000000000..0cb6eaf5d0
--- /dev/null
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Eugen Hristev <eugen.hristev@microchip.com>
+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
+ *
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clk/at91.h>
+
+/ {
+ model = "Microchip SAMA7G5 family SoC";
+ compatible = "microchip,sama7g5";
+
+ clocks {
+ slow_rc_osc: slow_rc_osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+
+ main_rc: main_rc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
+ clock-names = "cpu", "master", "xtal";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pioA: pinctrl@e0014000 {
+ compatible = "atmel,sama5d2-gpio";
+ reg = <0xe0014000 0x800>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+ status = "okay";
+
+ pinctrl: pinctrl_default {
+ compatible = "microchip,sama7g5-pinctrl";
+ };
+ };
+
+ pmc: pmc@e0018000 {
+ compatible = "microchip,sama7g5-pmc";
+ reg = <0xe0018000 0x200>;
+ #clock-cells = <2>;
+ clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
+ clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
+ status = "okay";
+ };
+
+ clk32: sckc@e001d050 {
+ compatible = "microchip,sam9x60-sckc";
+ reg = <0xe001d050 0x4>;
+ clocks = <&slow_rc_osc>, <&slow_xtal>;
+ #clock-cells = <1>;
+ };
+
+ sdmmc0: sdio-host@e1204000 {
+ compatible = "microchip,sama7g5-sdhci";
+ reg = <0xe1204000 0x300>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
+ assigned-clock-rates = <200000000>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
+ status = "disabled";
+ };
+
+ sdmmc1: sdio-host@e1208000 {
+ compatible = "microchip,sama7g5-sdhci";
+ reg = <0xe1208000 0x300>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
+ assigned-clock-rates = <200000000>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
+ status = "disabled";
+ };
+
+ pit64b0: timer@e1800000 {
+ compatible = "microchip,sama7g5-pit64b";
+ reg = <0xe1800000 0x4000>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
+ clock-names = "pclk", "gclk";
+ status = "okay";
+ };
+
+ flx1: flexcom@e181c000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xe181c000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe181c000 0x800>;
+ status = "disabled";
+
+ i2c1: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+ };
+ };
+
+ uart0: serial@e1824200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xe1824200 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ gmac0: ethernet@e2800000 {
+ compatible = "cdns,sama7g5-gem";
+ reg = <0xe2800000 0x4000>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
+ clock-names = "hclk", "pclk", "tx_clk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
+ assigned-clock-rates = <125000000>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@e2804000 {
+ compatible = "cdns,sama7g5-emac";
+ reg = <0xe2804000 0x1000>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
+ clock-names = "pclk", "hclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/sama7g5ek-u-boot.dtsi b/arch/arm/dts/sama7g5ek-u-boot.dtsi
new file mode 100644
index 0000000000..5e1a0d53a5
--- /dev/null
+++ b/arch/arm/dts/sama7g5ek-u-boot.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sama7g5ek-u-boot.dts - Device Tree file for SAMA7G5 SoC u-boot properties.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Eugen Hristev <eugen.hristev@microchip.com>
+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
+ *
+ */
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ };
+
+ ahb {
+ u-boot,dm-pre-reloc;
+
+ apb {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&main_rc {
+ u-boot,dm-pre-reloc;
+};
+
+&main_xtal {
+ u-boot,dm-pre-reloc;
+};
+
+&pioA {
+ u-boot,dm-pre-reloc;
+
+ pinctrl {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&pinctrl_flx3_default {
+ u-boot,dm-pre-reloc;
+};
+
+&pit64b0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pmc {
+ u-boot,dm-pre-reloc;
+};
+
+&slow_rc_osc {
+ u-boot,dm-pre-reloc;
+};
+
+&slow_xtal {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/sama7g5ek.dts
new file mode 100644
index 0000000000..ff9c9eb45c
--- /dev/null
+++ b/arch/arm/dts/sama7g5ek.dts
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * sama7g5ek.dts - Device Tree file for SAMA7G5 EK
+ * SAMA7G5 Evaluation Kit
+ *
+ * Copyright (c) 2020, Microchip Technology Inc.
+ * 2020, Eugen Hristev <eugen.hristev@microchip.com>
+ * 2020, Claudiu Beznea <claudiu.beznea@microchip.com>
+ */
+/dts-v1/;
+#include "sama7g5.dtsi"
+#include "sama7g5-pinfunc.h"
+
+/ {
+ model = "Microchip SAMA7G5 Evaluation Kit";
+ compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal: main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ ahb {
+
+ apb {
+ sdmmc0: sdio-host@e1204000 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_cmd_data_default
+ &pinctrl_sdmmc0_ck_rstn_ds_cd_default>;
+ status = "okay";
+ };
+
+ sdmmc1: sdio-host@e1208000 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default
+ &pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>;
+ status = "okay";
+ };
+
+ uart0: serial@e1824200 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ status = "okay";
+ };
+ };
+ };
+};
+
+&flx1 {
+ atmel,flexcom-mode = <3>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx1_default>;
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "microchip,24aa02e48";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "microchip,24aa02e48";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+};
+
+&gmac0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txc_default>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ ethernet-phy@7 {
+ reg = <0x7>;
+ };
+};
+
+&gmac1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gmac1_default>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ ethernet-phy@0 {
+ reg = <0x0>;
+ };
+};
+
+&pinctrl {
+ pinctrl_flx1_default: flx1_default {
+ pinmux = <PIN_PC9__FLEXCOM1_IO0>,
+ <PIN_PC10__FLEXCOM1_IO1>;
+ bias-disable;
+ };
+
+ pinctrl_flx3_default: flx3_default {
+ pinmux = <PIN_PD16__FLEXCOM3_IO0>,
+ <PIN_PD17__FLEXCOM3_IO1>;
+ bias-disable;
+ };
+
+ pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA3__SDMMC0_DAT0>,
+ <PIN_PA4__SDMMC0_DAT1>,
+ <PIN_PA5__SDMMC0_DAT2>,
+ <PIN_PA6__SDMMC0_DAT3>,
+ <PIN_PA7__SDMMC0_DAT4>,
+ <PIN_PA8__SDMMC0_DAT5>,
+ <PIN_PA9__SDMMC0_DAT6>,
+ <PIN_PA10__SDMMC0_DAT7>;
+ bias-pull-up;
+ };
+
+ pinctrl_sdmmc0_ck_rstn_ds_cd_default: sdmmc0_ck_rstn_ds_cd_default {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA2__SDMMC0_RSTN>,
+ <PIN_PA11__SDMMC0_DS>,
+ <PIN_PA14__SDMMC0_CD>;
+ bias-pull-up;
+ };
+
+ pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default {
+ pinmux = <PIN_PB29__SDMMC1_CMD>,
+ <PIN_PB31__SDMMC1_DAT0>,
+ <PIN_PC0__SDMMC1_DAT1>,
+ <PIN_PC1__SDMMC1_DAT2>,
+ <PIN_PC2__SDMMC1_DAT3>;
+ bias-pull-up;
+ };
+
+ pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default {
+ pinmux = <PIN_PB30__SDMMC1_CK>,
+ <PIN_PB28__SDMMC1_RSTN>,
+ <PIN_PC5__SDMMC1_1V8SEL>,
+ <PIN_PC4__SDMMC1_CD>;
+ bias-pull-up;
+ };
+
+ pinctrl_gmac0_default: gmac0_default {
+ pinmux = <PIN_PA16__G0_TX0>,
+ <PIN_PA17__G0_TX1>,
+ <PIN_PA26__G0_TX2>,
+ <PIN_PA27__G0_TX3>,
+ <PIN_PA19__G0_RX0>,
+ <PIN_PA20__G0_RX1>,
+ <PIN_PA28__G0_RX2>,
+ <PIN_PA29__G0_RX3>,
+ <PIN_PA15__G0_TXEN>,
+ <PIN_PA30__G0_RXCK>,
+ <PIN_PA18__G0_RXDV>,
+ <PIN_PA22__G0_MDC>,
+ <PIN_PA23__G0_MDIO>,
+ <PIN_PA25__G0_125CK>;
+ bias-disable;
+ };
+
+ pinctrl_gmac0_txc_default: gmac0_txc_default {
+ pinmux = <PIN_PA24__G0_TXCK>;
+ bias-pull-up;
+ };
+
+ pinctrl_gmac1_default: gmac1_default {
+ pinmux = <PIN_PD30__G1_TXCK>,
+ <PIN_PD22__G1_TX0>,
+ <PIN_PD23__G1_TX1>,
+ <PIN_PD21__G1_TXEN>,
+ <PIN_PD25__G1_RX0>,
+ <PIN_PD26__G1_RX1>,
+ <PIN_PD27__G1_RXER>,
+ <PIN_PD24__G1_RXDV>,
+ <PIN_PD28__G1_MDC>,
+ <PIN_PD29__G1_MDIO>;
+ bias-disable;
+ };
+};
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 54c144afd8..46d0f0666c 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -15,6 +15,19 @@
tst x0, x0 // this is "b #0x84" in ARM
b reset
.space 0x7c
+
+ .word 0xe28f0058 // add r0, pc, #88
+ .word 0xe59f1054 // ldr r1, [pc, #84]
+ .word 0xe0800001 // add r0, r0, r1
+ .word 0xe580d000 // str sp, [r0]
+ .word 0xe580e004 // str lr, [r0, #4]
+ .word 0xe10fe000 // mrs lr, CPSR
+ .word 0xe580e008 // str lr, [r0, #8]
+ .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0}
+ .word 0xe580e00c // str lr, [r0, #12]
+ .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0}
+ .word 0xe580e010 // str lr, [r0, #16]
+
.word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0
.word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE
.word 0xe5810000 // str r0, [r1]
@@ -36,6 +49,7 @@
#else
.word CONFIG_SYS_TEXT_BASE
#endif
+ .word fel_stash - .
#else
/* normal execution */
b reset
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index 8c916e8c75..58cdf806d9 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -7,19 +7,7 @@
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
-#define BOOT0_MAGIC "eGON.BT0"
-#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
-#define SPL_MAJOR_BITS 3
-#define SPL_MINOR_BITS 5
-#define SPL_VERSION(maj, min) \
- ((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \
- ((min) & ((1U << SPL_MINOR_BITS) - 1)))
-
-#define SPL_HEADER_VERSION SPL_VERSION(0, 2)
-
-#define SPL_ENV_HEADER_VERSION SPL_VERSION(0, 1)
-#define SPL_DT_HEADER_VERSION SPL_VERSION(0, 2)
-#define SPL_DRAM_HEADER_VERSION SPL_VERSION(0, 3)
+#include <sunxi_image.h>
#define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS
@@ -31,59 +19,7 @@
#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10
#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12
-/* boot head definition from sun4i boot code */
-struct boot_file_head {
- uint32_t b_instruction; /* one intruction jumping to real code */
- uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
- uint32_t check_sum; /* generated by PC */
- uint32_t length; /* generated by PC */
- /*
- * We use a simplified header, only filling in what is needed
- * by the boot ROM. To be compatible with Allwinner tools we
- * would need to implement the proper fields here instead of
- * padding.
- *
- * Actually we want the ability to recognize our "sunxi" variant
- * of the SPL. To do so, let's place a special signature into the
- * "pub_head_size" field. We can reasonably expect Allwinner's
- * boot0 to always have the upper 16 bits of this set to 0 (after
- * all the value shouldn't be larger than the limit imposed by
- * SRAM size).
- * If the signature is present (at 0x14), then we know it's safe
- * to use the remaining 8 bytes (at 0x18) for our own purposes.
- * (E.g. sunxi-tools "fel" utility can pass information there.)
- */
- union {
- uint32_t pub_head_size;
- uint8_t spl_signature[4];
- };
- uint32_t fel_script_address; /* since v0.1, set by sunxi-fel */
- /*
- * If the fel_uEnv_length member below is set to a non-zero value,
- * it specifies the size (byte count) of data at fel_script_address.
- * At the same time this indicates that the data is in uEnv.txt
- * compatible format, ready to be imported via "env import -t".
- */
- uint32_t fel_uEnv_length; /* since v0.1, set by sunxi-fel */
- /*
- * Offset of an ASCIIZ string (relative to the SPL header), which
- * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE).
- * This is optional and may be set to NULL. Is intended to be used
- * by flash programming tools for providing nice informative messages
- * to the users.
- */
- uint32_t dt_name_offset; /* since v0.2, set by mksunxiboot */
- uint32_t dram_size; /* in MiB, since v0.3, set by SPL */
- uint32_t boot_media; /* written here by the boot ROM */
- /* A padding area (may be used for storing text strings) */
- uint32_t string_pool[13]; /* since v0.2, filled by mksunxiboot */
- /* The header must be a multiple of 32 bytes (for VBAR alignment) */
-};
-
-/* Compile time check to assure proper alignment of structure */
-typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)];
-
-#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
+#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
uint32_t sunxi_get_boot_device(void);
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index be1415f909..c78a308f48 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -265,6 +265,13 @@ config TARGET_CORVUS
select SUPPORT_SPL
imply CMD_DM
+config TARGET_SAMA7G5EK
+ bool "SAMA7G5 EK board"
+ select SAMA7G5
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+
+
config TARGET_TAURUS
bool "Support taurus"
select AT91SAM9G20
@@ -327,6 +334,7 @@ source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sam9x60ek/Kconfig"
+source "board/atmel/sama7g5ek/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 49ef217f08..11e6445192 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1016,4 +1016,15 @@ config PINEPHONE_DT_SELECTION
Enable this option to automatically select the device tree for the
correct PinePhone hardware revision during boot.
+config BLUETOOTH_DT_DEVICE_FIXUP
+ string "Fixup the Bluetooth controller address"
+ default ""
+ help
+ This option specifies the DT compatible name of the Bluetooth
+ controller for which to set the "local-bd-address" property.
+ Set this option if your device ships with the Bluetooth controller
+ default address.
+ The used address is "bdaddr" if set, and "ethaddr" with the LSB
+ flipped elsewise.
+
endif
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 9e34da4747..32ec0bc4cd 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -37,9 +37,9 @@
static void mctl_sys_init(struct dram_para *para);
static void mctl_com_init(struct dram_para *para);
-static void mctl_channel_init(struct dram_para *para);
+static bool mctl_channel_init(struct dram_para *para);
-static void mctl_core_init(struct dram_para *para)
+static bool mctl_core_init(struct dram_para *para)
{
mctl_sys_init(para);
mctl_com_init(para);
@@ -51,7 +51,7 @@ static void mctl_core_init(struct dram_para *para)
default:
panic("Unsupported DRAM type!");
};
- mctl_channel_init(para);
+ return mctl_channel_init(para);
}
/* PHY initialisation */
@@ -411,7 +411,7 @@ static void mctl_bit_delay_set(struct dram_para *para)
}
}
-static void mctl_channel_init(struct dram_para *para)
+static bool mctl_channel_init(struct dram_para *para)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -528,46 +528,15 @@ static void mctl_channel_init(struct dram_para *para)
clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
udelay(10);
- if (readl(&mctl_phy->pgsr[0]) & 0x400000)
- {
- /* Check for single rank and optionally half DQ. */
- if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
- para->ranks = 1;
-
- if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
- (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
- para->bus_full_width = 0;
-
- /* Restart DRAM initialization from scratch. */
- mctl_core_init(para);
- return;
- }
-
- /*
- * Check for dual rank and half DQ. NOTE: This combination
- * is highly unlikely and was not tested. Condition is the
- * same as in libdram, though.
- */
- if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
- (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
- para->bus_full_width = 0;
-
- /* Restart DRAM initialization from scratch. */
- mctl_core_init(para);
- return;
- }
-
- panic("This DRAM setup is currently not supported.\n");
- }
-
if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
/* Oops! There's something wrong! */
debug("PLL = %x\n", readl(0x3001010));
debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
for (i = 0; i < 4; i++)
debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
- panic("Error while initializing DRAM PHY!\n");
+ debug("Error while initializing DRAM PHY!\n");
+
+ return false;
}
if (sunxi_dram_is_lpddr(para->type))
@@ -582,13 +551,59 @@ static void mctl_channel_init(struct dram_para *para)
writel(0xffffffff, &mctl_com->maer0);
writel(0x7ff, &mctl_com->maer1);
writel(0xffff, &mctl_com->maer2);
+
+ return true;
+}
+
+static void mctl_auto_detect_rank_width(struct dram_para *para)
+{
+ /* this is minimum size that it's supported */
+ para->cols = 8;
+ para->rows = 13;
+
+ /*
+ * Previous versions of this driver tried to auto detect the rank
+ * and width by looking at controller registers. However this proved
+ * to be not reliable, so this approach here is the more robust
+ * solution. Check the git history for details.
+ *
+ * Strategy here is to test most demanding combination first and least
+ * demanding last, otherwise HW might not be fully utilized. For
+ * example, half bus width and rank = 1 combination would also work
+ * on HW with full bus width and rank = 2, but only 1/4 RAM would be
+ * visible.
+ */
+
+ debug("testing 32-bit width, rank = 2\n");
+ para->bus_full_width = 1;
+ para->ranks = 2;
+ if (mctl_core_init(para))
+ return;
+
+ debug("testing 32-bit width, rank = 1\n");
+ para->bus_full_width = 1;
+ para->ranks = 1;
+ if (mctl_core_init(para))
+ return;
+
+ debug("testing 16-bit width, rank = 2\n");
+ para->bus_full_width = 0;
+ para->ranks = 2;
+ if (mctl_core_init(para))
+ return;
+
+ debug("testing 16-bit width, rank = 1\n");
+ para->bus_full_width = 0;
+ para->ranks = 1;
+ if (mctl_core_init(para))
+ return;
+
+ panic("This DRAM setup is currently not supported.\n");
}
static void mctl_auto_detect_dram_size(struct dram_para *para)
{
/* TODO: non-(LP)DDR3 */
- /* Detect rank number and half DQ by the code in mctl_channel_init. */
- mctl_core_init(para);
/* detect row address bits */
para->cols = 8;
@@ -652,10 +667,6 @@ unsigned long sunxi_dram_init(void)
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
- .ranks = 2,
- .cols = 11,
- .rows = 14,
- .bus_full_width = 1,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
.type = SUNXI_DRAM_TYPE_LPDDR3,
.dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
@@ -673,6 +684,7 @@ unsigned long sunxi_dram_init(void)
setbits_le32(0x7010310, BIT(8));
clrbits_le32(0x7010318, 0x3f);
+ mctl_auto_detect_rank_width(&para);
mctl_auto_detect_dram_size(&para);
mctl_core_init(&para);
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-01 09:33:12 +0000