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-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/mp.c8
-rw-r--r--arch/arm/cpu/armv8/zynqmp/mp.c8
-rw-r--r--arch/arm/dts/.gitignore1
-rw-r--r--arch/arm/dts/dragonboard410c-uboot.dtsi16
-rw-r--r--arch/arm/include/asm/arch-meson/clock.h117
-rw-r--r--arch/arm/include/asm/arch-meson/gx.h10
-rw-r--r--arch/arm/lib/image.c5
-rw-r--r--arch/arm/lib/vectors.S2
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h14
-rw-r--r--arch/arm/mach-imx/mx6/mp.c8
-rw-r--r--arch/arm/mach-meson/Kconfig2
-rw-r--r--arch/arm/mach-meson/eth.c3
-rw-r--r--arch/arm/mach-omap2/omap3/clock.c10
-rw-r--r--arch/arm/mach-sunxi/board.c3
14 files changed, 160 insertions, 47 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index dd89d0a83f..7627fd13e7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -191,14 +191,14 @@ int is_core_online(u64 cpu_id)
return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
}
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
puts("Feature is not implemented.\n");
return 0;
}
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
puts("Feature is not implemented.\n");
@@ -231,7 +231,7 @@ static int core_to_pos(int nr)
return i;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
u64 *table;
int pos;
@@ -257,7 +257,7 @@ int cpu_status(int nr)
return 0;
}
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
{
u64 boot_addr;
u64 *table = (u64 *)get_spin_tbl_addr();
diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c
index 7e270a7dc2..2a71870ae7 100644
--- a/arch/arm/cpu/armv8/zynqmp/mp.c
+++ b/arch/arm/cpu/armv8/zynqmp/mp.c
@@ -45,7 +45,7 @@ int is_core_valid(unsigned int core)
return 0;
}
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
puts("Feature is not implemented.\n");
return 0;
@@ -131,7 +131,7 @@ static void enable_clock_r5(void)
udelay(0x500);
}
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
u32 val = readl(&crfapb_base->rst_fpd_apu);
@@ -144,7 +144,7 @@ int cpu_disable(int nr)
return 0;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
@@ -220,7 +220,7 @@ void initialize_tcm(bool mode)
}
}
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
diff --git a/arch/arm/dts/.gitignore b/arch/arm/dts/.gitignore
deleted file mode 100644
index b60ed208c7..0000000000
--- a/arch/arm/dts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-*.dtb
diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi
index b968f5eb68..3a1ea13ee5 100644
--- a/arch/arm/dts/dragonboard410c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard410c-uboot.dtsi
@@ -6,10 +6,6 @@
*/
/ {
- config {
- u-boot,mmc-env-partition = "boot";
- };
-
soc {
u-boot,dm-pre-reloc;
@@ -21,14 +17,14 @@
};
};
- qcom,gcc@1800000 {
- u-boot,dm-pre-reloc;
- };
+ qcom,gcc@1800000 {
+ u-boot,dm-pre-reloc;
+ };
- serial@78b0000 {
- u-boot,dm-pre-reloc;
+ serial@78b0000 {
+ u-boot,dm-pre-reloc;
+ };
};
- };
};
diff --git a/arch/arm/include/asm/arch-meson/clock.h b/arch/arm/include/asm/arch-meson/clock.h
new file mode 100644
index 0000000000..c0ff00fc9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - AmLogic, Inc.
+ * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ */
+#ifndef _ARCH_MESON_CLOCK_H_
+#define _ARCH_MESON_CLOCK_H_
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet are listed in comment blocks below.
+ * Those offsets must be multiplied by 4 before adding them to the base address
+ * to get the right value
+ */
+#define SCR 0x2C /* 0x0b offset in data sheet */
+#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
+
+#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
+#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
+#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
+#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
+#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
+#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
+
+#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
+#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
+
+#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */
+#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */
+#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */
+#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
+#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
+
+#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
+#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
+#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
+#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
+#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
+#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
+#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */
+#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
+
+#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
+#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
+#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
+#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
+#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
+#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
+#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */
+#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
+#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */
+
+#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */
+#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */
+#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */
+#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */
+#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */
+#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */
+#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */
+
+#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */
+#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
+#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
+#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
+#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
+
+#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
+#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
+#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */
+
+#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
+#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
+#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
+#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
+#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
+#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
+#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */
+#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */
+#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
+#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
+
+#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */
+#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */
+#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
+#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
+
+#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
+#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */
+#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */
+#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */
+#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */
+#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */
+#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */
+#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
+#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
+#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
+#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
+#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
+#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
+#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */
+#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */
+
+#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */
+#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */
+#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */
+#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */
+
+#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */
+#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
+#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
+
+ulong meson_measure_clk_rate(unsigned int clk);
+
+#endif
diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
index 03fb6b03de..4bc9475d35 100644
--- a/arch/arm/include/asm/arch-meson/gx.h
+++ b/arch/arm/include/asm/arch-meson/gx.h
@@ -56,14 +56,4 @@
/* Ethernet memory power domain */
#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
-/* Clock gates */
-#define GX_GCLK_MPEG_0 GX_HIU_ADDR(0x50)
-#define GX_GCLK_MPEG_1 GX_HIU_ADDR(0x51)
-#define GX_GCLK_MPEG_2 GX_HIU_ADDR(0x52)
-#define GX_GCLK_MPEG_OTHER GX_HIU_ADDR(0x53)
-#define GX_GCLK_MPEG_AO GX_HIU_ADDR(0x54)
-
-#define GX_GCLK_MPEG_0_I2C BIT(9)
-#define GX_GCLK_MPEG_1_ETH BIT(3)
-
#endif /* __GX_H__ */
diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c
index 1a04e2b875..699bf44e70 100644
--- a/arch/arm/lib/image.c
+++ b/arch/arm/lib/image.c
@@ -26,7 +26,8 @@ struct Image_header {
uint32_t res5;
};
-int booti_setup(ulong image, ulong *relocated_addr, ulong *size)
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
+ bool force_reloc)
{
struct Image_header *ih;
uint64_t dst;
@@ -63,7 +64,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size)
* images->ep. Otherwise, relocate the image to the base of RAM
* since memory below it is not accessible via the linear mapping.
*/
- if (le64_to_cpu(ih->flags) & BIT(3))
+ if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3)))
dst = image - text_offset;
else
dst = gd->bd->bi_dram[0].start;
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 79afc27e84..d629cb1dc2 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -133,7 +133,7 @@ not_used:
irq:
fiq:
1:
- bl 1b /* hang and never return */
+ b 1b /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index f1d4d9e9e0..d4b25c3d60 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -39,7 +39,7 @@ struct davinci_gpio_bank {
unsigned int irq_num;
unsigned int irq_mask;
unsigned long *in_use;
- unsigned long base;
+ struct davinci_gpio *base;
};
#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
@@ -48,7 +48,9 @@ struct davinci_gpio_bank {
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
+#ifndef CONFIG_DM_GPIO
#define gpio_status() gpio_info()
+#endif
#define GPIO_NAME_SIZE 20
#if defined(CONFIG_SOC_DM644X)
/* GPIO0 to GPIO53, omit the V3.3 volts one */
@@ -63,4 +65,14 @@ struct davinci_gpio_bank {
void gpio_info(void);
+#ifdef CONFIG_DM_GPIO
+
+/* Information about a GPIO bank */
+struct davinci_gpio_platdata {
+ int bank_index;
+ ulong base; /* address of registers in physical memory */
+ const char *port_name;
+};
+#endif
+
#endif
diff --git a/arch/arm/mach-imx/mx6/mp.c b/arch/arm/mach-imx/mx6/mp.c
index c3806dca3a..eda168d867 100644
--- a/arch/arm/mach-imx/mx6/mp.c
+++ b/arch/arm/mach-imx/mx6/mp.c
@@ -29,20 +29,20 @@ static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
SRC_SCR_CORE_3_ENABLE_MASK
};
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
/* Software reset of the CPU N */
src->scr |= cpu_reset_mask[nr];
return 0;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
return 0;
}
-int cpu_release(int nr, int argc, char *const argv[])
+int cpu_release(u32 nr, int argc, char *const argv[])
{
uint32_t boot_addr;
@@ -78,7 +78,7 @@ int is_core_valid(unsigned int core)
return 1;
}
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
/* Disable the CPU N */
src->scr &= ~cpu_ctrl_mask[nr];
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 0350787daa..9a06ccc861 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -3,6 +3,7 @@ if ARCH_MESON
config MESON_GXBB
bool "Support Meson GXBaby"
select ARM64
+ select CLK
select DM
select DM_SERIAL
help
@@ -12,6 +13,7 @@ config MESON_GXBB
config MESON_GXL
bool "Support Meson GXL"
select ARM64
+ select CLK
select DM
select DM_SERIAL
help
diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c
index 061f19a0e3..8b28bc8531 100644
--- a/arch/arm/mach-meson/eth.c
+++ b/arch/arm/mach-meson/eth.c
@@ -48,7 +48,6 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
return;
}
- /* Enable power and clock gate */
- setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH);
+ /* Enable power gate */
clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
}
diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c
index b9d92c62b1..9a03bfa9d3 100644
--- a/arch/arm/mach-omap2/omap3/clock.c
+++ b/arch/arm/mach-omap2/omap3/clock.c
@@ -750,23 +750,23 @@ void per_clocks_enable(void)
setbits_le32(&prcm_base->iclken_per, 0x00000800);
#endif
-#ifdef CONFIG_OMAP3_GPIO_2
+#if (CONFIG_IS_ENABLED(OMAP3_GPIO_2) || CONFIG_IS_ENABLED(CMD_GPIO))
setbits_le32(&prcm_base->fclken_per, 0x00002000);
setbits_le32(&prcm_base->iclken_per, 0x00002000);
#endif
-#ifdef CONFIG_OMAP3_GPIO_3
+#if (CONFIG_IS_ENABLED(OMAP3_GPIO_3) || CONFIG_IS_ENABLED(CMD_GPIO))
setbits_le32(&prcm_base->fclken_per, 0x00004000);
setbits_le32(&prcm_base->iclken_per, 0x00004000);
#endif
-#ifdef CONFIG_OMAP3_GPIO_4
+#if (CONFIG_IS_ENABLED(OMAP3_GPIO_4) || CONFIG_IS_ENABLED(CMD_GPIO))
setbits_le32(&prcm_base->fclken_per, 0x00008000);
setbits_le32(&prcm_base->iclken_per, 0x00008000);
#endif
-#ifdef CONFIG_OMAP3_GPIO_5
+#if (CONFIG_IS_ENABLED(OMAP3_GPIO_5) || CONFIG_IS_ENABLED(CMD_GPIO))
setbits_le32(&prcm_base->fclken_per, 0x00010000);
setbits_le32(&prcm_base->iclken_per, 0x00010000);
#endif
-#ifdef CONFIG_OMAP3_GPIO_6
+#if (CONFIG_IS_ENABLED(OMAP3_GPIO_6) || CONFIG_IS_ENABLED(CMD_GPIO))
setbits_le32(&prcm_base->fclken_per, 0x00020000);
setbits_le32(&prcm_base->iclken_per, 0x00020000);
#endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 7ac8360c01..58fef05bd7 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -207,9 +207,6 @@ void s_init(void)
eth_init_board();
}
-#ifdef CONFIG_SPL_BUILD
-#endif
-
/* The sunxi internal brom will try to loader external bootloader
* from mmc0, nand flash, mmc2.
*/
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 22:16:28 +0000