diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/Kconfig | 52 | ||||
| -rw-r--r-- | arch/arm/dts/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/dts/px30-firefly-u-boot.dtsi | 84 | ||||
| -rw-r--r-- | arch/arm/dts/px30-firefly.dts | 531 | ||||
| -rw-r--r-- | arch/arm/dts/rk3328-u-boot.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/Kconfig | 2 | ||||
| -rwxr-xr-x | arch/arm/mach-rockchip/fit_spl_optee.sh | 12 | ||||
| -rwxr-xr-x | arch/arm/mach-rockchip/make_fit_atf.py | 2 |
8 files changed, 660 insertions, 32 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9dab073ea..36c9c2fecd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -17,7 +17,7 @@ config POSITION_INDEPENDENT be loaded to and run from that address. This option lifts that restriction, thus allowing the code to be loaded to and executed from almost any address. This logic relies on the relocation - information that is embedded into the binary to support U-Boot + information that is embedded in the binary to support U-Boot relocating itself to the top-of-RAM later during execution. config INIT_SP_RELATIVE @@ -26,7 +26,7 @@ config INIT_SP_RELATIVE U-Boot typically uses a hard-coded value for the stack pointer before relocation. Enable this option to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses - into U-Boot, so that can be loaded and executed at arbitrary + into U-Boot, so that it can be loaded and executed at arbitrary addresses and thus avoid using arbitrary addresses at runtime. If this option is enabled, the early stack pointer is set to @@ -57,7 +57,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE hex help The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the - TEXT_OFFSET value written in to the Linux kernel image header. + TEXT_OFFSET value written to the Linux kernel image header. endif endif @@ -121,7 +121,7 @@ config SYS_ARM_MMU select SYS_ARM_CACHE_CP15 help Select if you want MMU-based virtualised addressing space - support by paged memory management. + support via paged memory management. config SYS_ARM_MPU bool 'Use the ARM v7 PMSA Compliant MPU' @@ -136,8 +136,8 @@ config SYS_ARM_MPU # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in # the Linux kernel. Do not set these options unless they apply! Also note that -# the following can be machine specific errata. These do have ability to -# provide rudimentary version and machine specific checks, but expect no +# the following can be machine-specific errata. These do have ability to +# provide rudimentary version and machine-specific checks, but expect no # product checks: # CONFIG_ARM_ERRATA_430973 # CONFIG_ARM_ERRATA_454179 @@ -332,7 +332,7 @@ config SYS_CACHELINE_SIZE config ARCH_CPU_INIT bool "Enable ARCH_CPU_INIT" help - Some architectures require a call to arch_cpu_init() + Some architectures require a call to arch_cpu_init(). Say Y here to enable it config SYS_ARCH_TIMER @@ -342,7 +342,7 @@ config SYS_ARCH_TIMER help The ARM Generic Timer (aka arch-timer) provides an architected interface to a timer source on an SoC. - It is mandantory for ARMv8 implementation and widely available + It is mandatory for ARMv8 implementation and widely available on ARMv7 systems. config ARM_SMCCC @@ -385,7 +385,7 @@ config TPL_SYS_THUMB_BUILD default y if SYS_THUMB_BUILD depends on TPL && !ARM64 help - Use this flag to build SPL using the Thumb instruction set for + Use this flag to build TPL using the Thumb instruction set for ARM architectures. Thumb instruction set provides better code density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC. @@ -394,7 +394,7 @@ config TPL_SYS_THUMB_BUILD config SYS_L2CACHE_OFF bool "L2cache off" help - If SoC does not support L2CACHE or one do not want to enable + If SoC does not support L2CACHE or one does not want to enable L2CACHE, choose this option. config ENABLE_ARM_SOC_BOOT0_HOOK @@ -414,7 +414,7 @@ config USE_ARCH_MEMCPY depends on !ARM64 help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SPL_USE_ARCH_MEMCPY @@ -423,7 +423,7 @@ config SPL_USE_ARCH_MEMCPY depends on !ARM64 && SPL help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config TPL_USE_ARCH_MEMCPY @@ -432,7 +432,7 @@ config TPL_USE_ARCH_MEMCPY depends on !ARM64 && TPL help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config USE_ARCH_MEMSET @@ -441,7 +441,7 @@ config USE_ARCH_MEMSET depends on !ARM64 help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SPL_USE_ARCH_MEMSET @@ -450,7 +450,7 @@ config SPL_USE_ARCH_MEMSET depends on !ARM64 && SPL help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config TPL_USE_ARCH_MEMSET @@ -459,7 +459,7 @@ config TPL_USE_ARCH_MEMSET depends on !ARM64 && TPL help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SET_STACK_SIZE @@ -467,14 +467,14 @@ config SET_STACK_SIZE default y if ARCH_VERSAL || ARCH_ZYNQMP help This will enable an option to set max stack size that can be - used by u-boot. + used by U-Boot. config STACK_SIZE - hex "Define max stack size that can be used by u-boot" + hex "Define max stack size that can be used by U-Boot" depends on SET_STACK_SIZE default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP help - Defines Max stack size that can be used by u-boot so that the + Define Max stack size that can be used by U-Boot so that the initrd_high will be calculated as base stack pointer minus this stack size. @@ -689,7 +689,7 @@ config TARGET_BCMNS2 help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking - applications + applications. config ARCH_EXYNOS bool "Samsung EXYNOS" @@ -1101,8 +1101,8 @@ config TARGET_LS2080A_EMU select ARMV8_MULTIENTRY select FSL_DDR_SYNC_REFRESH help - Support for Freescale LS2080A_EMU platform - The LS2080A Development System (EMULATOR) is a pre silicon + Support for Freescale LS2080A_EMU platform. + The LS2080A Development System (EMULATOR) is a pre-silicon development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1114,7 +1114,7 @@ config TARGET_LS2080A_SIMU select ARMV8_MULTIENTRY select BOARD_LATE_INIT help - Support for Freescale LS2080A_SIMU platform + Support for Freescale LS2080A_SIMU platform. The LS2080A Development System (QDS) is a pre silicon development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1130,7 +1130,7 @@ config TARGET_LS1088AQDS select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT help - Support for NXP LS1088AQDS platform + Support for NXP LS1088AQDS platform. The LS1088A Development System (QDS) is a high-performance development platform that supports the QorIQ LS1088A Layerscape Architecture processor. @@ -1149,7 +1149,7 @@ config TARGET_LS2080AQDS select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL help - Support for Freescale LS2080AQDS platform + Support for Freescale LS2080AQDS platform. The LS2080A Development System (QDS) is a high-performance development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1649,7 +1649,7 @@ config TFABOOT default n help Enabling this will make a U-Boot binary that is capable of being - booted via TF-A. + booted via TF-A (Trusted Firmware for Cortex-A). config TI_SECURE_DEVICE bool "HS Device Type Support" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 88c750a646..0127a91a82 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -68,7 +68,8 @@ dtb-$(CONFIG_ARCH_OWL) += \ bubblegum_96.dtb dtb-$(CONFIG_ROCKCHIP_PX30) += \ - px30-evb.dtb + px30-evb.dtb \ + px30-firefly.dtb dtb-$(CONFIG_ROCKCHIP_RK3036) += \ rk3036-sdk.dtb diff --git a/arch/arm/dts/px30-firefly-u-boot.dtsi b/arch/arm/dts/px30-firefly-u-boot.dtsi new file mode 100644 index 0000000000..bb782b4e2d --- /dev/null +++ b/arch/arm/dts/px30-firefly-u-boot.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&uart5 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&emmc { + u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&xin24m { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&pmucru { + u-boot,dm-pre-reloc; +}; + +&saradc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/px30-firefly.dts b/arch/arm/dts/px30-firefly.dts new file mode 100644 index 0000000000..c0a8e3009a --- /dev/null +++ b/arch/arm/dts/px30-firefly.dts @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "px30.dtsi" + +/ { + model = "Firefly Core-PX30-JD4"; + compatible = "rockchip,px30-firefly", "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + esc-key { + label = "esc"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1310000>; + }; + + home-key { + label = "home"; + linux,code = <KEY_HOME>; + press-threshold-microvolt = <624000>; + }; + + menu-key { + label = "menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + label = "volume up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + power-supply = <&vcc3v3_lcd>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible = "sitronix,st7703"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + vci-supply = <&vcc3v3_lcd>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v0>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_rmii>; + snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <0>; + clock-output-names = "xin32k"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: vcc_rmii: DCDC_REG4 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-name = "vcc2v8_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v5_dvp: LDO_REG9 { + regulator-name = "vcc1v5_dvp"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-name = "vcc3v3_lcd"; + regulator-boot-on; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vccio_sdio>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; + vccio6-supply = <&vccio_flash>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <800>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index ffbd657e31..6d5b3ec06e 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -51,8 +51,14 @@ &emmc { u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ + u-boot,spl-fifo-mode; }; &sdmmc { u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ + u-boot,spl-fifo-mode; }; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d8d68ba447..b689a420bd 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -306,7 +306,7 @@ config SPL_ROCKCHIP_COMMON_BOARD no TPL for the board. config TPL_ROCKCHIP_COMMON_BOARD - bool "" + bool "Rockchip TPL common board file" depends on TPL help Rockchip SoCs have similar boot process, prefer to use TPL for DRAM diff --git a/arch/arm/mach-rockchip/fit_spl_optee.sh b/arch/arm/mach-rockchip/fit_spl_optee.sh index 89ef04312c..4118472d9f 100755 --- a/arch/arm/mach-rockchip/fit_spl_optee.sh +++ b/arch/arm/mach-rockchip/fit_spl_optee.sh @@ -17,6 +17,12 @@ if [ ! -f $TEE ]; then fi dtname=$1 +text_base=`sed -n "/SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" .config \ + |tr -d '\r'` +dram_base=`sed -n "/SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" \ + include/autoconf.mk|tr -d '\r'` +tee_base=`echo "obase=16;$(($dram_base+0x8400000))"|bc` +tee_base='0x'$tee_base cat << __HEADER_EOF /* @@ -39,7 +45,7 @@ cat << __HEADER_EOF os = "U-Boot"; arch = "arm"; compression = "none"; - load = <0x61000000>; + load = <$text_base>; }; optee { description = "OP-TEE"; @@ -48,8 +54,8 @@ cat << __HEADER_EOF arch = "arm"; os = "tee"; compression = "none"; - load = <0x68400000>; - entry = <0x68400000>; + load = <$tee_base>; + entry = <$tee_base>; }; fdt { description = "$(basename $dtname .dtb)"; diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 3c045a5e17..c79317d6c5 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 """ # SPDX-License-Identifier: GPL-2.0+ # |