diff options
Diffstat (limited to 'arch/arm/mach-stm32mp')
| -rw-r--r-- | arch/arm/mach-stm32mp/Kconfig | 13 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/cpu.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/include/mach/gpio.h | 37 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/spl.c | 3 |
5 files changed, 20 insertions, 39 deletions
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 478fd2f17d..f538d7cb83 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -93,6 +93,19 @@ config SYS_TEXT_BASE config NR_DRAM_BANKS default 1 +config DDR_CACHEABLE_SIZE + hex "Size of the DDR marked cacheable in pre-reloc stage" + default 0x10000000 if TFABOOT + default 0x40000000 + help + Define the size of the DDR marked as cacheable in U-Boot + pre-reloc stage. + This option can be useful to avoid speculatif access + to secured area of DDR used by TF-A or OP-TEE before U-Boot + initialization. + The areas marked "no-map" in device tree should be located + before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 hex "Partition on MMC2 to use to load U-Boot from" depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index ec3355d816..a777827c55 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -768,9 +768,8 @@ static int init_device(struct stm32prog_data *data, part_found = true; } + /* no partition for this device */ if (!part_found) { - stm32prog_err("%s (0x%x): Invalid partition", - part->name, part->id); pr_debug("\n"); continue; } diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index f19e5c3f33..6785ab6b58 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -230,7 +230,8 @@ static void early_enable_caches(void) round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), DCACHE_DEFAULT_OPTION); else - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h index 5ca76d21ff..7a0f293519 100644 --- a/arch/arm/mach-stm32mp/include/mach/gpio.h +++ b/arch/arm/mach-stm32mp/include/mach/gpio.h @@ -8,39 +8,6 @@ #define _STM32_GPIO_H_ #include <asm/gpio.h> -#define STM32_GPIOS_PER_BANK 16 - -enum stm32_gpio_port { - STM32_GPIO_PORT_A = 0, - STM32_GPIO_PORT_B, - STM32_GPIO_PORT_C, - STM32_GPIO_PORT_D, - STM32_GPIO_PORT_E, - STM32_GPIO_PORT_F, - STM32_GPIO_PORT_G, - STM32_GPIO_PORT_H, - STM32_GPIO_PORT_I -}; - -enum stm32_gpio_pin { - STM32_GPIO_PIN_0 = 0, - STM32_GPIO_PIN_1, - STM32_GPIO_PIN_2, - STM32_GPIO_PIN_3, - STM32_GPIO_PIN_4, - STM32_GPIO_PIN_5, - STM32_GPIO_PIN_6, - STM32_GPIO_PIN_7, - STM32_GPIO_PIN_8, - STM32_GPIO_PIN_9, - STM32_GPIO_PIN_10, - STM32_GPIO_PIN_11, - STM32_GPIO_PIN_12, - STM32_GPIO_PIN_13, - STM32_GPIO_PIN_14, - STM32_GPIO_PIN_15 -}; - enum stm32_gpio_mode { STM32_GPIO_MODE_IN = 0, STM32_GPIO_MODE_OUT, @@ -86,8 +53,8 @@ enum stm32_gpio_af { }; struct stm32_gpio_dsc { - enum stm32_gpio_port port; - enum stm32_gpio_pin pin; + u8 port; + u8 pin; }; struct stm32_gpio_ctl { diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index e84bdad7bf..b679b0a645 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -138,7 +138,8 @@ void board_init_f(ulong dummy) * to avoid speculative access and issue in get_ram_size() */ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); } |