aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-socfpga
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r--arch/arm/mach-socfpga/clock_manager.c4
-rw-r--r--arch/arm/mach-socfpga/clock_manager_arria10.c9
-rw-r--r--arch/arm/mach-socfpga/clock_manager_gen5.c15
-rw-r--r--arch/arm/mach-socfpga/reset_manager_arria10.c36
4 files changed, 40 insertions, 24 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 6b76221025..43e72a8b55 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -37,8 +37,8 @@ void cm_wait_for_lock(u32 mask)
/* function to poll in the fsm busy bit */
int cm_wait_for_fsm(void)
{
- return wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat,
- CLKMGR_STAT_BUSY, false, 20000, false);
+ return wait_for_bit_le32(&clock_manager_base->stat,
+ CLKMGR_STAT_BUSY, false, 20000, false);
}
int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 482b8543f4..623a266f80 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
+#include <dm.h>
#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
}
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ *rate = cm_get_spi_controller_clk_hz();
+
+ return 0;
+}
+
void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 31fd51097a..3d048ba3e4 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
+#include <dm.h>
#include <asm/arch/clock_manager.h>
#include <wait_bit.h>
@@ -37,15 +38,13 @@ static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
int ret;
/* poll until phase is zero */
- ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
- false, 20000, false);
+ ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
if (ret)
return ret;
writel(value, reg_address);
- return wait_for_bit(__func__, (const u32 *)reg_address, mask,
- false, 20000, false);
+ return wait_for_bit_le32(reg_address, mask, false, 20000, false);
}
/*
@@ -509,6 +508,14 @@ unsigned int cm_get_spi_controller_clk_hz(void)
return clock;
}
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ *rate = cm_get_spi_controller_clk_hz();
+
+ return 0;
+}
+
void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index ae16897494..54f0ddb255 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -222,8 +222,8 @@ int socfpga_reset_deassert_bridges_handoff(void)
clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
/* Poll until all idleack to 0, timeout at 1000ms */
- return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc,
- false, 1000, false);
+ return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
+ false, 1000, false);
}
void socfpga_reset_assert_fpga_connected_peripherals(void)
@@ -343,26 +343,26 @@ int socfpga_bridges_reset(void)
writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
/* Poll until all idleack to 1 */
- ret = wait_for_bit(__func__, &sysmgr_regs->noc_idleack,
- ALT_SYSMGR_NOC_H2F_SET_MSK |
- ALT_SYSMGR_NOC_LWH2F_SET_MSK |
- ALT_SYSMGR_NOC_F2H_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
- true, 10000, false);
+ ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
+ ALT_SYSMGR_NOC_H2F_SET_MSK |
+ ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+ ALT_SYSMGR_NOC_F2H_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+ true, 10000, false);
if (ret)
return ret;
/* Poll until all idlestatus to 1 */
- ret = wait_for_bit(__func__, &sysmgr_regs->noc_idlestatus,
- ALT_SYSMGR_NOC_H2F_SET_MSK |
- ALT_SYSMGR_NOC_LWH2F_SET_MSK |
- ALT_SYSMGR_NOC_F2H_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
- ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
- true, 10000, false);
+ ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
+ ALT_SYSMGR_NOC_H2F_SET_MSK |
+ ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+ ALT_SYSMGR_NOC_F2H_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+ ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+ true, 10000, false);
if (ret)
return ret;