diff options
Diffstat (limited to 'arch/arm/mach-mvebu/include/mach/soc.h')
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 01577f469b..f666ee2424 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -76,7 +76,11 @@ #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) +#ifdef CONFIG_ARMADA_MSYS +#define MVEBU_DFX_BASE (MBUS_DFX_BASE) +#else #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000)) +#endif #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) #define MBUS_ERR_PROP_EN (1 << 8) @@ -96,9 +100,20 @@ #define SPI_PUP_EN BIT(5) #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) +#ifdef CONFIG_ARMADA_MSYS +#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4)) +#define NAND_ECC_DIVCKL_RATIO_OFFS 6 +#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) +#else #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4)) +#endif +#ifdef CONFIG_ARMADA_MSYS +#define NAND_ECC_DIVCKL_RATIO_OFFS 6 +#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) +#else #define NAND_ECC_DIVCKL_RATIO_OFFS 8 #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) +#endif #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK 0xFF000000 @@ -149,6 +164,22 @@ #define BOOT_FROM_SPI 0x32 #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 +#elif defined(CONFIG_ARMADA_MSYS) +/* SAR values for MSYS */ +#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) +#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) + +#define SAR_CPU_FREQ_OFFS 18 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 11 +#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 11 +#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_NAND 0x1 +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 #else /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) |