5 files changed, 30 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
index 6f540d23af..38b5012fce 100644
--- a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
+++ b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
@@ -31,7 +31,7 @@ static struct usba_ep_data usba_udc_ep[] = {
 	EP("ep5", 5, 1024, 3, 1, 1),
 	EP("ep6", 6, 1024, 3, 1, 1),
 };
-#elif defined(CONFIG_SAMA5D3)
+#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
 static struct usba_ep_data usba_udc_ep[] = {
 	EP("ep0", 0, 64, 1, 0, 0),
 	EP("ep1", 1, 1024, 3, 1, 0),
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 5e934da797..791551841c 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -97,8 +97,13 @@
 #define CONFIG_SYS_FSL_DDR_VER			FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+#define CONFIG_SYS_FSL_ERRATUM_A008378
 #else
 #error SoC not defined
 #endif
 
+#define FSL_IFC_COMPAT		"fsl,ifc"
+#define FSL_QSPI_COMPAT		"fsl,ls1-qspi"
+#define FSL_DSPI_COMPAT		"fsl,vf610-dspi"
+
 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h
new file mode 100644
index 0000000000..b7044362d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_LS102XA_GPIO_H_
+#define __ASM_ARCH_LS102XA_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 697d4ca489..f70d568d46 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -105,6 +105,8 @@ struct ccsr_gur {
 
 #define SCFG_ETSECDMAMCR_LE_BD_FR	0xf8001a0f
 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
+#define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
+#define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
 #define SCFG_QSPI_CLKSEL		0xc0100000
 
@@ -456,6 +458,8 @@ struct ccsr_ddr {
 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
 #define CCI400_CTRLORD_EN_BARRIER	0
 #define CCI400_SHAORD_NON_SHAREABLE	0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN	0x00000002
+#define CCI400_SNOOP_REQ_EN		0x00000001
 
 /* CCI-400 registers */
 struct ccsr_cci400 {
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index 2aede0c552..e2e0b7321a 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -21,6 +21,9 @@
 #define ZYNQ_I2C_BASEADDR1		0xE0005000
 #define ZYNQ_SPI_BASEADDR0		0xE0006000
 #define ZYNQ_SPI_BASEADDR1		0xE0007000
+#define ZYNQ_QSPI_BASEADDR		0xE000D000
+#define ZYNQ_SMC_BASEADDR		0xE000E000
+#define ZYNQ_NAND_BASEADDR		0xE1000000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
 #define ZYNQ_EFUSE_BASEADDR		0xF800D000
 #define ZYNQ_USB_BASEADDR0		0xE0002000
@@ -28,7 +31,9 @@
 
 /* Bootmode setting values */
 #define ZYNQ_BM_MASK		0x7
+#define ZYNQ_BM_QSPI		0x1
 #define ZYNQ_BM_NOR		0x2
+#define ZYNQ_BM_NAND		0x4
 #define ZYNQ_BM_SD		0x5
 #define ZYNQ_BM_JTAG		0x0