diff options
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-ep93xx/ep93xx.h | 85 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/clock.h | 23 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 65 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 116 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/spl.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/spl.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 24 | ||||
| -rw-r--r-- | arch/arm/include/asm/cache.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/config.h | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/io.h | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/proc-armv/system.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/semihosting.h | 21 | ||||
| -rw-r--r-- | arch/arm/include/asm/system.h | 2 |
17 files changed, 468 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h index 9e7f2f3480..330493b606 100644 --- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h +++ b/arch/arm/include/asm/arch-ep93xx/ep93xx.h @@ -1,6 +1,9 @@ /* * Cirrus Logic EP93xx register definitions. * + * Copyright (C) 2013 + * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru> + * * Copyright (C) 2009 * Matthias Kaehlcke <matthias@kaehlcke.net> * @@ -287,6 +290,20 @@ struct sdram_regs { #define SDRAM_DEVCFG_CASLAT_2 0x00010000 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 +#define SDRAM_OFF_GLCONFIG 0x0004 +#define SDRAM_OFF_REFRSHTIMR 0x0008 + +#define SDRAM_OFF_DEVCFG0 0x0010 +#define SDRAM_OFF_DEVCFG1 0x0014 +#define SDRAM_OFF_DEVCFG2 0x0018 +#define SDRAM_OFF_DEVCFG3 0x001C + +#define SDRAM_DEVCFG0_BASE 0xC0000000 +#define SDRAM_DEVCFG1_BASE 0xD0000000 +#define SDRAM_DEVCFG2_BASE 0xE0000000 +#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000 +#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000 + #define GLCONFIG_INIT (1 << 0) #define GLCONFIG_MRS (1 << 1) #define GLCONFIG_SMEMBUSY (1 << 5) @@ -295,6 +312,43 @@ struct sdram_regs { #define GLCONFIG_CLKSHUTDOWN (1 << 30) #define GLCONFIG_CKE (1 << 31) +#define EP93XX_SDRAMCTRL 0x80060000 +#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001 +#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002 +#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020 +#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040 +#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000 + +#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF + +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004 + +#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004 +#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008 +#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010 +#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020 +#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040 +#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000 +#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000 +#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000 + /* * 0x80070000 - 0x8007FFFF: Reserved */ @@ -324,6 +378,13 @@ struct smc_regs { }; #endif +#define EP93XX_OFF_SMCBCR0 0x00 +#define EP93XX_OFF_SMCBCR1 0x04 +#define EP93XX_OFF_SMCBCR2 0x08 +#define EP93XX_OFF_SMCBCR3 0x0C +#define EP93XX_OFF_SMCBCR6 0x18 +#define EP93XX_OFF_SMCBCR7 0x1C + #define SMC_BCR_IDCY_SHIFT 0 #define SMC_BCR_WST1_SHIFT 5 #define SMC_BCR_BLE (1 << 10) @@ -445,6 +506,14 @@ struct gpio_regs { }; #endif +#define EP93XX_LED_DATA 0x80840020 +#define EP93XX_LED_GREEN_ON 0x0001 +#define EP93XX_LED_RED_ON 0x0002 + +#define EP93XX_LED_DDR 0x80840024 +#define EP93XX_LED_GREEN_ENABLE 0x0001 +#define EP93XX_LED_RED_ENABLE 0x00020000 + /* * 0x80850000 - 0x8087FFFF: Reserved */ @@ -519,6 +588,9 @@ struct gpio_regs { #define SYSCON_OFFSET 0x930000 #define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) +/* Security */ +#define SECURITY_EXTENSIONID 0x80832714 + #ifndef __ASSEMBLY__ struct syscon_regs { uint32_t pwrsts; @@ -553,7 +625,11 @@ struct syscon_regs { #define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) #endif +#define SYSCON_OFF_CLKSET1 0x0020 +#define SYSCON_OFF_SYSCFG 0x009c + #define SYSCON_PWRCNT_UART_BAUD (1 << 29) +#define SYSCON_PWRCNT_USH_EN (1 << 28) #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 @@ -571,6 +647,8 @@ struct syscon_regs { #define SYSCON_CHIPID_REV_MASK 0xF0000000 #define SYSCON_DEVICECFG_SWRST (1 << 31) +#define SYSCON_SYSCFG_LASDO 0x00000020 + /* * 0x80930000 - 0x8093FFFF: Watchdog Timer */ @@ -580,3 +658,10 @@ struct syscon_regs { /* * 0x80950000 - 0x9000FFFF: Reserved */ + +/* + * During low_level init we store memory layout in memory at specific location + */ +#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000 +#define UBOOT_MEMORYCNF_BANK_MASK 0x2004 +#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008 diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-lsch3/clock.h new file mode 100644 index 0000000000..831af0bda3 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/clock.h @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_ +#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_ + +#include <common.h> + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_BUS_CLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_I2C_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h new file mode 100644 index 0000000000..c1c718ecd4 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -0,0 +1,65 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ +#define _ASM_ARMV8_FSL_LSCH3_CONFIG_ + +#include <fsl_ddrc_version.h> + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) +#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) +#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 +#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ + 0x18A0) + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06100000 + +/* SMMU Defintions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* DDR */ +#define CONFIG_SYS_FSL_DDR_LE +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ +#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ +#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 + + +/* IFC */ +#define CONFIG_SYS_FSL_IFC_LE + +#ifdef CONFIG_LS2085A +#define CONFIG_MAX_CPUS 16 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#else +#error SoC not defined +#endif + +#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h new file mode 100644 index 0000000000..f23a78c62d --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h @@ -0,0 +1,9 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_ +#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_ +#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h new file mode 100644 index 0000000000..18e66bdf41 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -0,0 +1,116 @@ +/* + * LayerScape Internal Memory Map + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_FSL_LSCH3_IMMAP_H +#define __ARCH_FSL_LSCH3_IMMAP_H_ + +/* This is chassis generation 3 */ + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; + unsigned long freq_qe; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_QBMAN + unsigned long freq_qman; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freq_pme; +#endif +}; + +/* Global Utilities Block */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; /* General-purpose POR configuration 2 */ + u32 dcfg_fusesr; /* Fuse status register */ + u32 gpporcr3; + u32 gpporcr4; + u8 res_034[0x70-0x34]; + u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u32 devdisr7; /* Device disable control 7 */ + u8 res_08c[0x90-0x8c]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_098[0xa0-0x98]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u32 mvr; /* Manufacturing version */ + u8 res_0ac[0x100-0xac]; + u32 rcwsr[32]; /* Reset control word status */ + +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f + u8 res_180[0x200-0x180]; + u32 scratchrw[32]; /* Scratch Read/Write */ + u8 res_280[0x300-0x280]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 bootlocptrl; /* Boot location pointer low-order addr */ + u32 bootlocptrh; /* Boot location pointer high-order addr */ + u8 res_408[0x500-0x408]; + u8 res_500[0x740-0x500]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[3]; /* Core Cluster n Topology Register */ + u8 res_858[0x1000-0x858]; +}; + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 + +#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 + +struct ccsr_clk_cluster_group { + struct { + u8 res_00[0x10]; + u32 csr; + u8 res_14[0x20-0x14]; + } hwncsr[3]; + u8 res_60[0x80-0x60]; + struct { + u32 gsr; + u8 res_84[0xa0-0x84]; + } pllngsr[3]; + u8 res_e0[0x100-0xe0]; +}; + +struct ccsr_clk_ctrl { + struct { + u32 csr; /* core cluster n clock control status */ + u8 res_04[0x20-0x04]; + } clkcncsr[8]; +}; +#endif /* __ARCH_FSL_LSCH3_IMMAP_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h new file mode 100644 index 0000000000..8f005353b4 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ +#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/spl.h b/arch/arm/include/asm/arch-keystone/spl.h index 7012ea7ff0..a7102d5640 100644 --- a/arch/arm/include/asm/arch-keystone/spl.h +++ b/arch/arm/include/asm/arch-keystone/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_SPI 2 diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h new file mode 100644 index 0000000000..f9be6211b3 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SCAN_MANAGER_H_ +#define _SCAN_MANAGER_H_ + +struct socfpga_scan_manager { + u32 stat; + u32 en; + u32 padding[2]; + u32 fifo_single_byte; + u32 fifo_double_byte; + u32 fifo_quad_byte; +}; + +/* + * Shift count to get number of IO scan chain data in granularity + * of 128-bit ( N / 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_SHIFT 7 + +/* + * Mask to get residual IO scan chain data in + * granularity of 128-bit ( N mod 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_MASK 0x7F + +/* + * Shift count to get number of IO scan chain + * data in granularity of 32-bit ( N / 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_SHIFT 5 + +/* + * Mask to get residual IO scan chain data in + * granularity of 32-bit ( N mod 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_MASK 0x1F + +/* Byte mask */ +#define IO_SCAN_CHAIN_BYTE_MASK 0xFF + +/* 24-bits (3 bytes) IO scan chain payload definition */ +#define IO_SCAN_CHAIN_PAYLOAD_24BIT 24 + +/* + * Maximum length of TDI_TDO packet payload is 128 bits, + * represented by (length - 1) in TDI_TDO header + */ +#define TDI_TDO_MAX_PAYLOAD 127 + +/* TDI_TDO packet header for IO scan chain program */ +#define TDI_TDO_HEADER_FIRST_BYTE 0x80 + +/* Position of second command byte for TDI_TDO packet */ +#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT 8 + +/* + * Maximum polling loop to wait for IO scan chain engine + * becomes idle to prevent infinite loop + */ +#define SCAN_MAX_DELAY 100 + +#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) +#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) + +/* + * Program HPS IO Scan Chain + * io_scan_chain_id - IO scan chain ID + * io_scan_chain_len_in_bits - IO scan chain length in bits + * iocsr_scan_chain - IO scan chain table + */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain); + +extern const uint32_t iocsr_scan_chain0_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain1_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain2_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain3_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; + +#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index f564046bc0..5f738240f1 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -11,8 +11,10 @@ #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index ff871bcaee..acbec46cb8 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -7,7 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 1193e76a82..4b7b67b643 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -108,4 +108,28 @@ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) +#ifndef __ASSEMBLY__ +void set_pgtable_section(u64 *page_table, u64 index, + u64 section, u64 memory_type); +static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) +{ + asm volatile("dsb sy"); + if (el == 1) { + asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); + } else if (el == 2) { + asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); + } else if (el == 3) { + asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); + asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); + asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); + } else { + hang(); + } + asm volatile("isb"); +} +#endif #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index ddebbc8fcd..a836e9f2ab 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -29,6 +29,9 @@ void l2_cache_enable(void); void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); +void arm_init_before_mmu(void); +void arm_init_domains(void); +void cpu_cache_initialization(void); void dram_bank_mmu_setup(int bank); #endif diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 2a20a770bc..d3433dafd9 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -17,4 +17,8 @@ #define CONFIG_STATIC_RELA #endif +#ifdef CONFIG_FSL_LSCH3 +#include <asm/arch-fsl-lsch3/config.h> +#endif + #endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 9f35fd694b..214f3ea51f 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -70,10 +70,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr) #define __arch_getb(a) (*(volatile unsigned char *)(a)) #define __arch_getw(a) (*(volatile unsigned short *)(a)) #define __arch_getl(a) (*(volatile unsigned int *)(a)) +#define __arch_getq(a) (*(volatile unsigned long long *)(a)) #define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v)) extern inline void __raw_writesb(unsigned long addr, const void *data, int bytelen) @@ -123,10 +125,12 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define __raw_writeb(v,a) __arch_putb(v,a) #define __raw_writew(v,a) __arch_putw(v,a) #define __raw_writel(v,a) __arch_putl(v,a) +#define __raw_writeq(v,a) __arch_putq(v,a) #define __raw_readb(a) __arch_getb(a) #define __raw_readw(a) __arch_getw(a) #define __raw_readl(a) __arch_getl(a) +#define __raw_readq(a) __arch_getq(a) /* * TODO: The kernel offers some more advanced versions of barriers, it might @@ -139,10 +143,12 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) #define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) +#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; }) #define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) +#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) /* * The compiler seems to be incapable of optimising constants @@ -168,9 +174,11 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) #define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) +#define out_le64(a,v) out_arch(q,le64,a,v) #define out_le32(a,v) out_arch(l,le32,a,v) #define out_le16(a,v) out_arch(w,le16,a,v) +#define in_le64(a) in_arch(q,le64,a) #define in_le32(a) in_arch(l,le32,a) #define in_le16(a) in_arch(w,le16,a) diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h index 693d1f4921..c61374e9f2 100644 --- a/arch/arm/include/asm/proc-armv/system.h +++ b/arch/arm/include/asm/proc-armv/system.h @@ -22,7 +22,7 @@ #define local_irq_save(flags) \ ({ \ asm volatile( \ - "mrs %0, daif" \ + "mrs %0, daif\n" \ "msr daifset, #3" \ : "=r" (flags) \ : \ diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h new file mode 100644 index 0000000000..74111dc359 --- /dev/null +++ b/arch/arm/include/asm/semihosting.h @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Broadcom Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SEMIHOSTING_H__ +#define __SEMIHOSTING_H__ + +/* + * ARM semihosting functions for loading images to memory. See the source + * code for more information. + */ +int smh_load(const char *fname, void *memp, int avail, int verbose); +int smh_read(int fd, void *memp, int len); +int smh_open(const char *fname, char *modestr); +int smh_close(int fd); +int smh_len_fd(int fd); +int smh_len(const char *fname); + +#endif /* __SEMIHOSTING_H__ */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 74ee9a4df9..d51ba668f3 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -78,6 +78,8 @@ void gic_send_sgi(unsigned long sgino); void wait_for_wakeup(void); void smp_kick_all_cpus(void); +void flush_l3_cache(void); + #endif /* __ASSEMBLY__ */ #else /* CONFIG_ARM64 */ |