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-rw-r--r--arch/arm/dts/Makefile5
-rw-r--r--arch/arm/dts/socfpga_arria5.dtsi34
-rw-r--r--arch/arm/dts/socfpga_arria5_socdk.dts74
-rw-r--r--arch/arm/dts/socfpga_cyclone5_socdk.dts79
-rw-r--r--arch/arm/dts/tegra30-apalis.dts13
-rw-r--r--arch/arm/dts/tegra30-colibri.dts4
-rw-r--r--arch/arm/dts/uniphier-ph1-ld4-ref.dts7
-rw-r--r--arch/arm/dts/uniphier-ph1-ld4.dtsi27
-rw-r--r--arch/arm/dts/uniphier-ph1-pro4-ref.dts7
-rw-r--r--arch/arm/dts/uniphier-ph1-pro4.dtsi33
-rw-r--r--arch/arm/dts/uniphier-ph1-sld3-ref.dts7
-rw-r--r--arch/arm/dts/uniphier-ph1-sld3.dtsi27
-rw-r--r--arch/arm/dts/uniphier-ph1-sld8-ref.dts7
-rw-r--r--arch/arm/dts/uniphier-ph1-sld8.dtsi27
-rw-r--r--arch/arm/dts/uniphier-ref-daughter.dtsi3
15 files changed, 282 insertions, 72 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fac16cc384..cbe5b86755 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -49,7 +49,10 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
-dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+dtb-$(CONFIG_SOCFPGA) += \
+ socfpga_arria5_socdk.dtb \
+ socfpga_cyclone5_socdk.dtb \
+ socfpga_cyclone5_socrates.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi
new file mode 100644
index 0000000000..5175f03da4
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria5.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+ soc {
+ clkmgr@ffd04000 {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+
+ mmc0: dwmmc0@ff704000 {
+ num-slots = <1>;
+ broken-cd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ };
+
+ sysmgr@ffd08000 {
+ cpu1-start-addr = <0xffd080c4>;
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
new file mode 100644
index 0000000000..4e529a15c3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_arria5.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Arria V SoC Development Kit";
+ compatible = "altr,socfpga-arria5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&regulator_3_3v>;
+ vqmmc-supply = <&regulator_3_3v>;
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
new file mode 100644
index 0000000000..8e1f88c2c7
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Cyclone V SoC Development Kit";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&mmc0 {
+ cd-gpios = <&portb 18 0>;
+ vmmc-supply = <&regulator_3_3v>;
+ vqmmc-supply = <&regulator_3_3v>;
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 15db0f275b..13ab42bf3d 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -18,6 +18,10 @@
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
sdhci2 = "/sdhci@78000000";
+ spi0 = "/spi@7000d400";
+ spi1 = "/spi@7000dc00";
+ spi2 = "/spi@7000de00";
+ spi3 = "/spi@7000da00";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d004000";
usb2 = "/usb@7d008000";
@@ -243,13 +247,15 @@
sdhci@78000000 {
status = "okay";
bus-width = <4>;
- cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
+ /* SD1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
};
sdhci@78000400 {
status = "okay";
bus-width = <8>;
- cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+ /* MMC1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
};
sdhci@78000600 {
@@ -262,12 +268,14 @@
usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
+ /* USBO1_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
usb@7d004000 {
status = "okay";
+ /* USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
phy_type = "utmi";
};
@@ -275,6 +283,7 @@
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
usb@7d008000 {
status = "okay";
+ /* USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts
index 6cd1902f11..36533dc840 100644
--- a/arch/arm/dts/tegra30-colibri.dts
+++ b/arch/arm/dts/tegra30-colibri.dts
@@ -64,7 +64,7 @@
sdhci@78000200 {
status = "okay";
bus-width = <4>;
- cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
};
sdhci@78000600 {
@@ -83,12 +83,14 @@
usb@7d004000 {
status = "okay";
phy_type = "utmi";
+ /* VBUS_LAN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
usb@7d008000 {
status = "okay";
+ /* USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index d479be1d4d..d972c0230e 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier PH1-LD4 Reference Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -12,8 +13,8 @@
/include/ "uniphier-ref-daughter.dtsi"
/ {
- model = "Panasonic UniPhier PH1-LD4 Reference Board";
- compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4";
+ model = "UniPhier PH1-LD4 Reference Board";
+ compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 8ed7bbf53c..c2008383c1 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier PH1-LD4 SoC
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,7 +11,7 @@
/include/ "skeleton.dtsi"
/ {
- compatible = "panasonic,ph1-ld4";
+ compatible = "socionext,ph1-ld4";
cpus {
#address-cells = <1>;
@@ -30,35 +31,35 @@
ranges;
uart0: serial@54006800 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <36864000>;
};
uart1: serial@54006900 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <36864000>;
};
uart2: serial@54006a00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <36864000>;
};
uart3: serial@54006b00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x20>;
clock-frequency = <36864000>;
};
i2c0: i2c@58400000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58400000 0x40>;
@@ -67,7 +68,7 @@
};
i2c1: i2c@58480000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58480000 0x40>;
@@ -76,7 +77,7 @@
};
i2c2: i2c@58500000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58500000 0x40>;
@@ -85,7 +86,7 @@
};
i2c3: i2c@58580000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58580000 0x40>;
@@ -94,19 +95,19 @@
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index 5bec92b8f3..f6d03e3e26 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier PH1-Pro4 Reference Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -12,8 +13,8 @@
/include/ "uniphier-ref-daughter.dtsi"
/ {
- model = "Panasonic UniPhier PH1-Pro4 Reference Board";
- compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4";
+ model = "UniPhier PH1-Pro4 Reference Board";
+ compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 1247779ab0..8195266db3 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier PH1-Pro4 SoC
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,7 +11,7 @@
/include/ "skeleton.dtsi"
/ {
- compatible = "panasonic,ph1-pro4";
+ compatible = "socionext,ph1-pro4";
cpus {
#address-cells = <1>;
@@ -36,35 +37,35 @@
ranges;
uart0: serial@54006800 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <73728000>;
};
uart1: serial@54006900 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <73728000>;
};
uart2: serial@54006a00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <73728000>;
};
uart3: serial@54006b00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x20>;
clock-frequency = <73728000>;
};
i2c0: i2c@58780000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58780000 0x80>;
@@ -73,7 +74,7 @@
};
i2c1: i2c@58781000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58781000 0x80>;
@@ -82,7 +83,7 @@
};
i2c2: i2c@58782000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58782000 0x80>;
@@ -91,7 +92,7 @@
};
i2c3: i2c@58783000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58783000 0x80>;
@@ -102,7 +103,7 @@
/* i2c4 does not exist */
i2c5: i2c@58785000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58785000 0x80>;
@@ -111,7 +112,7 @@
};
i2c6: i2c@58786000 {
- compatible = "panasonic,uniphier-fi2c";
+ compatible = "socionext,uniphier-fi2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58786000 0x80>;
@@ -120,25 +121,25 @@
};
usb2: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb3: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb0: usb@65a00000 {
- compatible = "panasonic,uniphier-xhci", "generic-xhci";
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
status = "disabled";
reg = <0x65a00000 0x100>;
};
usb1: usb@65c00000 {
- compatible = "panasonic,uniphier-xhci", "generic-xhci";
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
status = "disabled";
reg = <0x65c00000 0x100>;
};
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index 8a7f90ac78..d9616f68a0 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier PH1-sLD3 Reference Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -12,8 +13,8 @@
/include/ "uniphier-ref-daughter.dtsi"
/ {
- model = "Panasonic UniPhier PH1-sLD3 Reference Board";
- compatible = "panasonic,ph1-sld3-ref", "panasonic,ph1-sld3";
+ model = "UniPhier PH1-sLD3 Reference Board";
+ compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 88322c6a8c..44b19897b3 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier PH1-sLD3 SoC
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,7 +11,7 @@
/include/ "skeleton.dtsi"
/ {
- compatible = "panasonic,ph1-sld3";
+ compatible = "socionext,ph1-sld3";
cpus {
#address-cells = <1>;
@@ -36,28 +37,28 @@
ranges;
uart0: serial@54006800 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <36864000>;
};
uart1: serial@54006900 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <36864000>;
};
uart2: serial@54006a00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <36864000>;
};
i2c0: i2c@58400000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58400000 0x40>;
@@ -66,7 +67,7 @@
};
i2c1: i2c@58480000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58480000 0x40>;
@@ -75,7 +76,7 @@
};
i2c2: i2c@58500000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58500000 0x40>;
@@ -84,7 +85,7 @@
};
i2c3: i2c@58580000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58580000 0x40>;
@@ -93,25 +94,25 @@
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
usb3: usb@5a830100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a830100 0x100>;
};
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index 0cb9c47b65..69e9bfa9ba 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier PH1-sLD8 Reference Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -12,8 +13,8 @@
/include/ "uniphier-ref-daughter.dtsi"
/ {
- model = "Panasonic UniPhier PH1-sLD8 Reference Board";
- compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8";
+ model = "UniPhier PH1-sLD8 Reference Board";
+ compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index 1b3eb228c8..d9f61c2231 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier PH1-sLD8 SoC
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,7 +11,7 @@
/include/ "skeleton.dtsi"
/ {
- compatible = "panasonic,ph1-sld8";
+ compatible = "socionext,ph1-sld8";
cpus {
#address-cells = <1>;
@@ -30,35 +31,35 @@
ranges;
uart0: serial@54006800 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x20>;
clock-frequency = <80000000>;
};
uart1: serial@54006900 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x20>;
clock-frequency = <80000000>;
};
uart2: serial@54006a00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x20>;
clock-frequency = <80000000>;
};
uart3: serial@54006b00 {
- compatible = "panasonic,uniphier-uart";
+ compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x20>;
clock-frequency = <80000000>;
};
i2c0: i2c@58400000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58400000 0x40>;
@@ -67,7 +68,7 @@
};
i2c1: i2c@58480000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58480000 0x40>;
@@ -76,7 +77,7 @@
};
i2c2: i2c@58500000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58500000 0x40>;
@@ -85,7 +86,7 @@
};
i2c3: i2c@58580000 {
- compatible = "panasonic,uniphier-i2c";
+ compatible = "socionext,uniphier-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58580000 0x40>;
@@ -94,19 +95,19 @@
};
usb0: usb@5a800100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
- compatible = "panasonic,uniphier-ehci", "generic-ehci";
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi
index 0145b51780..aca9f58b25 100644
--- a/arch/arm/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/dts/uniphier-ref-daughter.dtsi
@@ -2,7 +2,8 @@
* Device Tree Source for UniPhier Reference Daughter Board
*
* Copyright (C) 2014-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-01 04:13:33 +0000