diff options
Diffstat (limited to 'arch/arm/dts/armada-8040-mcbin.dts')
| -rw-r--r-- | arch/arm/dts/armada-8040-mcbin.dts | 91 |
1 files changed, 46 insertions, 45 deletions
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 5a046d9de4..2184648318 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2016 - 2021 Marvell International Ltd. */ #include "armada-8040.dtsi" /* include SoC device tree */ @@ -15,12 +15,12 @@ }; aliases { - i2c0 = &cpm_i2c0; - i2c1 = &cpm_i2c1; - spi0 = &cps_spi1; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + spi0 = &cp1_spi1; gpio0 = &ap_gpio0; - gpio1 = &cpm_gpio0; - gpio2 = &cpm_gpio1; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; }; memory@00000000 { @@ -36,7 +36,7 @@ reg_usb3h0_vbus: usb3-vbus0 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&cpm_xhci_vbus_pins>; + pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "reg-usb3h0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -44,7 +44,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ + gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ }; }; }; @@ -73,7 +73,7 @@ status = "okay"; }; -&cpm_pinctl { +&cp0_pinctl { /* * MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins: @@ -108,59 +108,59 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >; - cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + cp0_xhci_vbus_pins: cp0-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; }; - cpm_pcie_reset_pins: cpm-pcie-reset-pins { + cp0_pcie_reset_pins: cp0-pcie-reset-pins { marvell,pins = < 52 >; marvell,function = <0>; }; }; /* uSD slot */ -&cpm_sdhci0 { +&cp0_sdhci0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; + pinctrl-0 = <&cp0_sdhci_pins>; bus-width= <4>; status = "okay"; }; /* PCIe x4 */ -&cpm_pcie0 { +&cp0_pcie0 { num-lanes = <4>; pinctrl-names = "default"; - pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ + pinctrl-0 = <&cp0_pcie_reset_pins>; + marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ status = "okay"; }; -&cpm_i2c0 { +&cp0_i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c0_pins>; + pinctrl-0 = <&cp0_i2c0_pins>; status = "okay"; clock-frequency = <100000>; }; -&cpm_i2c1 { +&cp0_i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&cpm_i2c1_pins>; + pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; clock-frequency = <100000>; }; -&cpm_sata0 { +&cp0_sata0 { status = "okay"; }; -&cpm_mdio { +&cp0_mdio { ge_phy: ethernet-phy@0 { reg = <0>; }; }; -&cpm_comphy { +&cp0_comphy { /* * CP0 Serdes Configuration: * Lane 0: PCIe0 (x4) @@ -171,49 +171,49 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy3 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; }; -&cps_sata0 { +&cp1_sata0 { status = "okay"; }; -&cps_usb3_0 { +&cp1_usb3_0 { vbus-supply = <®_usb3h0_vbus>; status = "okay"; }; -&cps_utmi0 { +&cp1_utmi0 { status = "okay"; }; -&cps_ethernet { +&cp1_ethernet { status = "okay"; }; -&cps_eth1 { +&cp1_eth1 { status = "okay"; phy = <&ge_phy>; phy-mode = "sgmii"; }; -&cps_pinctl { +&cp1_pinctl { /* * MPP Bus: * [0-5] TDM @@ -246,9 +246,9 @@ 0xff 0xff 0xff>; }; -&cps_spi1 { +&cp1_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cps_spi1_pins>; + pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; spi-flash@0 { @@ -275,7 +275,7 @@ }; }; -&cps_comphy { +&cp1_comphy { /* * CP1 Serdes Configuration: * Lane 0: SGMII1 @@ -286,22 +286,23 @@ * Lane 5: SGMII3 */ phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI0>; }; phy5 { - phy-type = <PHY_TYPE_SGMII3>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; |