19 files changed, 514 insertions, 55 deletions

diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile
index dcbd57065b..774f352ece 100644
--- a/arch/arm/cpu/arm1136/mx31/Makefile
+++ b/arch/arm/cpu/arm1136/mx31/Makefile
@@ -8,7 +8,4 @@
 obj-y	+= generic.o
 obj-y	+= timer.o
 obj-y	+= devices.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y  += relocate.o
-endif
+obj-y	+= relocate.o
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index 796db9c7cc..e4c8e2e684 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -10,7 +10,4 @@
 obj-y	+= generic.o
 obj-y	+= timer.o
 obj-y	+= mx35_sdram.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y  += relocate.o
-endif
+obj-y	+= relocate.o
diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile
index ebc0407ef4..7d608c6082 100644
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -4,8 +4,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-obj-y	= generic.o timer.o reset.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y	+= relocate.o
-endif
+obj-y	+= generic.o timer.o reset.o relocate.o
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 0edf1445fe..7d608c6082 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -4,8 +4,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-obj-y	= generic.o reset.o timer.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y	+= relocate.o
-endif
+obj-y	+= generic.o timer.o reset.o relocate.o
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 95a0b5224b..7e2695761e 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -239,55 +239,47 @@ skip_errata_801819:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_454179
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_454179
+	orrlt	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_454179:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_430973
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_430973
+	orrlt	r0, r0, #(0x1 << 6)	@ Set IBE bit
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x1 << 6)	@ Set IBE bit
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_430973:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_621766
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_621766
+	orrlt	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_621766:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_725233
+	mrc	p15, 1, r0, c9, c0, 2	@ Read L2ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1 (Cortex A8)
-	bge	skip_errata_725233
+	orrlt	r0, r0, #(0x1 << 27)	@ L2 PLD data forwarding disable
 
-	mrc	p15, 1, r0, c9, c0, 2	@ Read L2ACR
-	orr	r0, r0, #(0x1 << 27)	@ L2 PLD data forwarding disable
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_l2aux_ctrl
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_725233:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_852421
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 12aba9d4e9..3a0e129d2e 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -85,11 +85,12 @@ endmenu
 config PSCI_RESET
 	bool "Use PSCI for reset and shutdown"
 	default y
-	depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
+	depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
 		   !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
-		   !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+		   !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
 		   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
+		   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS2081ARDB && \
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 6c03dfb1d5..cefbdfe855 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,6 +1,7 @@
 config ARCH_LS1012A
 	bool
 	select ARMV8_SET_SMPEN
+	select ARM_ERRATA_855873
 	select FSL_LSCH2
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_MMDC
@@ -16,6 +17,7 @@ config ARCH_LS1012A
 config ARCH_LS1043A
 	bool
 	select ARMV8_SET_SMPEN
+	select ARM_ERRATA_855873
 	select FSL_LSCH2
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
@@ -68,6 +70,7 @@ config ARCH_LS1046A
 config ARCH_LS1088A
 	bool
 	select ARMV8_SET_SMPEN
+	select ARM_ERRATA_855873
 	select FSL_LSCH3
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_LE
@@ -493,8 +496,7 @@ config SYS_FSL_HAS_RGMII
 config SYS_MC_RSV_MEM_ALIGN
 	hex "Management Complex reserved memory alignment"
 	depends on RESV_RAM
-	default 0x20000000 if ARCH_LS2080A
-	default 0x70000000 if ARCH_LS1088A
+	default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
 	help
 	  Reserved memory needs to be aligned for MC to use. Default value
 	  is 512MB.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 115c3fc1d1..0cb6d4eb4d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,8 +7,10 @@
 obj-y += cpu.o
 obj-y += lowlevel.o
 obj-y += soc.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
+endif
 obj-$(CONFIG_SPL) += spl.o
 obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 00d2564c79..70a6070935 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -30,6 +30,7 @@
 #endif
 #include <asm/arch/clock.h>
 #include <hwconfig.h>
+#include <fsl_qbman.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -565,6 +566,9 @@ int arch_early_init_r(void)
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_qbman_portals();
+#endif
 	return 0;
 }
 
@@ -574,7 +578,7 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 	u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
 	u32 svr_dev_id;
 #endif
@@ -593,7 +597,7 @@ int timer_init(void)
 	out_le32(cltbenr, 0xf);
 #endif
 
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 	/*
 	 * In certain Layerscape SoCs, the clock for each core's
 	 * has an enable bit in the PMU Physical Core Time Base Enable
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
index 2505f408ab..a00b5bc9c3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
@@ -86,7 +86,7 @@ Example:
 	#address-cells = <1>;
 
 	images {
-		kernel@1 {
+		kernel {
 			description = "ARM64 Linux kernel";
 			data = /incbin/("./arch/arm64/boot/Image.gz");
 			type = "kernel";
@@ -96,7 +96,7 @@ Example:
 			load = <0x80080000>;
 			entry = <0x80080000>;
 		};
-		fdt@1 {
+		fdt-1 {
 			description = "Flattened Device Tree blob";
 			data = /incbin/("./fsl-ls1043ardb-static.dtb");
 			type = "flat_dt";
@@ -104,7 +104,7 @@ Example:
 			compression = "none";
 			load = <0x90000000>;
 		};
-		ramdisk@1 {
+		ramdisk {
 			description = "LS1043 Ramdisk";
                         data = /incbin/("./rootfs.cpio.gz");
 			type = "ramdisk";
@@ -116,12 +116,12 @@ Example:
 	};
 
 	configurations {
-		default = "config@1";
-		config@1 {
+		default = "config-1";
+		config-1 {
 			description = "Boot Linux kernel";
-			kernel = "kernel@1";
-			fdt = "fdt@1";
-			ramdisk = "ramdisk@1";
+			kernel = "kernel";
+			fdt = "fdt-1";
+			ramdisk = "ramdisk";
 			loadables = "fdt", "ramdisk";
 		};
 	};
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 39ffe1ab4d..80af318822 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -26,6 +26,8 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
 #endif
+#include <asm/arch/speed.h>
+#include <fsl_qbman.h>
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -442,6 +444,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	fdt_fixup_esdhc(blob, bd);
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	fdt_fixup_bportals(blob);
+	fdt_fixup_qportals(blob);
+	do_fixup_by_compat_u32(blob, "fsl,qman",
+			       "clock-frequency", get_qman_freq(), 1);
+#endif
+
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 2d7775e54f..5f23aadc2c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -155,8 +155,22 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_localbus = sys_info->freq_systembus /
 						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	sys_info->freq_qman = sys_info->freq_systembus;
+#endif
 }
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void)
+{
+	struct sys_info sys_info;
+
+	get_sys_info(&sys_info);
+
+	return sys_info.freq_qman;
+}
+#endif
+
 int get_clocks(void)
 {
 	struct sys_info sys_info;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 179cac6e49..9ee0dd23e9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -158,6 +158,293 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 	serdes_prtcl_map[NONE] = 1;
 }
 
+__weak int get_serdes_volt(void)
+{
+	return -1;
+}
+
+__weak int set_serdes_volt(int svdd)
+{
+	return -1;
+}
+
+#define LNAGCR0_RT_RSTB		0x00600000
+
+#define RSTCTL_RESET_MASK	0x000000E0
+
+#define RSTCTL_RSTREQ		0x80000000
+#define RSTCTL_RST_DONE		0x40000000
+#define RSTCTL_RSTERR		0x20000000
+
+#define RSTCTL_SDEN		0x00000020
+#define RSTCTL_SDRST_B		0x00000040
+#define RSTCTL_PLLRST_B		0x00000080
+
+#define TCALCR_CALRST_B		0x08000000
+
+struct serdes_prctl_info {
+	u32 id;
+	u32 mask;
+	u32 shift;
+};
+
+struct serdes_prctl_info srds_prctl_info[] = {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	{.id = 1,
+	 .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
+	 .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
+	},
+
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	{.id = 2,
+	 .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
+	 .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
+	},
+#endif
+	{} /* NULL ENTRY */
+};
+
+static int get_serdes_prctl_info_idx(u32 serdes_id)
+{
+	int pos = 0;
+	struct serdes_prctl_info *srds_info;
+
+	/* loop until NULL ENTRY defined by .id=0 */
+	for (srds_info = srds_prctl_info; srds_info->id != 0;
+	     srds_info++, pos++) {
+		if (srds_info->id == serdes_id)
+			return pos;
+	}
+
+	return -1;
+}
+
+static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
+				   struct ccsr_serdes __iomem *serdes_base,
+				   bool cmplt)
+{
+	int i, pos;
+	u32 cfg_tmp;
+
+	pos = get_serdes_prctl_info_idx(serdes_id);
+	if (pos == -1) {
+		printf("invalid serdes_id %d\n", serdes_id);
+		return;
+	}
+
+	cfg_tmp = cfg & srds_prctl_info[pos].mask;
+	cfg_tmp >>= srds_prctl_info[pos].shift;
+
+	for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
+		if (cmplt)
+			setbits_le32(&serdes_base->lane[i].gcr0,
+				     LNAGCR0_RT_RSTB);
+		else
+			clrbits_le32(&serdes_base->lane[i].gcr0,
+				     LNAGCR0_RT_RSTB);
+	}
+}
+
+static void do_pll_reset(u32 cfg,
+			 struct ccsr_serdes __iomem *serdes_base)
+{
+	int i;
+
+	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+		clrbits_le32(&serdes_base->bank[i].rstctl,
+			     RSTCTL_RESET_MASK);
+		udelay(1);
+
+		setbits_le32(&serdes_base->bank[i].rstctl,
+			     RSTCTL_RSTREQ);
+	}
+	udelay(1);
+}
+
+static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
+{
+	clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+	clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+}
+
+static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
+				    struct ccsr_serdes __iomem *serdes_base)
+{
+	if (!(cfg == 0x3 && i == 1)) {
+		udelay(1);
+		setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+		setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+	}
+	udelay(1);
+}
+
+static void do_pll_reset_done(u32 cfg,
+			      struct ccsr_serdes __iomem *serdes_base)
+{
+	int i;
+	u32 reg = 0;
+
+	for (i = 0; i < 2; i++) {
+		reg = in_le32(&serdes_base->bank[i].pllcr0);
+		if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
+			setbits_le32(&serdes_base->bank[i].rstctl,
+				     RSTCTL_RST_DONE);
+		}
+	}
+}
+
+static void do_serdes_enable(u32 cfg,
+			     struct ccsr_serdes __iomem *serdes_base)
+{
+	int i;
+
+	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+		setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
+		udelay(1);
+
+		setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
+		udelay(1);
+		/* Take the Rx/Tx calibration out of reset */
+		do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
+	}
+}
+
+static void do_pll_lock(u32 cfg,
+			struct ccsr_serdes __iomem *serdes_base)
+{
+	int i;
+	u32 reg = 0;
+
+	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+		/* if the PLL is not locked, set RST_ERR */
+		reg = in_le32(&serdes_base->bank[i].pllcr0);
+		if (!((reg >> 23) & 0x1)) {
+			setbits_le32(&serdes_base->bank[i].rstctl,
+				     RSTCTL_RSTERR);
+		} else {
+			udelay(1);
+			setbits_le32(&serdes_base->bank[i].rstctl,
+				     RSTCTL_SDRST_B);
+			udelay(1);
+		}
+	}
+}
+
+int setup_serdes_volt(u32 svdd)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_serdes __iomem *serdes1_base =
+			(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
+	u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	struct ccsr_serdes __iomem *serdes2_base =
+			(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+	u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
+#endif
+	u32 cfg_tmp;
+	int svdd_cur, svdd_tar;
+	int ret = 1;
+
+	/* Only support switch SVDD to 900mV */
+	if (svdd != 900)
+		return -EINVAL;
+
+	/* Scale up to the LTC resolution is 1/4096V */
+	svdd = (svdd * 4096) / 1000;
+
+	svdd_tar = svdd;
+	svdd_cur = get_serdes_volt();
+	if (svdd_cur < 0)
+		return -EINVAL;
+
+	debug("%s: current SVDD: %x; target SVDD: %x\n",
+	      __func__, svdd_cur, svdd_tar);
+	if (svdd_cur == svdd_tar)
+		return 0;
+
+	/* Put the all enabled lanes in reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
+#endif
+
+	/* Put the all enabled PLL in reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	cfg_tmp = cfg_rcwsrds1 & 0x3;
+	do_pll_reset(cfg_tmp, serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	cfg_tmp = cfg_rcwsrds1 & 0xC;
+	cfg_tmp >>= 2;
+	do_pll_reset(cfg_tmp, serdes2_base);
+#endif
+
+	/* Put the Rx/Tx calibration into reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	do_rx_tx_cal_reset(serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	do_rx_tx_cal_reset(serdes2_base);
+#endif
+
+	ret = set_serdes_volt(svdd);
+	if (ret < 0) {
+		printf("could not change SVDD\n");
+		ret = -1;
+	}
+
+	/* For each PLL that’s not disabled via RCW enable the SERDES */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	cfg_tmp = cfg_rcwsrds1 & 0x3;
+	do_serdes_enable(cfg_tmp, serdes1_base);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	cfg_tmp = cfg_rcwsrds1 & 0xC;
+	cfg_tmp >>= 2;
+	do_serdes_enable(cfg_tmp, serdes2_base);
+#endif
+
+	/* Wait for at at least 625us, ensure the PLLs being reset are locked */
+	udelay(800);
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	cfg_tmp = cfg_rcwsrds1 & 0x3;
+	do_pll_lock(cfg_tmp, serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	cfg_tmp = cfg_rcwsrds1 & 0xC;
+	cfg_tmp >>= 2;
+	do_pll_lock(cfg_tmp, serdes2_base);
+#endif
+	/* Take the all enabled lanes out of reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
+#endif
+
+	/* For each PLL being reset, and achieved PLL lock set RST_DONE */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	cfg_tmp = cfg_rcwsrds1 & 0x3;
+	do_pll_reset_done(cfg_tmp, serdes1_base);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	cfg_tmp = cfg_rcwsrds1 & 0xC;
+	cfg_tmp >>= 2;
+	do_pll_reset_done(cfg_tmp, serdes2_base);
+#endif
+
+	return ret;
+}
+
 void fsl_serdes_init(void)
 {
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index ae57c0e31d..b9f837d58d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -341,6 +341,8 @@ int sata_init(void)
 #ifdef CONFIG_SYS_SATA2
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 #endif
@@ -348,6 +350,8 @@ int sata_init(void)
 #ifdef CONFIG_SYS_SATA1
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
@@ -359,6 +363,45 @@ int sata_init(void)
 }
 #endif
 
+/* Get VDD in the unit mV from voltage ID */
+int get_core_volt_from_fuse(void)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	int vdd;
+	u32 fusesr;
+	u8 vid;
+
+	/* get the voltage ID from fuse status register */
+	fusesr = in_le32(&gur->dcfg_fusesr);
+	debug("%s: fusesr = 0x%x\n", __func__, fusesr);
+	vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+		FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+	if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+		vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+			FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+	}
+	debug("%s: VID = 0x%x\n", __func__, vid);
+	switch (vid) {
+	case 0x00: /* VID isn't supported */
+		vdd = -EINVAL;
+		debug("%s: The VID feature is not supported\n", __func__);
+		break;
+	case 0x08: /* 0.9V silicon */
+		vdd = 900;
+		break;
+	case 0x10: /* 1.0V silicon */
+		vdd = 1000;
+		break;
+	default:  /* Other core voltage */
+		vdd = -EINVAL;
+		debug("%s: The VID(%x) isn't supported\n", __func__, vid);
+		break;
+	}
+	debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
+
+	return vdd;
+}
+
 #elif defined(CONFIG_FSL_LSCH2)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 int sata_init(void)
@@ -368,6 +411,8 @@ int sata_init(void)
 	/* Disable SATA ECC */
 	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 1c694e7c67..4093d15e56 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -85,6 +85,9 @@ void board_init_f(ulong dummy)
 #ifdef CONFIG_SPL_I2C_SUPPORT
 	i2c_init_all();
 #endif
+#ifdef CONFIG_VID
+	init_func_vid();
+#endif
 	dram_init();
 #ifdef CONFIG_SPL_FSL_LS_PPA
 #ifndef CONFIG_SYS_MEM_RESERVE_SECURE
diff --git a/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h
new file mode 100644
index 0000000000..3e720937f0
--- /dev/null
+++ b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2017 NVIDIA Corporation <www.nvidia.com>
+ *
+ * Derived from Linux kernel v4.14 files:
+ *
+ * arch/arm64/include/asm/assembler.h:
+ * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
+ * Copyright (C) 1996-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * arch/arm64/kernel/head.S:
+ * Based on arch/arm/kernel/head.S
+ * Copyright (C) 1994-2002 Russell King
+ * Copyright (C) 2003-2012 ARM Ltd.
+ * Authors:	Catalin Marinas <catalin.marinas@arm.com>
+ *		Will Deacon <will.deacon@arm.com>
+ *
+ * arch/arm64/kernel/image.h:
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+/*
+ * There aren't any ELF relocations we can use to endian-swap values known only
+ * at link time (e.g. the subtraction of two symbol addresses), so we must get
+ * the linker to endian-swap certain values before emitting them.
+ *
+ * Note that, in order for this to work when building the ELF64 PIE executable
+ * (for KASLR), these values should not be referenced via R_AARCH64_ABS64
+ * relocations, since these are fixed up at runtime rather than at build time
+ * when PIE is in effect. So we need to split them up in 32-bit high and low
+ * words.
+ */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define DATA_LE32(data)				\
+	((((data) & 0x000000ff) << 24) |	\
+	 (((data) & 0x0000ff00) << 8)  |	\
+	 (((data) & 0x00ff0000) >> 8)  |	\
+	 (((data) & 0xff000000) >> 24))
+#else
+#define DATA_LE32(data) ((data) & 0xffffffff)
+#endif
+
+#define DEFINE_IMAGE_LE64(sym, data)				\
+	sym##_lo32 = DATA_LE32((data) & 0xffffffff);		\
+	sym##_hi32 = DATA_LE32((data) >> 32)
+
+#define __MAX(a, b)		(((a) > (b)) ? (a) : (b))
+#define __CODE_DATA_SIZE	(__bss_start - _start)
+#define __BSS_SIZE		(__bss_end - __bss_start)
+#ifdef CONFIG_SYS_INIT_SP_BSS_OFFSET
+#define __MAX_EXTRA_RAM_USAGE	__MAX(__BSS_SIZE, CONFIG_SYS_INIT_SP_BSS_OFFSET)
+#else
+#define __MAX_EXTRA_RAM_USAGE	__BSS_SIZE
+#endif
+#define __MEM_USAGE		(__CODE_DATA_SIZE + __MAX_EXTRA_RAM_USAGE)
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define __HEAD_FLAG_BE		1
+#else
+#define __HEAD_FLAG_BE		0
+#endif
+
+#define __HEAD_FLAG_PAGE_SIZE	1 /* 4K hard-coded */
+
+#define __HEAD_FLAG_PHYS_BASE	1
+
+#define __HEAD_FLAGS		((__HEAD_FLAG_BE << 0) |	\
+				 (__HEAD_FLAG_PAGE_SIZE << 1) |	\
+				 (__HEAD_FLAG_PHYS_BASE << 3))
+
+#define TEXT_OFFSET (CONFIG_SYS_TEXT_BASE - \
+			CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE)
+
+/*
+ * These will output as part of the Image header, which should be little-endian
+ * regardless of the endianness of the kernel. While constant values could be
+ * endian swapped in head.S, all are done here for consistency.
+ */
+#define HEAD_SYMBOLS						\
+	DEFINE_IMAGE_LE64(_kernel_size_le, __MEM_USAGE);	\
+	DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET);	\
+	DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS);
+
+	HEAD_SYMBOLS
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 927eae4f74..b56ea785c5 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -30,7 +30,7 @@ phys_addr_t sec_firmware_addr;
 #define SEC_FIRMWARE_FIT_IMAGE		"firmware"
 #endif
 #ifndef SEC_FIRMEWARE_FIT_CNF_NAME
-#define SEC_FIRMEWARE_FIT_CNF_NAME	"config@1"
+#define SEC_FIRMEWARE_FIT_CNF_NAME	"config-1"
 #endif
 #ifndef SEC_FIRMWARE_TARGET_EL
 #define SEC_FIRMWARE_TARGET_EL		2
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 03e744e4a6..7a98a1c95d 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -19,7 +19,9 @@
 
 .globl	_start
 _start:
-#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+#if defined(LINUX_KERNEL_IMAGE_HEADER)
+#include <asm/boot0-linux-kernel-header.h>
+#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
 /*
  * Various SoCs need something special and SoC-specific up front in
  * order to boot, allow them to set that in their boot0.h file and then
@@ -196,7 +198,10 @@ reset_sctrl:
 WEAK(apply_core_errata)
 
 	mov	x29, lr			/* Save LR */
-	/* For now, we support Cortex-A57 specific errata only */
+	/* For now, we support Cortex-A53, Cortex-A57 specific errata */
+
+	/* Check if we are running on a Cortex-A53 core */
+	branch_if_a53_core x0, apply_a53_core_errata
 
 	/* Check if we are running on a Cortex-A57 core */
 	branch_if_a57_core x0, apply_a57_core_errata
@@ -204,6 +209,25 @@ WEAK(apply_core_errata)
 	mov	lr, x29			/* Restore LR */
 	ret
 
+apply_a53_core_errata:
+
+#ifdef CONFIG_ARM_ERRATA_855873
+	mrs	x0, midr_el1
+	tst	x0, #(0xf << 20)
+	b.ne	0b
+
+	mrs	x0, midr_el1
+	and	x0, x0, #0xf
+	cmp	x0, #3
+	b.lt	0b
+
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Enable data cache clean as data cache clean/invalidate */
+	orr	x0, x0, #1 << 44
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+	b 0b
+
 apply_a57_core_errata:
 
 #ifdef CONFIG_ARM_ERRATA_828024
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 22195b8834..7b76e0f9f0 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -159,4 +159,8 @@ SECTIONS
 	/DISCARD/ : { *(.plt*) }
 	/DISCARD/ : { *(.interp*) }
 	/DISCARD/ : { *(.gnu*) }
+
+#ifdef CONFIG_LINUX_KERNEL_IMAGE_HEADER
+#include "linux-kernel-image-header-vars.h"
+#endif
 }