diff options
Diffstat (limited to 'arch/arm/cpu/armv8')
| -rw-r--r-- | arch/arm/cpu/armv8/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/cpu-dt.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fel_utils.S | 78 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/spl.c | 5 |
7 files changed, 92 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 93d26f9856..f7b4a5ee46 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -27,6 +27,8 @@ obj-$(CONFIG_ARM_SMCCC) += smccc-call.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o +else +obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o endif obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 97d4473a68..61c38b17cb 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -9,7 +9,7 @@ #include <asm/system.h> #include <asm/armv8/sec_firmware.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) int psci_update_dt(void *fdt) { /* diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S new file mode 100644 index 0000000000..9510dcd9e4 --- /dev/null +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -0,0 +1,78 @@ +/* + * Utility functions for FEL mode, when running SPL in AArch64. + * + * Copyright (c) 2017 Arm Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/system.h> +#include <linux/linkage.h> + +/* + * We don't overwrite save_boot_params() here, to save the FEL state upon + * entry, since this would run *after* the RMR reset, which clobbers that + * state. + * Instead we store the state _very_ early in the boot0 hook, *before* + * resetting to AArch64. + */ + +/* + * The FEL routines in BROM run in AArch32. + * Reset back into 32-bit mode here and restore the saved FEL state + * afterwards. + * Resetting back into AArch32/EL3 using the RMR always enters the BROM, + * but we can use the CPU hotplug mechanism to branch back to our code + * immediately. + */ +ENTRY(return_to_fel) + /* + * the RMR reset will clear all registers, so save the arguments + * (LR and SP) in the fel_stash structure, which we read anyways later + */ + adr x2, fel_stash + str w0, [x2] + str w1, [x2, #4] + + adr x1, fel_stash_addr // to find the fel_stash address in AA32 + str w2, [x1] + + ldr x0, =0xfa50392f // CPU hotplug magic +#ifdef CONFIG_MACH_SUN50I_H6 + ldr x2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG + str w0, [x2], #0x4 +#else + ldr x2, =(SUNXI_CPUCFG_BASE + 0x1a4) // offset for CPU hotplug base + str w0, [x2, #0x8] +#endif + adr x0, back_in_32 + str w0, [x2] + + dsb sy + isb sy + mov x0, #2 // RMR reset into AArch32 + dsb sy + msr RMR_EL3, x0 + isb sy +1: wfi + b 1b + +/* AArch32 code to restore the state from fel_stash and return back to FEL. */ +back_in_32: + .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address + .word 0xe5901008 // ldr r1, [r0, #8] + .word 0xe129f001 // msr CPSR_fc, r1 + .word 0xf57ff06f // isb + .word 0xe590d000 // ldr sp, [r0] + .word 0xe590e004 // ldr lr, [r0, #4] + .word 0xe5901010 // ldr r1, [r0, #16] + .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR + .word 0xe590100c // ldr r1, [r0, #12] + .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR + .word 0xf57ff06f // isb + .word 0xe12fff1e // bx lr ; return to FEL +fel_stash_addr: + .word 0x00000000 // receives fel_stash addr, by AA64 code above +ENDPROC(return_to_fel) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 3a04dce56f..7f29aa4725 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -26,7 +26,7 @@ #endif #include <fsl_sec.h> #include <asm/arch-fsl-layerscape/soc.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) #include <asm/armv8/sec_firmware.h> #endif #include <asm/arch/speed.h> @@ -81,7 +81,7 @@ void ft_fixup_cpu(void *blob) "device_type", "cpu", 4); } -#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) int node; u32 psci_ver; @@ -383,7 +383,7 @@ static void fdt_fixup_msi(void *blob) } #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) /* Remove JR node used by SEC firmware */ void fdt_fixup_remove_jr(void *blob) { @@ -490,7 +490,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) else { ccsr_sec_t __iomem *sec; -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) fdt_fixup_remove_jr(blob); fdt_fixup_kaslr(blob); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a519f6ed67..d8803738f1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -192,6 +192,7 @@ ENTRY(lowlevel_init) #endif /* Initialize GIC Secure Bank Status */ +#if !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f bl get_gic_offset @@ -205,6 +206,7 @@ ENTRY(lowlevel_init) bl gic_init_secure_percpu #endif #endif +#endif 100: branch_if_master x0, x1, 2f diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index 1ddb267093..2285296ea0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -16,7 +16,7 @@ #elif defined(CONFIG_FSL_LSCH2) #include <asm/arch/immap_lsch2.h> #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) #include <asm/armv8/sec_firmware.h> #endif #ifdef CONFIG_CHAIN_OF_TRUST diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 77724336d6..215ed9759e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -38,6 +38,9 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_BUILD +/* Define board data structure */ +static struct bd_info bdata __attribute__ ((section(".data"))); + void spl_board_init(void) { #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2) @@ -74,7 +77,7 @@ void board_init_f(ulong dummy) get_clocks(); preloader_console_init(); - spl_set_bd(); + gd->bd = &bdata; #ifdef CONFIG_SYS_I2C #ifdef CONFIG_SPL_I2C_SUPPORT |