diff options
Diffstat (limited to 'arch/arm/cpu/arm920t/start.S')
| -rw-r--r-- | arch/arm/cpu/arm920t/start.S | 22 |
1 files changed, 4 insertions, 18 deletions
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index e2b5f2bff4..cba4a1f035 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -35,25 +35,11 @@ reset: orr r0, r0, #0xd3 msr cpsr, r0 -#if defined(CONFIG_AT91RM9200DK) - /* - * relocate exception table - */ - ldr r0, =_start - ldr r1, =0x0 - mov r2, #16 -copyex: - subs r2, r2, #1 - ldr r3, [r0], #4 - str r3, [r1], #4 - bne copyex -#endif - /* * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -78,7 +64,7 @@ c_runtime_cpu_setup: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -97,7 +83,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will @@ -109,4 +95,4 @@ cpu_init_crit: mov lr, ip #endif mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ |