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-rw-r--r--arch/arm/dts/stm32mp15-pinctrl.dtsi61
-rw-r--r--arch/arm/dts/stm32mp151.dtsi39
-rw-r--r--arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi1
-rw-r--r--arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi2
-rw-r--r--arch/arm/mach-stm32mp/Kconfig4
-rw-r--r--arch/arm/mach-stm32mp/cmd_stm32key.c239
-rw-r--r--arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c10
-rw-r--r--arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c6
-rw-r--r--arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h1
-rw-r--r--arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c2
-rw-r--r--arch/arm/mach-stm32mp/cpu.c16
-rw-r--r--arch/arm/mach-stm32mp/include/mach/stm32.h4
-rw-r--r--arch/arm/mach-stm32mp/syscon.c14
-rw-r--r--board/st/stm32mp1/stm32mp1.c35
-rw-r--r--configs/stm32mp15_basic_defconfig3
-rw-r--r--configs/stm32mp15_trusted_defconfig3
-rw-r--r--drivers/clk/clk_stm32mp1.c1
-rw-r--r--include/configs/stm32mp1.h4
18 files changed, 369 insertions, 76 deletions
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index 20a59e8f7a..060baa8b7e 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1273,6 +1273,18 @@
};
};
+ sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
@@ -1299,6 +1311,17 @@
};
};
+ sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
@@ -1868,10 +1891,15 @@
usart2_idle_pins_c: usart2-idle-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
bias-disable;
};
@@ -1917,10 +1945,15 @@
usart3_idle_pins_b: usart3-idle-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
+ pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
@@ -1953,10 +1986,15 @@
usart3_idle_pins_c: usart3-idle-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
+ pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
@@ -2018,6 +2056,23 @@
};
};
+ i2c6_pins_a: i2c6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */
+ <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c6_sleep_pins_a: i2c6-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */
+ <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */
+ };
+ };
+
spi1_pins_a: spi1-0 {
pins1 {
pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index b564fc6269..177927d14e 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -470,32 +470,36 @@
usart2: serial@4000e000 {
compatible = "st,stm32h7-uart";
reg = <0x4000e000 0x400>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
+ wakeup-source;
status = "disabled";
};
usart3: serial@4000f000 {
compatible = "st,stm32h7-uart";
reg = <0x4000f000 0x400>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
+ wakeup-source;
status = "disabled";
};
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
+ wakeup-source;
status = "disabled";
};
uart5: serial@40011000 {
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
+ wakeup-source;
status = "disabled";
};
@@ -511,6 +515,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x1>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -526,6 +531,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x2>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -541,6 +547,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x4>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -556,6 +563,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x10>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -595,16 +603,18 @@
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
+ wakeup-source;
status = "disabled";
};
uart8: serial@40019000 {
compatible = "st,stm32h7-uart";
reg = <0x40019000 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
+ wakeup-source;
status = "disabled";
};
@@ -683,8 +693,9 @@
usart6: serial@44003000 {
compatible = "st,stm32h7-uart";
reg = <0x44003000 0x400>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
+ wakeup-source;
status = "disabled";
};
@@ -1065,7 +1076,7 @@
};
};
- sdmmc3: sdmmc@48004000 {
+ sdmmc3: mmc@48004000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
@@ -1398,7 +1409,7 @@
status = "disabled";
};
- sdmmc1: sdmmc@58005000 {
+ sdmmc1: mmc@58005000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
@@ -1413,7 +1424,7 @@
status = "disabled";
};
- sdmmc2: sdmmc@58007000 {
+ sdmmc2: mmc@58007000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
@@ -1451,11 +1462,13 @@
"mac-clk-tx",
"mac-clk-rx",
"eth-ck",
+ "ptp_ref",
"ethstp";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
<&rcc ETHCK_K>,
+ <&rcc ETHPTP_K>,
<&rcc ETHSTP>;
st,syscon = <&syscfg 0x4>;
snps,mixed-burst;
@@ -1512,6 +1525,7 @@
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <0>;
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
@@ -1534,8 +1548,9 @@
usart1: serial@5c000000 {
compatible = "st,stm32h7-uart";
reg = <0x5c000000 0x400>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
+ wakeup-source;
status = "disabled";
};
@@ -1565,6 +1580,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x8>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -1605,6 +1621,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x20>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 6787619290..7dcc96c19c 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -10,7 +10,6 @@
/ {
aliases {
i2c3 = &i2c4;
- mmc0 = &sdmmc1;
usb0 = &usbotg_hs;
};
config {
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index f3002e995b..46a43371bd 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -10,8 +10,6 @@
/ {
aliases {
i2c3 = &i2c4;
- mmc0 = &sdmmc1;
- mmc1 = &sdmmc2;
};
config {
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 7c25266f33..0e59931679 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -174,10 +174,12 @@ config STM32_ETZPC
config CMD_STM32KEY
bool "command stm32key to fuse public key hash"
- default y
+ default n
help
fuse public key hash in corresponding fuse used to authenticate
binary.
+ This command is used to evaluate the secure boot on stm32mp SOC,
+ it is deactivated by default in real products.
config PRE_CON_BUF_ADDR
default 0xC02FF000
diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
index 42fdc11238..50840b0f38 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
@@ -11,13 +11,30 @@
#include <dm/device.h>
#include <dm/uclass.h>
-#define STM32_OTP_HASH_KEY_START 24
-#define STM32_OTP_HASH_KEY_SIZE 8
+/* Closed device : bit 6 of OPT0*/
+#define STM32_OTP_CLOSE_ID 0
+#define STM32_OTP_CLOSE_MASK BIT(6)
+
+/* HASH of key: 8 OTPs, starting with OTP24) */
+#define STM32_OTP_HASH_KEY_START 24
+#define STM32_OTP_HASH_KEY_SIZE 8
+
+static int get_misc_dev(struct udevice **dev)
+{
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), dev);
+ if (ret)
+ log_err("Can't find stm32mp_bsec driver\n");
+
+ return ret;
+}
static void read_hash_value(u32 addr)
{
int i;
+ printf("Read KEY at 0x%x\n", addr);
for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i,
__be32_to_cpu(*(u32 *)addr));
@@ -25,32 +42,101 @@ static void read_hash_value(u32 addr)
}
}
-static void fuse_hash_value(u32 addr, bool print)
+static int read_hash_otp(bool print, bool *locked, bool *closed)
{
struct udevice *dev;
- u32 word, val;
- int i, ret;
+ int i, word, ret;
+ int nb_invalid = 0, nb_zero = 0, nb_lock = 0;
+ u32 val, lock;
+ bool status;
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_DRIVER_GET(stm32mp_bsec),
- &dev);
- if (ret) {
- log_err("Can't find stm32mp_bsec driver\n");
- return;
+ ret = get_misc_dev(&dev);
+ if (ret)
+ return ret;
+
+ for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; i++, word++) {
+ ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret != 4)
+ val = ~0x0;
+ ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
+ if (ret != 4)
+ lock = -1;
+ if (print)
+ printf("OTP HASH %i: %x lock : %d\n", word, val, lock);
+ if (val == ~0x0)
+ nb_invalid++;
+ else if (val == 0x0)
+ nb_zero++;
+ if (lock == 1)
+ nb_lock++;
}
- for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
+ word = STM32_OTP_CLOSE_ID;
+ ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret != 4)
+ val = 0x0;
+ ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
+ if (ret != 4)
+ lock = -1;
+
+ status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK;
+ if (closed)
+ *closed = status;
+ if (print)
+ printf("OTP %d: closed status: %d lock : %d\n", word, status, lock);
+
+ status = (nb_lock == STM32_OTP_HASH_KEY_SIZE);
+ if (locked)
+ *locked = status;
+ if (!status && print)
+ printf("Hash of key is not locked!\n");
+
+ if (nb_invalid == STM32_OTP_HASH_KEY_SIZE) {
if (print)
- printf("Fuse OTP %i : %x\n",
- STM32_OTP_HASH_KEY_START + i,
- __be32_to_cpu(*(u32 *)addr));
+ printf("Hash of key is invalid!\n");
+ return -EINVAL;
+ }
+ if (nb_zero == STM32_OTP_HASH_KEY_SIZE) {
+ if (print)
+ printf("Hash of key is free!\n");
+ return -ENOENT;
+ }
+
+ return 0;
+}
- word = STM32_OTP_HASH_KEY_START + i;
+static int fuse_hash_value(u32 addr, bool print)
+{
+ struct udevice *dev;
+ u32 word, val;
+ int i, ret;
+
+ ret = get_misc_dev(&dev);
+ if (ret)
+ return ret;
+
+ for (i = 0, word = STM32_OTP_HASH_KEY_START;
+ i < STM32_OTP_HASH_KEY_SIZE;
+ i++, word++, addr += 4) {
val = __be32_to_cpu(*(u32 *)addr);
- misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (print)
+ printf("Fuse OTP %i : %x\n", word, val);
- addr += 4;
+ ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret != 4) {
+ log_err("Fuse OTP %i failed\n", word);
+ return ret;
+ }
+ /* on success, lock the OTP for HASH key */
+ val = 1;
+ ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4);
+ if (ret != 4) {
+ log_err("Lock OTP %i failed\n", word);
+ return ret;
+ }
}
+
+ return 0;
}
static int confirm_prog(void)
@@ -67,36 +153,117 @@ static int confirm_prog(void)
return 0;
}
-static int do_stm32key(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
u32 addr;
- const char *op = argc >= 2 ? argv[1] : NULL;
- int confirmed = argc > 3 && !strcmp(argv[2], "-y");
- argc -= 2 + confirmed;
- argv += 2 + confirmed;
+ if (argc == 1) {
+ read_hash_otp(true, NULL, NULL);
+ return CMD_RET_SUCCESS;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ if (!addr)
+ return CMD_RET_USAGE;
+
+ read_hash_value(addr);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ u32 addr;
+ bool yes = false, lock, closed;
- if (argc < 1)
+ if (argc < 2)
return CMD_RET_USAGE;
- addr = simple_strtoul(argv[0], NULL, 16);
+ if (argc == 3) {
+ if (strcmp(argv[1], "-y"))
+ return CMD_RET_USAGE;
+ yes = true;
+ }
+
+ addr = simple_strtoul(argv[argc - 1], NULL, 16);
if (!addr)
return CMD_RET_USAGE;
- if (!strcmp(op, "read"))
- read_hash_value(addr);
+ if (read_hash_otp(!yes, &lock, &closed) != -ENOENT) {
+ printf("Error: can't fuse again the OTP\n");
+ return CMD_RET_FAILURE;
+ }
- if (!strcmp(op, "fuse")) {
- if (!confirmed && !confirm_prog())
- return CMD_RET_FAILURE;
- fuse_hash_value(addr, !confirmed);
+ if (lock || closed) {
+ printf("Error: invalid OTP configuration (lock=%d, closed=%d)\n", lock, closed);
+ return CMD_RET_FAILURE;
}
+ if (!yes && !confirm_prog())
+ return CMD_RET_FAILURE;
+
+ if (fuse_hash_value(addr, !yes))
+ return CMD_RET_FAILURE;
+
+ printf("Hash key updated !\n");
+
return CMD_RET_SUCCESS;
}
-U_BOOT_CMD(stm32key, 4, 1, do_stm32key,
- "Fuse ST Hash key",
- "read <addr>: Read the hash store at addr in memory\n"
- "stm32key fuse [-y] <addr> : Fuse hash store at addr in otp\n");
+static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ bool yes, lock, closed;
+ struct udevice *dev;
+ u32 val;
+ int ret;
+
+ yes = false;
+ if (argc == 2) {
+ if (strcmp(argv[1], "-y"))
+ return CMD_RET_USAGE;
+ yes = true;
+ }
+
+ ret = read_hash_otp(!yes, &lock, &closed);
+ if (ret) {
+ if (ret == -ENOENT)
+ printf("Error: OTP not programmed!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (closed) {
+ printf("Error: already closed!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (!lock)
+ printf("Warning: OTP not locked!\n");
+
+ if (!yes && !confirm_prog())
+ return CMD_RET_FAILURE;
+
+ ret = get_misc_dev(&dev);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ val = STM32_OTP_CLOSE_MASK;
+ ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4);
+ if (ret != 4) {
+ printf("Error: can't update OTP\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Device is closed !\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+static char stm32key_help_text[] =
+ "read [<addr>]: Read the hash stored at addr in memory or in OTP\n"
+ "stm32key fuse [-y] <addr> : Fuse hash stored at addr in OTP\n"
+ "stm32key close [-y] : Close the device, the hash stored in OTP\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Fuse ST Hash key", stm32key_help_text,
+ U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read),
+ U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse),
+ U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close));
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
index feff73c79e..064f51b2c7 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
@@ -177,12 +177,12 @@ cleanup:
}
U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog,
+ "start communication with tools STM32Cubeprogrammer",
"<link> <dev> [<addr>] [<size>]\n"
- "start communication with tools STM32Cubeprogrammer on <link> with Flashlayout at <addr>",
- "<link> = serial|usb\n"
- "<dev> = device instance\n"
- "<addr> = address of flashlayout\n"
- "<size> = size of flashlayout\n"
+ " <link> = serial|usb\n"
+ " <dev> = device instance\n"
+ " <addr> = address of flashlayout\n"
+ " <size> = size of flashlayout (optional for image with STM32 header)\n"
);
bool stm32prog_get_tee_partitions(void)
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index f7c93a1298..96ebc6d978 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -1199,13 +1199,13 @@ static int dfu_init_entities(struct stm32prog_data *data)
}
if (!ret)
- ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, 512);
+ ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE);
if (!ret)
- ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, 512);
+ ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, OTP_SIZE);
if (!ret && CONFIG_IS_ENABLED(DM_PMIC))
- ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, 8);
+ ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE);
if (ret)
stm32prog_err("dfu init failed: %d", ret);
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
index efb51a3022..9d58cf0e2d 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
@@ -19,6 +19,7 @@
#define DEFAULT_ADDRESS 0xFFFFFFFF
+#define CMD_SIZE 512
#define OTP_SIZE 1024
#define PMIC_SIZE 8
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
index d4a3f7ea16..e8acc302f9 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
@@ -178,7 +178,7 @@ int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
switch (dfu->data.virt.dev_num) {
case PHASE_CMD:
- *size = 512;
+ *size = CMD_SIZE;
break;
case PHASE_OTP:
*size = OTP_SIZE;
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 592bfd413d..f6ed2ce0e4 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -483,6 +483,11 @@ static void setup_boot_mode(void)
STM32_UART7_BASE,
STM32_UART8_BASE
};
+ const u32 sdmmc_addr[] = {
+ STM32_SDMMC1_BASE,
+ STM32_SDMMC2_BASE,
+ STM32_SDMMC3_BASE
+ };
char cmd[60];
u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
u32 boot_mode =
@@ -525,7 +530,16 @@ static void setup_boot_mode(void)
break;
case BOOT_FLASH_SD:
case BOOT_FLASH_EMMC:
- sprintf(cmd, "%d", instance);
+ if (instance > ARRAY_SIZE(sdmmc_addr))
+ break;
+ /* search associated sdmmc node in devicetree */
+ sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
+ printf("mmc%d = %s not found in device tree!\n",
+ instance, cmd);
+ break;
+ }
+ sprintf(cmd, "%d", dev_seq(dev));
env_set("boot_device", "mmc");
env_set("boot_instance", cmd);
break;
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 5fdb893b0e..c11a9903f2 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -32,6 +32,10 @@
#define STM32_UART7_BASE 0x40018000
#define STM32_UART8_BASE 0x40019000
+#define STM32_SDMMC1_BASE 0x58005000
+#define STM32_SDMMC2_BASE 0x58007000
+#define STM32_SDMMC3_BASE 0x48004000
+
#define STM32_SYSRAM_BASE 0x2FFC0000
#define STM32_SYSRAM_SIZE SZ_256K
diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c
index 3e61ce4097..a0e8e1dfdc 100644
--- a/arch/arm/mach-stm32mp/syscon.c
+++ b/arch/arm/mach-stm32mp/syscon.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch/stm32.h>
@@ -14,9 +15,22 @@ static const struct udevice_id stm32mp_syscon_ids[] = {
{ }
};
+static int stm32mp_syscon_probe(struct udevice *dev)
+{
+ struct clk_bulk clk_bulk;
+ int ret;
+
+ ret = clk_get_bulk(dev, &clk_bulk);
+ if (!ret)
+ clk_enable_bulk(&clk_bulk);
+
+ return 0;
+}
+
U_BOOT_DRIVER(syscon_stm32mp) = {
.name = "stmp32mp_syscon",
.id = UCLASS_SYSCON,
.of_match = stm32mp_syscon_ids,
.bind = dm_scan_fdt_dev,
+ .probe = stm32mp_syscon_probe,
};
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 18b8870269..2faf5c81b4 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -841,6 +841,31 @@ const char *env_ext4_get_intf(void)
}
}
+int mmc_get_boot(void)
+{
+ struct udevice *dev;
+ u32 boot_mode = get_bootmode();
+ unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ char cmd[20];
+ const u32 sdmmc_addr[] = {
+ STM32_SDMMC1_BASE,
+ STM32_SDMMC2_BASE,
+ STM32_SDMMC3_BASE
+ };
+
+ if (instance > ARRAY_SIZE(sdmmc_addr))
+ return 0;
+
+ /* search associated sdmmc node in devicetree */
+ snprintf(cmd, sizeof(cmd), "mmc@%x", sdmmc_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
+ log_err("mmc%d = %s not found in device tree!\n", instance, cmd);
+ return 0;
+ }
+
+ return dev_seq(dev);
+};
+
const char *env_ext4_get_dev_part(void)
{
static char *const env_dev_part =
@@ -854,22 +879,16 @@ const char *env_ext4_get_dev_part(void)
if (strlen(env_dev_part) > 0)
return env_dev_part;
- u32 bootmode = get_bootmode();
-
- return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1];
+ return dev_part[mmc_get_boot()];
}
int mmc_get_env_dev(void)
{
- u32 bootmode;
-
if (CONFIG_SYS_MMC_ENV_DEV >= 0)
return CONFIG_SYS_MMC_ENV_DEV;
- bootmode = get_bootmode();
-
/* use boot instance to select the correct mmc device identifier */
- return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ return mmc_get_boot();
}
#if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index e199f2b7f9..ab02c35b12 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TARGET_ST_STM32MP15x=y
+CONFIG_CMD_STM32KEY=y
CONFIG_CMD_STM32PROG=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
@@ -54,6 +55,7 @@ CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
@@ -168,7 +170,6 @@ CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
-# CONFIG_HEXDUMP is not set
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_LMB_MEMORY_REGIONS=2
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 5bc5e79400..a58ea91d3e 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0x280000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_TARGET_ST_STM32MP15x=y
+CONFIG_CMD_STM32KEY=y
CONFIG_CMD_STM32PROG=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
@@ -37,6 +38,7 @@ CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
@@ -150,7 +152,6 @@ CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
-# CONFIG_HEXDUMP is not set
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_LMB_MEMORY_REGIONS=2
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 0c0ef366a1..48c9514ba0 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -540,6 +540,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index 440efa1a55..2e7f49e7bb 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -155,7 +155,7 @@
/*
* memory layout for 32M uncompressed/compressed kernel,
- * 1M fdt, 1M script, 1M pxe and 1M for splashimage
+ * 1M fdt, 1M script, 1M pxe and 1M for overlay
* and the ramdisk at the end.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -163,7 +163,7 @@
"fdt_addr_r=0xc4000000\0" \
"scriptaddr=0xc4100000\0" \
"pxefile_addr_r=0xc4200000\0" \
- "splashimage=0xc4300000\0" \
+ "fdtoverlay_addr_r=0xc4300000\0" \
"ramdisk_addr_r=0xc4400000\0" \
"altbootcmd=run bootcmd\0" \
"env_check=if env info -p -d -q; then env save; fi\0" \
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-02 10:57:37 +0000