diff options
1454 files changed, 5354 insertions, 21985 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 915d5115b1..bc2b437bd9 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -261,6 +261,9 @@ stages: evb_ast2500: TEST_PY_BD: "evb-ast2500" TEST_PY_ID: "--id qemu" + evb_ast2600: + TEST_PY_BD: "evb-ast2600" + TEST_PY_ID: "--id qemu" vexpress_ca9x4: TEST_PY_BD: "vexpress_ca9x4" TEST_PY_ID: "--id qemu" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c6a608f7e2..f9cd417507 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -272,6 +272,12 @@ evb-ast2500 test.py: TEST_PY_ID: "--id qemu" <<: *buildman_and_testpy_dfn +evb-ast2600 test.py: + variables: + TEST_PY_BD: "evb-ast2600" + TEST_PY_ID: "--id qemu" + <<: *buildman_and_testpy_dfn + sandbox_flattree test.py: variables: TEST_PY_BD: "sandbox_flattree" diff --git a/MAINTAINERS b/MAINTAINERS index bfa3bfbc1f..a6a16a3053 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -348,13 +348,6 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: drivers/serial/serial_mvebu_a3700.c -ARM MARVELL PXA -M: Marek Vasut <marex@denx.de> -S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-pxa.git -F: arch/arm/cpu/pxa/ -F: arch/arm/include/asm/arch-pxa/ - ARM MEDIATEK M: Ryder Lee <ryder.lee@mediatek.com> M: Weijie Gao <weijie.gao@mediatek.com> @@ -640,6 +633,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal/ F: drivers/net/xilinx_axi_mrmac.* F: drivers/soc/soc_xilinx_versal.c +F: drivers/spi/cadence_ospi_versal.c F: drivers/watchdog/xilinx_wwdt.c N: (?<!uni)versal @@ -673,6 +673,12 @@ else include/config/auto.conf: ; endif # $(dot-config) +ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG +KBUILD_HOSTCFLAGS := -Wall -Wstrict-prototypes -Og -g -fomit-frame-pointer \ + $(HOST_LFS_CFLAGS) $(HOSTCFLAGS) +KBUILD_HOSTCXXFLAGS := -Og -g $(HOST_LFS_CFLAGS) $(HOSTCXXFLAGS) +endif + # # Xtensa linker script cannot be preprocessed with -ansi because of # preprocessor operations on strings that don't make C identifiers. @@ -2207,7 +2213,7 @@ CLEAN_DIRS += $(MODVERDIR) \ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ - include/generated/env.in drivers/video/u_boot_logo.S \ + include/generated/env.* drivers/video/u_boot_logo.S \ tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \ u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \ lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \ @@ -371,10 +371,6 @@ The following options need to be configured: In this mode, a single differential clock is used to supply clocks to the sysclock, ddrclock and usbclock. - CONFIG_SYS_CPC_REINIT_F - This CONFIG is defined when the CPC is configured as SRAM at the - time of U-Boot entry and is required to be re-initialized. - - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN @@ -388,10 +384,6 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR_ADDR Freescale DDR memory-mapped register base. - CONFIG_SYS_FSL_DDR_EMU - Specify emulator support for DDR. Some DDR features such as - deskew training are not available. - CONFIG_SYS_FSL_DDRC_GEN1 Freescale DDR1 controller. @@ -664,18 +656,6 @@ The following options need to be configured: CONFIG_SCSI) you must configure support for at least one non-MTD partition type as well. -- LBA48 Support - CONFIG_LBA48 - - Set this to enable support for disks larger than 137GB - Also look at CONFIG_SYS_64BIT_LBA. - Whithout these , LBA48 support uses 32bit variables and will 'only' - support disks up to 2.1TB. - - CONFIG_SYS_64BIT_LBA: - When enabled, makes the IDE subsystem use 64bit sector addresses. - Default is 32bit. - - NETWORK Support (PCI): CONFIG_E1000_SPI Utility code for direct access to the SPI bus on Intel 8257x. @@ -793,9 +773,6 @@ The following options need to be configured: Supported are USB Keyboards and USB Floppy drives (TEAC FD-05PUB). - CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the - txfilltuning field in the EHCI controller on reset. - CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2 HW module registers. @@ -869,13 +846,6 @@ The following options need to be configured: the appropriate value in Hz. - MMC Support: - The MMC controller on the Intel PXA is supported. To - enable this define CONFIG_MMC. The MMC can be - accessed from the boot prompt by mapping the device - to physical memory similar to flash. Command line is - enabled with CONFIG_CMD_MMC. The MMC driver also works with - the FAT fs. This is enabled with CONFIG_CMD_FAT. - CONFIG_SH_MMCIF Support for Renesas on-chip MMCIF controller @@ -1321,11 +1291,6 @@ The following options need to be configured: will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CONFIG_SYS_SPD_BUS_NUM - - If defined, then this indicates the I2C bus number for DDR SPD. - If not defined, then U-Boot assumes that SPD is on I2C bus 0. - CONFIG_SYS_RTC_BUS_NUM If defined, then this indicates the I2C bus number for the RTC. @@ -1365,10 +1330,6 @@ The following options need to be configured: Enables support for FPGA family. (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX) - CONFIG_FPGA_COUNT - - Specify the number of FPGA devices to support. - CONFIG_SYS_FPGA_PROG_FEEDBACK Enable printing of hash marks during FPGA configuration. @@ -1537,20 +1498,6 @@ The following options need to be configured: overwriting the architecture dependent default settings. -- Frame Buffer Address: - CONFIG_FB_ADDR - - Define CONFIG_FB_ADDR if you want to use specific - address for frame buffer. This is typically the case - when using a graphics controller has separate video - memory. U-Boot will then place the frame buffer at - the given address instead of dynamically reserving it - in system RAM by calling lcd_setmem(), which grabs - the memory for the frame buffer depending on the - configured panel size. - - Please see board_init_f function. - - Automatic software updates via TFTP server CONFIG_UPDATE_TFTP CONFIG_UPDATE_TFTP_CNT_MAX @@ -1789,12 +1736,6 @@ Configuration Settings: Non-cached memory is only supported on 32-bit ARM at present. -- CONFIG_SYS_BOOTM_LEN: - Normally compressed uImages are limited to an - uncompressed size of 8 MBytes. If this is not enough, - you can define CONFIG_SYS_BOOTM_LEN in your board config file - to adjust this setting to your needs. - - CONFIG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by @@ -1807,11 +1748,6 @@ Configuration Settings: CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined, then the value in "bootm_size" will be used instead. -- CONFIG_SYS_BOOT_RAMDISK_HIGH: - Enable initrd_high functionality. If defined then the - initrd_high feature is enabled and the bootm ramdisk subcommand - is enabled. - - CONFIG_SYS_BOOT_GET_CMDLINE: Enables allocating and saving kernel cmdline in space between "bootm_low" and "bootm_low" + BOOTMAPSZ. @@ -1892,14 +1828,6 @@ Configuration Settings: while unprotecting/erasing/programming. Please only enable this option if you really know what you are doing. -- CONFIG_ENV_MAX_ENTRIES - - Maximum number of entries in the hash table that is used - internally to store the environment settings. The default - setting is supposed to be generous and should work in most - cases. This setting can be used to tune behaviour; see - lib/hashtable.c for details. - - CONFIG_ENV_FLAGS_LIST_DEFAULT - CONFIG_ENV_FLAGS_LIST_STATIC Enable validation of the values given to environment variables when @@ -2115,12 +2043,6 @@ Low Level (hardware related) configuration options: one, specify here. Note that the value must resolve to something your driver can deal with. -- CONFIG_SYS_DDR_RAW_TIMING - Get DDR timing information from other than SPD. Common with - soldered DDR chips onboard without SPD. DDR raw timing - parameters are extracted from datasheet and hard-coded into - header files or board specific files. - - CONFIG_FSL_DDR_INTERACTIVE Enable interactive DDR debugging. See doc/README.fsl-ddr. @@ -2130,10 +2052,6 @@ Low Level (hardware related) configuration options: - CONFIG_FSL_DDR_BIST Enable built-in memory test for Freescale DDR controllers. -- CONFIG_SYS_83XX_DDR_USES_CS0 - Only for 83xx systems. If specified, then DDR should - be configured using CS0 and CS1 instead of CS2 and CS3. - - CONFIG_RMII Enable RMII mode for all FECs. Note that this is a global option, we can't @@ -2179,11 +2097,6 @@ Low Level (hardware related) configuration options: proper). Code that needs stage-specific behavior should check this. -- CONFIG_SYS_MPC85XX_NO_RESETVEC - Only for 85xx systems. If this variable is specified, the section - .resetvec is not kept and the section .bootpg is placed in the - previous 4k of the .text section. - - CONFIG_ARCH_MAP_SYSMEM Generally U-Boot (and in particular the md command) uses effective address. It is therefore not necessary to regard diff --git a/arch/Kconfig b/arch/Kconfig index d35a590f93..6495e780fe 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -451,6 +451,12 @@ source "arch/x86/Kconfig" source "arch/xtensa/Kconfig" source "arch/riscv/Kconfig" +if ARM || M68K || PPC + +source "arch/Kconfig.nxp" + +endif + source "board/keymile/Kconfig" if MIPS || MICROBLAZE diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp new file mode 100644 index 0000000000..d3ebbff43b --- /dev/null +++ b/arch/Kconfig.nxp @@ -0,0 +1,241 @@ +config NXP_ESBC + bool "NXP ESBC (secure boot) functionality" + help + Enable Freescale Secure Boot feature. Normally selected by defconfig. + If unsure, do not change. + +menu "Chain of trust / secure boot options" + depends on !FIT_SIGNATURE && NXP_ESBC + +config CHAIN_OF_TRUST + select FSL_CAAM + select ARCH_MISC_INIT + select FSL_SEC_MON + select SPL_BOARD_INIT if (ARM && SPL) + select SPL_HASH if (ARM && SPL) + select SHA_HW_ACCEL + select SHA_PROG_HW_ACCEL + select ENV_IS_NOWHERE + select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT + select CMD_EXT4 if ARM + select CMD_EXT4_WRITE if ARM + imply CMD_BLOB + imply CMD_HASH if ARM + def_bool y + +config CMD_ESBC_VALIDATE + bool "Enable the 'esbc_validate' and 'esbc_halt' commands" + default y + help + This option enables two commands used for secure booting: + + esbc_validate - validate signature using RSA verification + esbc_halt - put the core in spin loop (Secure Boot Only) + +config ESBC_HDR_LS + bool + +config ESBC_ADDR_64BIT + def_bool y + depends on ESBC_HDR_LS && FSL_LAYERSCAPE + help + For Layerscape based platforms, ESBC image Address in Header is 64bit. + +config SYS_FSL_SFP_BE + def_bool y + depends on PPC || FSL_LSCH2 || ARCH_LS1021A + +config SYS_FSL_SFP_LE + def_bool y + depends on !SYS_FSL_SFP_BE + +choice + prompt "SFP IP revision" + default SYS_FSL_SFP_VER_3_0 if PPC + default SYS_FSL_SFP_VER_3_4 + +config SYS_FSL_SFP_VER_3_0 + bool "SFP version 3.0" + +config SYS_FSL_SFP_VER_3_2 + bool "SFP version 3.2" + +config SYS_FSL_SFP_VER_3_4 + bool "SFP version 3.4" + +endchoice + +config SPL_UBOOT_KEY_HASH + string "Non-SRK key hash for U-Boot public/private key pair" + depends on SPL + default "" + help + Set the key hash for U-Boot here if public/private key pair used to + sign U-boot are different from the SRK hash put in the fuse. Example + of a key hash is + 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b. + Otherwise leave this empty. + +if PPC + +config BOOTSCRIPT_COPY_RAM + bool "Secure boot copies boot script to RAM" + help + On systems that support chain of trust booting, a number of addresses + are required to set variables that are used in the copying and then + verification of different parts of the system. If enabled, the subsequent + options are for what location to use in each step. + +config BS_ADDR_DEVICE + hex "Address in RAM for bs_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_SIZE + hex "The size of bs_size which is the amount read from bs_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_ADDR_RAM + hex "Address in RAM for bs_ram" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_ADDR_DEVICE + hex "Address in RAM for bs_hdr_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_SIZE + hex "The size of bs_hdr_size which is the amount read from bs_hdr_device" + depends on BOOTSCRIPT_COPY_RAM + +config BS_HDR_ADDR_RAM + hex "Address in RAM for bs_hdr_ram" + depends on BOOTSCRIPT_COPY_RAM + +config BOOTSCRIPT_HDR_ADDR + hex "CONFIG_BOOTSCRIPT_HDR_ADDR" + default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM + +endif + +config SYS_FSL_SRK_LE + def_bool y + depends on ARM + +config KEY_REVOCATION + def_bool y + +endmenu + +comment "Other functionality shared between NXP SoCs" + +config DEEP_SLEEP + bool "Enable SoC deep sleep feature" + depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A + default y + help + Indicates this SoC supports deep sleep feature. If deep sleep is + supported, core will start to execute uboot when wakes up. + +config LAYERSCAPE_NS_ACCESS + bool "Layerscape non-secure access support" + depends on ARCH_LS1021A || FSL_LSCH2 + +config PCIE1 + bool "PCIe controller #1" + depends on LAYERSCAPE_NS_ACCESS || PPC + +config PCIE2 + bool "PCIe controller #2" + depends on LAYERSCAPE_NS_ACCESS || PPC + +config PCIE3 + bool "PCIe controller #3" + depends on LAYERSCAPE_NS_ACCESS || PPC + +config PCIE4 + bool "PCIe controller #4" + depends on LAYERSCAPE_NS_ACCESS || PPC + +config FSL_USE_PCA9547_MUX + bool "Enable PCA9547 I2C Mux on Freescale boards" + depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 + help + This option enables the PCA9547 I2C mux on Freescale boards. + +config VID + bool "Enable Freescale VID" + depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C) + help + This option enables setting core voltage based on individual + values saved in SoC fuses. + +config SPL_VID + bool "Enable Freescale VID in SPL" + depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C) + help + This option enables setting core voltage based on individual + values saved in SoC fuses, in SPL. + +if VID || SPL_VID + +config VID_FLS_ENV + string "Environment variable for overriding VDD" + help + This option allows for specifying the environment variable + to check to override VDD information. + +config VOL_MONITOR_INA220 + bool "Enable the INA220 voltage monitor read" + help + This option enables INA220 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_IR36021_READ + bool "Enable the IR36021 voltage monitor read" + help + This option enables IR36021 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_IR36021_SET + bool "Enable the IR36021 voltage monitor set" + help + This option enables IR36021 voltage monitor set + functionality. It is used by the common VID driver. + +config VOL_MONITOR_LTC3882_READ + bool "Enable the LTC3882 voltage monitor read" + help + This option enables LTC3882 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_LTC3882_SET + bool "Enable the LTC3882 voltage monitor set" + help + This option enables LTC3882 voltage monitor set + functionality. It is used by the common VID driver. + +config VOL_MONITOR_ISL68233_READ + bool "Enable the ISL68233 voltage monitor read" + help + This option enables ISL68233 voltage monitor read + functionality. It is used by the common VID driver. + +config VOL_MONITOR_ISL68233_SET + bool "Enable the ISL68233 voltage monitor set" + help + This option enables ISL68233 voltage monitor set + functionality. It is used by the common VID driver. + +endif + +config FSL_QIXIS + bool "Enable QIXIS support" + depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 + +config QIXIS_I2C_ACCESS + bool "Access to QIXIS is over i2c" + depends on FSL_QIXIS + default y + +config HAS_FSL_DR_USB + def_bool y + depends on USB_EHCI_HCD && PPC diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h index 46e94be141..afdfcaa78b 100644 --- a/arch/arc/include/asm/config.h +++ b/arch/arc/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef __ASM_ARC_CONFIG_H_ #define __ASM_ARC_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif /*__ASM_ARC_CONFIG_H_ */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dab785efad..434c5e98fa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -330,15 +330,6 @@ config CPU_V7R select SYS_ARM_MPU select SYS_CACHE_SHIFT_6 -config CPU_PXA - bool - select SYS_CACHE_SHIFT_5 - imply SYS_ARM_MMU - -config CPU_PXA27X - bool - select CPU_PXA - config CPU_SA1100 bool select SYS_CACHE_SHIFT_5 @@ -354,7 +345,6 @@ config SYS_CPU default "armv7" if CPU_V7A default "armv7" if CPU_V7R default "armv7m" if CPU_V7M - default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 default "armv8" if ARM64 @@ -369,14 +359,12 @@ config SYS_ARM_ARCH default 7 if CPU_V7A default 7 if CPU_V7M default 7 if CPU_V7R - default 5 if CPU_PXA default 4 if CPU_SA1100 default 8 if ARM64 choice prompt "Select the ARM data write cache policy" - default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ - CPU_PXA || RZA1 + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1 default SYS_ARM_CACHE_WRITEBACK config SYS_ARM_CACHE_WRITEBACK @@ -609,6 +597,9 @@ config ARM64_SUPPORT_AARCH32 help This ARM64 system supports AArch32 execution state. +config S5P + def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX + choice prompt "Target select" default TARGET_HIKEY @@ -996,11 +987,6 @@ config ARCH_MX6 imply SYS_THUMB_BUILD imply SPL_SEPARATE_BSS -if ARCH_MX6 -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" -endif - config ARCH_MX5 bool "Freescale MX5" select BOARD_EARLY_INIT_F @@ -1121,7 +1107,6 @@ config ARCH_SOCFPGA select SPL_DM_SERIAL select SPL_LIBCOMMON_SUPPORT select SPL_LIBGENERIC_SUPPORT - select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 select SPL_SERIAL @@ -2354,6 +2339,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/siemens/common/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" source "board/st/stv0991/Kconfig" @@ -2368,8 +2354,3 @@ source "board/xen/xenguest_arm64/Kconfig" source "arch/arm/Kconfig.debug" endmenu - -config SPL_LDSCRIPT - default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK - default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 - default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 64c58f4c4a..09fc318878 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -11,7 +11,6 @@ arch-$(CONFIG_CPU_ARM920T) =-march=armv4t arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te arch-$(CONFIG_CPU_SA1100) =-march=armv4 -arch-$(CONFIG_CPU_PXA) = arch-$(CONFIG_CPU_ARM1136) =-march=armv5t arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \ @@ -41,7 +40,6 @@ tune-$(CONFIG_CPU_ARM920T) = tune-$(CONFIG_CPU_ARM926EJS) = tune-$(CONFIG_CPU_ARM946ES) = tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100 -tune-$(CONFIG_CPU_PXA) =-mcpu=xscale tune-$(CONFIG_CPU_ARM1136) = tune-$(CONFIG_CPU_ARM1176) = tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index c496e64391..a901360fa7 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -41,12 +41,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config NXP_ESBC - bool "NXP_ESBC" - help - Enable Freescale Secure Boot feature. Normally selected - by defconfig. If unsure, do not change. - config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index bfe02389cd..0985420fe5 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -3,14 +3,13 @@ # Copyright (C) 2009 Samsung Electronics # Minkyu Kang <mk7.kang@samsung.com> +obj-$(CONFIG_PWM_S5P) += pwm.o ifdef CONFIG_ARCH_NEXELL -obj-$(CONFIG_PWM_NX) += pwm.o obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o else obj-y += cpu_info.o ifndef CONFIG_SPL_BUILD obj-y += timer.o obj-y += sromc.o -obj-$(CONFIG_PWM) += pwm.o endif endif diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 72d12b4e07..1305238c9d 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -76,6 +76,7 @@ config ARMV8_SEC_FIRMWARE_SUPPORT config SPL_ARMV8_SEC_FIRMWARE_SUPPORT bool "Enable ARMv8 secure monitor firmware framework support for SPL" + depends on SPL select SPL_FIT select SPL_OF_LIBFDT help @@ -83,6 +84,7 @@ config SPL_ARMV8_SEC_FIRMWARE_SUPPORT config SPL_RECOVER_DATA_SECTION bool "save/restore SPL data section" + depends on SPL help Say Y here to save SPL data section for cold boot, and restore at warm boot in SPL phase. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 80a1642447..602b624dca 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -26,6 +26,7 @@ config ARCH_LS1012A config ARCH_LS1028A bool select ARMV8_SET_SMPEN + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_LAYERSCAPE select FSL_LSCH3 select GICV3 @@ -138,6 +139,7 @@ config ARCH_LS1088A bool select ARMV8_SET_SMPEN select ARM_ERRATA_855873 if !TFABOOT + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_IFC select FSL_LAYERSCAPE select FSL_LSCH3 @@ -187,6 +189,7 @@ config ARCH_LS2080A select ARM_ERRATA_828024 select ARM_ERRATA_829520 select ARM_ERRATA_833471 + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_IFC select FSL_LAYERSCAPE select FSL_LSCH3 @@ -239,6 +242,7 @@ config ARCH_LS2080A config ARCH_LX2162A bool select ARMV8_SET_SMPEN + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_DDR_BIST select FSL_DDR_INTERACTIVE select FSL_LAYERSCAPE @@ -277,6 +281,7 @@ config ARCH_LX2162A config ARCH_LX2160A bool select ARMV8_SET_SMPEN + select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_DDR_BIST select FSL_DDR_INTERACTIVE select FSL_LAYERSCAPE @@ -456,11 +461,6 @@ config EMC2305 Enable the EMC2305 fan controller for configuration of fan speed. -config NXP_ESBC - bool "NXP_ESBC" - help - Enable Freescale Secure Boot feature - config QSPI_AHB_INIT bool "Init the QSPI AHB bus" help @@ -511,6 +511,11 @@ config DP_DDR_CTRL depends on SYS_FSL_HAS_DP_DDR default 2 if ARCH_LS2080A +config DP_DDR_DIMM_SLOTS_PER_CTLR + int + depends on SYS_FSL_HAS_DP_DDR + default 1 if ARCH_LS2080A + config DP_DDR_NUM_CTRLS int depends on SYS_FSL_HAS_DP_DDR @@ -701,9 +706,6 @@ config SYS_FSL_HAS_RGMII bool depends on SYS_FSL_EC1 || SYS_FSL_EC2 -config SPL_LDSCRIPT - default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A - config HAS_FSL_XHCI_USB bool help diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile deleted file mode 100644 index fab77325c7..0000000000 --- a/arch/arm/cpu/pxa/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -extra-y = start.o - -obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o - -obj-y += cpuinfo.o -obj-y += timer.o -obj-y += usb.o -obj-y += relocate.o -obj-y += cache.o diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c deleted file mode 100644 index a2ec5e28c7..0000000000 --- a/arch/arm/cpu/pxa/cache.c +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com> - */ - -#include <cpu_func.h> -#include <asm/cache.h> -#include <linux/types.h> -#include <common.h> - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void invalidate_dcache_all(void) -{ - /* Flush/Invalidate I cache */ - asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0)); - /* Flush/Invalidate D cache */ - asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); -} - -void flush_dcache_all(void) -{ - return invalidate_dcache_all(); -} - -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ - start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); - stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); - - while (start <= stop) { - asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); - start += CONFIG_SYS_CACHELINE_SIZE; - } -} - -void flush_dcache_range(unsigned long start, unsigned long stop) -{ - return invalidate_dcache_range(start, stop); -} -#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ -void invalidate_dcache_all(void) -{ -} - -void flush_dcache_all(void) -{ -} -#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ - -/* - * Stub implementations for l2 cache operations - */ - -__weak void l2_cache_disable(void) {} - -#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) -__weak void invalidate_l2_cache(void) {} -#endif diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk deleted file mode 100644 index e7b183674a..0000000000 --- a/arch/arm/cpu/pxa/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> - -# -# !WARNING! -# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from -# really small OneNAND memories where the mmap'd window is only 1KiB big. The -# .text.0 contains only the bare minimum needed to load the real SPL into SRAM. -# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd, -# they are not discarded. -# - -#ifdef CONFIG_SPL_BUILD -OBJCOPYFLAGS += -j .text.0 -j .text.1 -#endif diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c deleted file mode 100644 index 549b61d6e0..0000000000 --- a/arch/arm/cpu/pxa/cpuinfo.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PXA CPU information display - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <errno.h> -#include <linux/compiler.h> - -#define CPU_MASK_PXA_PRODID 0x000003f0 -#define CPU_MASK_PXA_REVID 0x0000000f - -#define CPU_MASK_PRODREV (CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID) - -#define CPU_VALUE_PXA25X 0x100 -#define CPU_VALUE_PXA27X 0x110 - -static uint32_t pxa_get_cpuid(void) -{ - uint32_t cpuid; - asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid)); - return cpuid; -} - -int cpu_is_pxa25x(void) -{ - uint32_t id = pxa_get_cpuid(); - id &= CPU_MASK_PXA_PRODID; - return id == CPU_VALUE_PXA25X; -} - -int cpu_is_pxa27x(void) -{ - uint32_t id = pxa_get_cpuid(); - id &= CPU_MASK_PXA_PRODID; - return id == CPU_VALUE_PXA27X; -} - -int cpu_is_pxa27xm(void) -{ - uint32_t id = pxa_get_cpuid(); - return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) && - ((id & CPU_MASK_PXA_REVID) == 8); -} - -uint32_t pxa_get_cpu_revision(void) -{ - return pxa_get_cpuid() & CPU_MASK_PRODREV; -} - -#ifdef CONFIG_DISPLAY_CPUINFO -static const char *pxa25x_get_revision(void) -{ - static __maybe_unused const char * const revs_25x[] = { "A0" }; - static __maybe_unused const char * const revs_26x[] = { - "A0", "B0", "B1" - }; - static const char *unknown = "Unknown"; - uint32_t id; - - if (!cpu_is_pxa25x()) - return unknown; - - id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; - -/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */ -#ifdef CONFIG_CPU_PXA26X - switch (id) { - case 3: return revs_26x[0]; - case 5: return revs_26x[1]; - case 6: return revs_26x[2]; - } -#else - if (id == 6) - return revs_25x[0]; -#endif - return unknown; -} - -static const char *pxa27x_get_revision(void) -{ - static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" }; - static const char *unknown = "Unknown"; - uint32_t id; - - if (!cpu_is_pxa27x()) - return unknown; - - id = pxa_get_cpuid() & CPU_MASK_PXA_REVID; - - if ((id == 5) || (id == 6) || (id > 8)) - return unknown; - - /* Cap the special PXA270 C5 case. */ - if (id == 7) - id = 5; - - /* Cap the special PXA270M A1 case. */ - if (id == 8) - id = 1; - - return rev[id]; -} - -static int print_cpuinfo_pxa2xx(void) -{ - if (cpu_is_pxa25x()) { - puts("Marvell PXA25x rev. "); - puts(pxa25x_get_revision()); - } else if (cpu_is_pxa27x()) { - puts("Marvell PXA27x"); - if (cpu_is_pxa27xm()) puts("M"); - puts(" rev. "); - puts(pxa27x_get_revision()); - } else - return -EINVAL; - - puts("\n"); - - return 0; -} - -int print_cpuinfo(void) -{ - int ret; - - puts("CPU: "); - - ret = print_cpuinfo_pxa2xx(); - if (!ret) - return ret; - - return ret; -} -#endif diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c deleted file mode 100644 index c7efb67754..0000000000 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <irq_func.h> -#include <asm/arch/pxa-regs.h> -#include <asm/cache.h> -#include <asm/io.h> -#include <asm/system.h> -#include <command.h> - -/* Flush I/D-cache */ -static void cache_flush(void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); -} - -int cleanup_before_linux(void) -{ - /* - * This function is called just before we call Linux. It prepares - * the processor for Linux by just disabling everything that can - * disturb booting Linux. - */ - - disable_interrupts(); - icache_disable(); - dcache_disable(); - cache_flush(); - - return 0; -} - -inline void writelrb(uint32_t val, uint32_t addr) -{ - writel(val, addr); - asm volatile("" : : : "memory"); - readl(addr); - asm volatile("" : : : "memory"); -} - -void pxa2xx_dram_init(void) -{ - uint32_t tmp; - int i; - /* - * 1) Initialize Asynchronous static memory controller - */ - - writelrb(CONFIG_SYS_MSC0_VAL, MSC0); - writelrb(CONFIG_SYS_MSC1_VAL, MSC1); - writelrb(CONFIG_SYS_MSC2_VAL, MSC2); - /* - * 2) Initialize Card Interface - */ - - /* MECR: Memory Expansion Card Register */ - writelrb(CONFIG_SYS_MECR_VAL, MECR); - /* MCMEM0: Card Interface slot 0 timing */ - writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0); - /* MCMEM1: Card Interface slot 1 timing */ - writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1); - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0); - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1); - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0); - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1); - - /* - * 3) Configure Fly-By DMA register - */ - - writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG); - - /* - * 4) Initialize Timing for Sync Memory (SDCLK0) - */ - - /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. - */ - - /* Read current MDREFR config and zero out DRI */ - tmp = readl(MDREFR) & ~0xfff; - /* Add user-specified DRI */ - tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff; - /* Configure important bits */ - tmp |= MDREFR_K0RUN | MDREFR_SLFRSH; - tmp &= ~(MDREFR_APD | MDREFR_E1PIN); - - /* Write MDREFR back */ - writelrb(tmp, MDREFR); - - /* - * 5) Initialize Synchronous Static Memory (Flash/Peripherals) - */ - - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. - */ - writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG); - - /* - * 6) Initialize SDRAM - */ - - writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR); - writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR); - - /* - * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure - * but not enable each SDRAM partition pair. - */ - - writelrb(CONFIG_SYS_MDCNFG_VAL & - ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG); - - /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ - writel(0, OSCR); - while (readl(OSCR) < 0x300) - asm volatile("" : : : "memory"); - - /* - * 8) Trigger a number (usually 8) refresh cycles by attempting - * non-burst read or write accesses to disabled SDRAM, as commonly - * specified in the power up sequence documented in SDRAM data - * sheets. The address(es) used for this purpose must not be - * cacheable. - */ - for (i = 9; i >= 0; i--) { - writel(i, 0xa0000000); - asm volatile("" : : : "memory"); - } - /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). - */ - - tmp = CONFIG_SYS_MDCNFG_VAL & - (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3); - tmp |= readl(MDCNFG); - writelrb(tmp, MDCNFG); - - /* - * 10) Write MDMRS. - */ - - writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS); - - /* - * 11) Enable APD - */ - - if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) { - tmp = readl(MDREFR); - tmp |= MDREFR_APD; - writelrb(tmp, MDREFR); - } -} - -void pxa_gpio_setup(void) -{ - writel(CONFIG_SYS_GPSR0_VAL, GPSR0); - writel(CONFIG_SYS_GPSR1_VAL, GPSR1); - writel(CONFIG_SYS_GPSR2_VAL, GPSR2); -#if defined(CONFIG_CPU_PXA27X) - writel(CONFIG_SYS_GPSR3_VAL, GPSR3); -#endif - - writel(CONFIG_SYS_GPCR0_VAL, GPCR0); - writel(CONFIG_SYS_GPCR1_VAL, GPCR1); - writel(CONFIG_SYS_GPCR2_VAL, GPCR2); -#if defined(CONFIG_CPU_PXA27X) - writel(CONFIG_SYS_GPCR3_VAL, GPCR3); -#endif - - writel(CONFIG_SYS_GPDR0_VAL, GPDR0); - writel(CONFIG_SYS_GPDR1_VAL, GPDR1); - writel(CONFIG_SYS_GPDR2_VAL, GPDR2); -#if defined(CONFIG_CPU_PXA27X) - writel(CONFIG_SYS_GPDR3_VAL, GPDR3); -#endif - - writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L); - writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U); - writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L); - writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U); - writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L); - writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U); -#if defined(CONFIG_CPU_PXA27X) - writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L); - writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U); -#endif - - writel(CONFIG_SYS_PSSR_VAL, PSSR); -} - -void pxa_interrupt_setup(void) -{ - writel(0, ICLR); - writel(0, ICMR); -#if defined(CONFIG_CPU_PXA27X) - writel(0, ICLR2); - writel(0, ICMR2); -#endif -} - -void pxa_clock_setup(void) -{ - writel(CONFIG_SYS_CKEN, CKEN); - writel(CONFIG_SYS_CCCR, CCCR); - asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b)); - - /* enable the 32Khz oscillator for RTC and PowerManager */ - writel(OSCC_OON, OSCC); - while (!(readl(OSCC) & OSCC_OOK)) - asm volatile("" : : : "memory"); -} - -void pxa_wakeup(void) -{ - uint32_t rcsr; - - rcsr = readl(RCSR); - writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR); - - /* Wakeup */ - if (rcsr & RCSR_SMR) { - writel(PSSR_PH, PSSR); - pxa2xx_dram_init(); - icache_disable(); - dcache_disable(); - asm volatile("mov pc, %0" : : "r"(readl(PSPR))); - } -} - -int arch_cpu_init(void) -{ - pxa_gpio_setup(); - pxa_wakeup(); - pxa_interrupt_setup(); - pxa_clock_setup(); - return 0; -} - -void i2c_clk_enable(void) -{ - /* Set the global I2C clock on */ - writel(readl(CKEN) | CKEN14_I2C, CKEN); -} - -void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn)); - -void reset_cpu(void) -{ - uint32_t tmp; - - setbits_le32(OWER, OWER_WME); - - tmp = readl(OSCR); - tmp += 0x1000; - writel(tmp, OSMR3); - writel(MDREFR_SLFRSH, MDREFR); - - for (;;) - ; -} - -void enable_caches(void) -{ -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) - icache_enable(); -#endif -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) - dcache_enable(); -#endif -} diff --git a/arch/arm/cpu/pxa/relocate.S b/arch/arm/cpu/pxa/relocate.S deleted file mode 100644 index 778cd45e9c..0000000000 --- a/arch/arm/cpu/pxa/relocate.S +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * relocate - PXA270 vector relocation - * - * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> - */ - -#include <linux/linkage.h> - -/* - * The PXA SoC is very specific with respect to exceptions: it - * does not provide RAM at the high vectors address (0xFFFF0000), - * thus only the low address (0x00000000) is useable; but that is - * in ROM, so let's avoid relocating the vectors. - */ - .section .text.relocate_vectors,"ax",%progbits - -ENTRY(relocate_vectors) - - bx lr - -ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S deleted file mode 100644 index ab7bcb4e56..0000000000 --- a/arch/arm/cpu/pxa/start.S +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * armboot - Startup Code for XScale CPU-core - * - * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> - * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> - * Copyright (C) 2001 Marius Groger <mag@sysgo.de> - * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> - * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> - * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> - * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> - * Copyright (C) 2003 Kshitij <kshitij@ti.com> - * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> - * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> - * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - */ - -#include <asm-offsets.h> -#include <config.h> - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - - .globl reset - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) - bl cpu_init_crit -#endif - -#ifdef CONFIG_CPU_PXA27X - /* - * enable clock for SRAM - */ - ldr r0,=CKEN - ldr r1,[r0] - orr r1,r1,#(1 << 20) - str r1,[r0] -#endif - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - bx lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ - mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 1 (A) Align - mcr p15, 0, r0, c1, c0, 0 - - mov pc, lr /* back to my caller */ -#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c deleted file mode 100644 index 8e9d610441..0000000000 --- a/arch/arm/cpu/pxa/timer.c +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Marvell PXA2xx/3xx timer driver - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> - -int timer_init(void) -{ - writel(0, CONFIG_SYS_TIMER_COUNTER); - return 0; -} diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c deleted file mode 100644 index 13e010d91e..0000000000 --- a/arch/arm/cpu/pxa/usb.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de> - */ - -#include <common.h> -#include <linux/delay.h> - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) - -#include <asm/arch/pxa-regs.h> -#include <asm/io.h> -#include <usb.h> - -int usb_cpu_init(void) -{ -#if defined(CONFIG_CPU_MONAHANS) - /* Enable USB host clock. */ - writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); - udelay(100); -#endif -#if defined(CONFIG_CPU_PXA27X) - /* Enable USB host clock. */ - writel(readl(CKEN) | CKEN10_USBHOST, CKEN); -#endif - -#if defined(CONFIG_CPU_MONAHANS) - /* Configure Port 2 for Host (USB Client Registers) */ - writel(0x3000c, UP2OCR); -#endif - - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - mdelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (readl(UHCHR) & UHCHR_FSBIR) - udelay(1); - -#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) - writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); -#endif -#if defined(CONFIG_CPU_PXA27X) - writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); -#endif - writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); - - return 0; -} - -int usb_cpu_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS); - udelay(10); - -#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) - writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); -#endif -#if defined(CONFIG_CPU_PXA27X) - writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR); -#endif - writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR); - -#if defined(CONFIG_CPU_MONAHANS) - /* Disable USB host clock. */ - writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA); - udelay(100); -#endif -#if defined(CONFIG_CPU_PXA27X) - /* Disable USB host clock. */ - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); -#endif - - return 0; -} - -int usb_cpu_init_fail(void) -{ - return usb_cpu_stop(); -} - -# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */ -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a9f4cccf8d..8f7ecfd0f6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -5,9 +5,9 @@ dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb -dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb -dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb -dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ +dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb +dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb +dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ @@ -19,7 +19,7 @@ dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb -dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ +dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-spring.dtb \ exynos5250-smdk5250.dtb \ @@ -414,7 +414,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am437x-cm-t43.dtb dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb dtb-$(CONFIG_TI816X) += dm8168-evm.dtb -dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb +dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index 4796ed445f..cc577761fa 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -60,6 +60,10 @@ pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>; }; +&sdmmc { + status = "okay"; +}; + &sdhci0 { status = "okay"; @@ -73,3 +77,22 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd2_default>; }; + +&i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c7 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index ea60e4c8db..057390fe70 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -28,31 +28,6 @@ clocks = <&scu ASPEED_CLK_MPLL>; resets = <&rst ASPEED_RESET_SDRAM>; }; - - ahb { - u-boot,dm-pre-reloc; - - apb { - u-boot,dm-pre-reloc; - - sdhci0: sdhci@1e740100 { - compatible = "aspeed,ast2500-sdhci"; - reg = <0x1e740100>; - #reset-cells = <1>; - clocks = <&scu ASPEED_CLK_SDIO>; - resets = <&rst ASPEED_RESET_SDIO>; - }; - - sdhci1: sdhci@1e740200 { - compatible = "aspeed,ast2500-sdhci"; - reg = <0x1e740200>; - #reset-cells = <1>; - clocks = <&scu ASPEED_CLK_SDIO>; - resets = <&rst ASPEED_RESET_SDIO>; - }; - }; - - }; }; &uart1 { diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index ee66ef6704..cea08e6f08 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -207,6 +207,34 @@ reg = <0x1e720000 0x9000>; // 36K }; + sdmmc: sd-controller@1e740000 { + compatible = "aspeed,ast2500-sd-controller"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&scu ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; + + sdhci0: sdhci@100 { + compatible = "aspeed,ast2500-sdhci"; + reg = <0x100 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&scu ASPEED_CLK_SDIO>; + status = "disabled"; + }; + + sdhci1: sdhci@200 { + compatible = "aspeed,ast2500-sdhci"; + reg = <0x200 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&scu ASPEED_CLK_SDIO>; + status = "disabled"; + }; + }; + gpio: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index 0d65054313..a9bba96816 100644 --- a/arch/arm/dts/ast2600-evb.dts +++ b/arch/arm/dts/ast2600-evb.dts @@ -15,9 +15,9 @@ }; aliases { - mmc0 = &emmc_slot0; - mmc1 = &sdhci_slot0; - mmc2 = &sdhci_slot1; + mmc0 = &emmc; + mmc1 = &sdhci0; + mmc2 = &sdhci1; spi0 = &fmc; spi1 = &spi1; spi2 = &spi2; @@ -134,53 +134,52 @@ }; }; -&emmc { - u-boot,dm-pre-reloc; - timing-phase = <0x700ff>; + +&emmc_controller { + status = "okay"; }; -&emmc_slot0 { - u-boot,dm-pre-reloc; - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc_default>; - sdhci-drive-type = <1>; +&emmc { + non-removable; + bus-width = <4>; + max-frequency = <100000000>; + clk-phase-mmc-hs200 = <9>, <225>; }; &i2c4 { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; }; &i2c5 { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; }; &i2c6 { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; }; &i2c7 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; + temp@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; }; &i2c8 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; }; &mdio0 { diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index 64074309b7..ac8cd4d67d 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -416,60 +416,51 @@ status = "disabled"; }; - sdhci: sdhci@1e740000 { - #interrupt-cells = <1>; - compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd"; - reg = <0x1e740000 0x1000>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - clocks = <&scu ASPEED_CLK_GATE_SDCLK>, - <&scu ASPEED_CLK_GATE_SDEXTCLK>; - clock-names = "ctrlclk", "extclk"; + sdc: sdc@1e740000 { + compatible = "aspeed,ast2600-sd-controller"; + reg = <0x1e740000 0x100>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x1e740000 0x1000>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&scu ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; - sdhci_slot0: sdhci_slot0@100 { - compatible = "aspeed,sdhci-ast2600"; + sdhci0: sdhci@1e740100 { + compatible = "aspeed,ast2600-sdhci", "sdhci"; reg = <0x100 0x100>; - interrupts = <0>; - interrupt-parent = <&sdhci>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; sdhci,auto-cmd12; clocks = <&scu ASPEED_CLK_SDIO>; status = "disabled"; }; - sdhci_slot1: sdhci_slot1@200 { - compatible = "aspeed,sdhci-ast2600"; + sdhci1: sdhci@1e740200 { + compatible = "aspeed,ast2600-sdhci", "sdhci"; reg = <0x200 0x100>; - interrupts = <1>; - interrupt-parent = <&sdhci>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; sdhci,auto-cmd12; clocks = <&scu ASPEED_CLK_SDIO>; status = "disabled"; }; }; - emmc: emmc@1e750000 { - #interrupt-cells = <1>; - compatible = "aspeed,aspeed-emmc-irq", "simple-mfd"; - reg = <0x1e750000 0x1000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>, - <&scu ASPEED_CLK_GATE_EMMCEXTCLK>; - clock-names = "ctrlclk", "extclk"; + emmc_controller: sdc@1e750000 { + compatible = "aspeed,ast2600-sd-controller"; + reg = <0x1e750000 0x100>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x1e750000 0x1000>; + ranges = <0 0x1e750000 0x10000>; + clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>; + status = "disabled"; - emmc_slot0: emmc_slot0@100 { - compatible = "aspeed,emmc-ast2600"; + emmc: sdhci@1e750100 { + compatible = "aspeed,ast2600-sdhci"; reg = <0x100 0x100>; - interrupts = <0>; - interrupt-parent = <&emmc>; + sdhci,auto-cmd12; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_EMMC>; - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc_default>; }; }; @@ -832,7 +823,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; status = "disabled"; }; @@ -845,7 +839,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; status = "disabled"; }; @@ -858,7 +855,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; }; i2c3: i2c@200 { @@ -870,7 +871,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; }; i2c4: i2c@280 { @@ -882,7 +887,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; }; i2c5: i2c@300 { @@ -894,7 +903,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; }; i2c6: i2c@380 { @@ -906,7 +919,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; }; i2c7: i2c@400 { @@ -918,7 +935,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; }; i2c8: i2c@480 { @@ -930,7 +951,11 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; }; i2c9: i2c@500 { @@ -942,7 +967,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; status = "disabled"; }; @@ -955,7 +983,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; status = "disabled"; }; @@ -968,7 +999,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; status = "disabled"; }; @@ -981,7 +1015,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; status = "disabled"; }; @@ -994,7 +1031,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; status = "disabled"; }; @@ -1007,7 +1047,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c15_default>; status = "disabled"; }; @@ -1020,7 +1063,10 @@ compatible = "aspeed,ast2600-i2c-bus"; bus-frequency = <100000>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst ASPEED_RESET_I2C>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c16_default>; status = "disabled"; }; @@ -1246,6 +1292,7 @@ function = "I2C1"; groups = "I2C1"; }; + pinctrl_i2c2_default: i2c2_default { function = "I2C2"; groups = "I2C2"; diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts index 44522197ff..0b0db1b2be 100644 --- a/arch/arm/dts/at91-sama5d2_icp.dts +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -68,19 +68,19 @@ status = "okay"; eeprom@50 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x50>; pagesize = <16>; }; eeprom@52 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x52>; pagesize = <16>; }; eeprom@53 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x53>; pagesize = <16>; }; diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts index ee46112b08..eaba0de3f7 100644 --- a/arch/arm/dts/at91-sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -14,6 +14,7 @@ #include <dt-bindings/mfd/atmel-flexcom.h> #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/sound/microchip,pdmc.h> / { model = "Microchip SAMA7G5-EK"; @@ -404,13 +405,13 @@ status = "okay"; eeprom@52 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x52>; pagesize = <16>; }; eeprom@53 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x53>; pagesize = <16>; }; @@ -468,7 +469,7 @@ &pinctrl_gmac1_mdio_default &pinctrl_gmac1_phy_irq>; phy-mode = "rmii"; - status = "okay"; + status = "okay"; /* Conflict with pdmc0. */ ethernet-phy@0 { reg = <0x0>; @@ -482,6 +483,17 @@ pinctrl-0 = <&pinctrl_i2s0_default>; }; +&pdmc0 { + #sound-dai-cells = <0>; + microchip,mic-pos = <MCHP_PDMC_DS0 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 1 */ + <MCHP_PDMC_DS1 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 2 */ + <MCHP_PDMC_DS0 MCHP_PDMC_CLK_POSITIVE>, /* MIC 3 */ + <MCHP_PDMC_DS1 MCHP_PDMC_CLK_POSITIVE>; /* MIC 4 */ + status = "disabled"; /* Conflict with gmac1. */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdmc0_default>; +}; + &pioA { pinctrl_can0_default: can0_default { @@ -651,6 +663,13 @@ bias-disable; }; + pinctrl_pdmc0_default: pdmc0_default { + pinmux = <PIN_PD23__PDMC0_DS0>, + <PIN_PD24__PDMC0_DS1>, + <PIN_PD22__PDMC0_CLK>; + bias_disable; + }; + pinctrl_qspi: qspi { pinmux = <PIN_PB12__QSPI0_IO0>, <PIN_PB11__QSPI0_IO1>, diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 2691af40a1..5aab858edd 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -28,6 +28,7 @@ /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + u-boot,dm-spl; }; reserved-memory { diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index e1971ecdfe..159fa36bbe 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -13,6 +13,10 @@ aliases { mmc1 = &sdhci1; }; + + memory@80000000 { + u-boot,dm-spl; + }; }; &cbass_main{ diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index 32ffe93b4d..54c694bd78 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -49,7 +49,7 @@ status = "okay"; nor_flash: sst26vf064@0 { - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; spi-rx-bus-width = <4>; @@ -72,7 +72,7 @@ status = "okay"; eeprom@53 { - compatible = "atmel,24c32"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */ reg = <0x53>; pagesize = <16>; }; diff --git a/arch/arm/dts/sama5d27_som1.dtsi b/arch/arm/dts/sama5d27_som1.dtsi index ea7540bcfc..db4fefadcd 100644 --- a/arch/arm/dts/sama5d27_som1.dtsi +++ b/arch/arm/dts/sama5d27_som1.dtsi @@ -92,7 +92,7 @@ status = "okay"; i2c_eeprom: i2c_eeprom@50 { - compatible = "microchip,24aa02e48"; + compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa02e48 */ reg = <0x50>; }; }; diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index 4efecdb92c..97400dc18e 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -33,6 +33,7 @@ reg = <0x0>; clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>; clock-names = "cpu", "master", "xtal"; + operating-points-v2 = <&cpu_opp_table>; }; }; @@ -225,7 +226,7 @@ status = "disabled"; }; - rtt: rtt@e001d020 { + rtt: rtc@e001d020 { compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; reg = <0xe001d020 0x30>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -490,6 +491,30 @@ status = "disabled"; }; + pdmc0: sound@e1608000 { + compatible = "microchip,sama7g5-pdmc"; + reg = <0xe1608000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + pdmc1: sound@e160c000 { + compatible = "microchip,sama7g5-pdmc"; + reg = <0xe160c000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + spdifrx: spdifrx@e1614000 { #sound-dai-cells = <0>; compatible = "microchip,sama7g5-spdifrx"; @@ -628,9 +653,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, - <&dma0 AT91_XDMAC_DT_PERID(8)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -814,9 +839,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, - <&dma0 AT91_XDMAC_DT_PERID(22)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -838,9 +863,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, - <&dma0 AT91_XDMAC_DT_PERID(24)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -885,7 +910,6 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - interrupt-parent; reg = <0xe8c11000 0x1000>, <0xe8c12000 0x2000>; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 1315bebb56..cd795d6919 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -55,17 +55,6 @@ /* SMMU Defintions */ #define SMMU_BASE 0x05000000 /* GR0 Base */ -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE @@ -160,17 +149,6 @@ #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 @@ -215,17 +193,6 @@ /* SMMU Definitions */ #define SMMU_BASE 0x05000000 /* GR0 Base */ -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE @@ -274,20 +241,9 @@ #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - /* SEC */ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - /* DCFG - GUR */ #define CONFIG_SYS_FSL_CCSR_GUR_LE @@ -321,11 +277,6 @@ #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION /* SMMU Defintions */ #define SMMU_BASE 0x09000000 @@ -361,11 +312,6 @@ #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -380,11 +326,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 61db1738f3..f2dbcdc816 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -13,10 +13,8 @@ #define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) -#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) @@ -26,9 +24,7 @@ #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) -#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) -#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) @@ -37,7 +33,6 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 304cd7980a..570397b3c0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -52,7 +52,6 @@ #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL -#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 653792c610..32d68cbeb8 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -52,11 +52,7 @@ /* USB OHCI */ #if defined(CONFIG_USB_OHCI_LPC32XX) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci" #endif #endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 3b1d9a3f0c..e5f61ea4a6 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -32,15 +32,11 @@ #define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 -#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 -#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) @@ -80,23 +76,17 @@ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_SEC_MON_LE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE #define DCU_LAYER_MAX_NUM 16 #ifdef CONFIG_ARCH_LS1021A -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-pxa/bitfield.h b/arch/arm/include/asm/arch-pxa/bitfield.h deleted file mode 100644 index 104a21c2e4..0000000000 --- a/arch/arm/include/asm/arch-pxa/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/arch/arm/include/asm/arch-pxa/config.h b/arch/arm/include/asm/arch-pxa/config.h deleted file mode 100644 index 11effd47f5..0000000000 --- a/arch/arm/include/asm/arch-pxa/config.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Andrew Ruder <andrew.ruder@elecsyscorp.com> - */ - -#ifndef _ASM_ARM_PXA_CONFIG_ -#define _ASM_ARM_PXA_CONFIG_ - -#include <asm/arch/pxa-regs.h> - -/* - * Generic timer support - */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define CONFIG_SYS_TIMER_RATE 3250000 -#else -#error "Timer frequency unknown - please config PXA CPU type" -#endif - -#define CONFIG_SYS_TIMER_COUNTER OSCR - -#endif /* _ASM_ARM_PXA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h deleted file mode 100644 index 6d0023d7b8..0000000000 --- a/arch/arm/include/asm/arch-pxa/hardware.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/hardware.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: This file was taken from linux-2.4.19-rmk4-pxa1 - * - * - 2003/01/20 implementation specifics activated - * Robert Schwebel <r.schwebel@pengutronix.de> - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/mach-types.h> - -/* - * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected. - * PXA300/310/320 all have distinct register mappings in some cases, that's why - * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common - * drivers and compatibility glue with old source then. - */ -#ifndef CONFIG_CPU_MONAHANS -#if defined(CONFIG_CPU_PXA300) || \ - defined(CONFIG_CPU_PXA310) || \ - defined(CONFIG_CPU_PXA320) -#define CONFIG_CPU_MONAHANS -#endif -#endif - -/* - * These are statically mapped PCMCIA IO space for designs using it as a - * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. - * The actual PCMCIA code is mapping required IO region at run time. - */ -#define PCMCIA_IO_0_BASE 0xf6000000 -#define PCMCIA_IO_1_BASE 0xf7000000 - - -/* - * We requires absolute addresses. - */ -#define PCIO_BASE 0 - -/* - * Workarounds for at least 2 errata so far require this. - * The mapping is set in mach-pxa/generic.c. - */ -#define UNCACHED_PHYS_0 0xff000000 -#define UNCACHED_ADDR UNCACHED_PHYS_0 - -/* - * Intel PXA internal I/O mappings: - * - * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff - * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff - * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff - */ - -#include "pxa-regs.h" - -#ifndef __ASSEMBLY__ - -/* - * GPIO edge detection for IRQs: - * IRQs are generated on Falling-Edge, Rising-Edge, or both. - * This must be called *before* the corresponding IRQ is registered. - * Use this instead of directly setting GRER/GFER. - */ -#define GPIO_FALLING_EDGE 1 -#define GPIO_RISING_EDGE 2 -#define GPIO_BOTH_EDGES 3 - -#endif - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h deleted file mode 100644 index b81b42c07c..0000000000 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ /dev/null @@ -1,2635 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/pxa-regs.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de - * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions. - * Added include for hardware.h (for __REG definition) - */ -#ifndef _PXA_REGS_H_ -#define _PXA_REGS_H_ - -#include "bitfield.h" -#include "hardware.h" - -/* FIXME hack so that SA-1111.h will work [cb] */ - -#ifndef __ASSEMBLY__ -typedef unsigned short Word16 ; -typedef unsigned int Word32 ; -typedef Word32 Word ; -typedef Word Quad [4] ; -typedef void *Address ; -typedef void (*ExcpHndlr) (void) ; -#endif - -/* - * PXA Chip selects - */ -#ifdef CONFIG_CPU_MONAHANS -#define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */ -#define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */ -#define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */ -#define PXA_CS2_PHYS 0x10000000 /* (64MB) */ -#define PXA_CS3_PHYS 0x14000000 /* (64MB) */ -#define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */ -#else -#define PXA_CS0_PHYS 0x00000000 -#define PXA_CS1_PHYS 0x04000000 -#define PXA_CS2_PHYS 0x08000000 -#define PXA_CS3_PHYS 0x0C000000 -#define PXA_CS4_PHYS 0x10000000 -#define PXA_CS5_PHYS 0x14000000 -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * Personal Computer Memory Card International Association (PCMCIA) sockets - */ -#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ -#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ - -#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ -#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ -#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ -#endif - -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ -#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ -#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ - -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ - (0x20000000 + (Nb)*PCMCIASp) -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ - (_PCMCIA (Nb) + 2*PCMCIAPrtSp) -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ - (_PCMCIA (Nb) + 3*PCMCIAPrtSp) - -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ - -#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ -#endif - -/* - * DMA Controller - */ -#define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */ -#define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */ -#define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */ -#define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */ -#define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */ -#define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */ -#define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */ -#define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */ -#define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */ -#define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */ -#define DCSR10 0x40000028 /* DMA Control / Status Register for Channel 10 */ -#define DCSR11 0x4000002c /* DMA Control / Status Register for Channel 11 */ -#define DCSR12 0x40000030 /* DMA Control / Status Register for Channel 12 */ -#define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */ -#define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */ -#define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */ -#define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */ -#define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */ -#define DCSR19 0x4000004c /* DMA Control / Status Register for Channel 19 */ -#define DCSR20 0x40000050 /* DMA Control / Status Register for Channel 20 */ -#define DCSR21 0x40000054 /* DMA Control / Status Register for Channel 21 */ -#define DCSR22 0x40000058 /* DMA Control / Status Register for Channel 22 */ -#define DCSR23 0x4000005c /* DMA Control / Status Register for Channel 23 */ -#define DCSR24 0x40000060 /* DMA Control / Status Register for Channel 24 */ -#define DCSR25 0x40000064 /* DMA Control / Status Register for Channel 25 */ -#define DCSR26 0x40000068 /* DMA Control / Status Register for Channel 26 */ -#define DCSR27 0x4000006c /* DMA Control / Status Register for Channel 27 */ -#define DCSR28 0x40000070 /* DMA Control / Status Register for Channel 28 */ -#define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */ -#define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */ -#define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#define DCSR(x) (0x40000000 | ((x) << 2)) - -#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ -#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ -#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ -#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ -#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ -#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ -#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ -#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ -#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ -#endif - -#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ -#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ -#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ -#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ -#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ - -#define DINT 0x400000f0 /* DMA Interrupt Register */ - -#define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */ -#define DRCMR1 0x40000104 /* Request to Channel Map Register for DREQ 1 */ -#define DRCMR2 0x40000108 /* Request to Channel Map Register for I2S receive Request */ -#define DRCMR3 0x4000010c /* Request to Channel Map Register for I2S transmit Request */ -#define DRCMR4 0x40000110 /* Request to Channel Map Register for BTUART receive Request */ -#define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ -#define DRCMR6 0x40000118 /* Request to Channel Map Register for FFUART receive Request */ -#define DRCMR7 0x4000011c /* Request to Channel Map Register for FFUART transmit Request */ -#define DRCMR8 0x40000120 /* Request to Channel Map Register for AC97 microphone Request */ -#define DRCMR9 0x40000124 /* Request to Channel Map Register for AC97 modem receive Request */ -#define DRCMR10 0x40000128 /* Request to Channel Map Register for AC97 modem transmit Request */ -#define DRCMR11 0x4000012c /* Request to Channel Map Register for AC97 audio receive Request */ -#define DRCMR12 0x40000130 /* Request to Channel Map Register for AC97 audio transmit Request */ -#define DRCMR13 0x40000134 /* Request to Channel Map Register for SSP receive Request */ -#define DRCMR14 0x40000138 /* Request to Channel Map Register for SSP transmit Request */ -#define DRCMR15 0x4000013c /* Reserved */ -#define DRCMR16 0x40000140 /* Reserved */ -#define DRCMR17 0x40000144 /* Request to Channel Map Register for ICP receive Request */ -#define DRCMR18 0x40000148 /* Request to Channel Map Register for ICP transmit Request */ -#define DRCMR19 0x4000014c /* Request to Channel Map Register for STUART receive Request */ -#define DRCMR20 0x40000150 /* Request to Channel Map Register for STUART transmit Request */ -#define DRCMR21 0x40000154 /* Request to Channel Map Register for MMC receive Request */ -#define DRCMR22 0x40000158 /* Request to Channel Map Register for MMC transmit Request */ -#define DRCMR23 0x4000015c /* Reserved */ -#define DRCMR24 0x40000160 /* Reserved */ -#define DRCMR25 0x40000164 /* Request to Channel Map Register for USB endpoint 1 Request */ -#define DRCMR26 0x40000168 /* Request to Channel Map Register for USB endpoint 2 Request */ -#define DRCMR27 0x4000016C /* Request to Channel Map Register for USB endpoint 3 Request */ -#define DRCMR28 0x40000170 /* Request to Channel Map Register for USB endpoint 4 Request */ -#define DRCMR29 0x40000174 /* Reserved */ -#define DRCMR30 0x40000178 /* Request to Channel Map Register for USB endpoint 6 Request */ -#define DRCMR31 0x4000017C /* Request to Channel Map Register for USB endpoint 7 Request */ -#define DRCMR32 0x40000180 /* Request to Channel Map Register for USB endpoint 8 Request */ -#define DRCMR33 0x40000184 /* Request to Channel Map Register for USB endpoint 9 Request */ -#define DRCMR34 0x40000188 /* Reserved */ -#define DRCMR35 0x4000018C /* Request to Channel Map Register for USB endpoint 11 Request */ -#define DRCMR36 0x40000190 /* Request to Channel Map Register for USB endpoint 12 Request */ -#define DRCMR37 0x40000194 /* Request to Channel Map Register for USB endpoint 13 Request */ -#define DRCMR38 0x40000198 /* Request to Channel Map Register for USB endpoint 14 Request */ -#define DRCMR39 0x4000019C /* Reserved */ - -#define DRCMR68 0x40001110 /* Request to Channel Map Register for Camera FIFO 0 Request */ -#define DRCMR69 0x40001114 /* Request to Channel Map Register for Camera FIFO 1 Request */ -#define DRCMR70 0x40001118 /* Request to Channel Map Register for Camera FIFO 2 Request */ - -#define DRCMRRXSADR DRCMR2 -#define DRCMRTXSADR DRCMR3 -#define DRCMRRXBTRBR DRCMR4 -#define DRCMRTXBTTHR DRCMR5 -#define DRCMRRXFFRBR DRCMR6 -#define DRCMRTXFFTHR DRCMR7 -#define DRCMRRXMCDR DRCMR8 -#define DRCMRRXMODR DRCMR9 -#define DRCMRTXMODR DRCMR10 -#define DRCMRRXPCDR DRCMR11 -#define DRCMRTXPCDR DRCMR12 -#define DRCMRRXSSDR DRCMR13 -#define DRCMRTXSSDR DRCMR14 -#define DRCMRRXICDR DRCMR17 -#define DRCMRTXICDR DRCMR18 -#define DRCMRRXSTRBR DRCMR19 -#define DRCMRTXSTTHR DRCMR20 -#define DRCMRRXMMC DRCMR21 -#define DRCMRTXMMC DRCMR22 - -#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ -#define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */ - -#define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */ -#define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */ -#define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */ -#define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */ -#define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */ -#define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */ -#define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */ -#define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */ -#define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */ -#define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */ -#define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */ -#define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */ -#define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */ -#define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */ -#define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */ -#define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */ -#define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */ -#define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */ -#define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */ -#define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */ -#define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */ -#define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */ -#define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */ -#define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */ -#define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */ -#define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */ -#define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */ -#define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */ -#define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */ -#define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */ -#define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */ -#define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */ -#define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */ -#define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */ -#define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */ -#define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */ -#define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */ -#define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */ -#define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */ -#define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */ -#define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */ -#define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */ -#define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */ -#define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */ -#define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */ -#define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */ -#define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */ -#define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */ -#define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */ -#define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */ -#define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */ -#define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */ -#define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */ -#define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */ -#define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */ -#define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */ -#define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */ -#define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */ -#define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */ -#define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */ -#define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */ -#define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */ -#define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */ -#define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */ - -#define DDADR(x) (0x40000200 | ((x) << 4)) -#define DSADR(x) (0x40000204 | ((x) << 4)) -#define DTADR(x) (0x40000208 | ((x) << 4)) -#define DCMD(x) (0x4000020c | ((x) << 4)) - -#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ -#define DDADR_STOP (1 << 0) /* Stop (read / write) */ - -#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ -#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ -#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ -#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ -#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ -#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ -#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ -#define DCMD_BURST8 (1 << 16) /* 8 byte burst */ -#define DCMD_BURST16 (2 << 16) /* 16 byte burst */ -#define DCMD_BURST32 (3 << 16) /* 32 byte burst */ -#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ -#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ -#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ -#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ - -/* default combinations */ -#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) -#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) -#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) - -/******************************************************************************/ -/* - * IrSR (Infrared Selection Register) - */ -#define IrSR_OFFSET 0x20 - -#define IrSR_RXPL_NEG_IS_ZERO (1<<4) -#define IrSR_RXPL_POS_IS_ZERO 0x0 -#define IrSR_TXPL_NEG_IS_ZERO (1<<3) -#define IrSR_TXPL_POS_IS_ZERO 0x0 -#define IrSR_XMODE_PULSE_1_6 (1<<2) -#define IrSR_XMODE_PULSE_3_16 0x0 -#define IrSR_RCVEIR_IR_MODE (1<<1) -#define IrSR_RCVEIR_UART_MODE 0x0 -#define IrSR_XMITIR_IR_MODE (1<<0) -#define IrSR_XMITIR_UART_MODE 0x0 - -#define IrSR_IR_RECEIVE_ON (\ - IrSR_RXPL_NEG_IS_ZERO | \ - IrSR_TXPL_POS_IS_ZERO | \ - IrSR_XMODE_PULSE_3_16 | \ - IrSR_RCVEIR_IR_MODE | \ - IrSR_XMITIR_UART_MODE) - -#define IrSR_IR_TRANSMIT_ON (\ - IrSR_RXPL_NEG_IS_ZERO | \ - IrSR_TXPL_POS_IS_ZERO | \ - IrSR_XMODE_PULSE_3_16 | \ - IrSR_RCVEIR_UART_MODE | \ - IrSR_XMITIR_IR_MODE) - -/* - * Serial Audio Controller - */ -/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these - * short defines because there is too much chance of namespace collision - */ -#define SACR0 0x40400000 /* Global Control Register */ -#define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */ -#define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ -#define SAIMR 0x40400014 /* Serial Audio Interrupt Mask Register */ -#define SAICR 0x40400018 /* Serial Audio Interrupt Clear Register */ -#define SADIV 0x40400060 /* Audio Clock Divider Register. */ -#define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ - -/* - * AC97 Controller registers - */ -#define POCR 0x40500000 /* PCM Out Control Register */ -#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define PICR 0x40500004 /* PCM In Control Register */ -#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define MCCR 0x40500008 /* Mic In Control Register */ -#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define GCR 0x4050000C /* Global Control Register */ -#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ -#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ -#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ -#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ -#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ -#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ -#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ -#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ -#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ -#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ - -#define POSR 0x40500010 /* PCM Out Status Register */ -#define POSR_FIFOE (1 << 4) /* FIFO error */ - -#define PISR 0x40500014 /* PCM In Status Register */ -#define PISR_FIFOE (1 << 4) /* FIFO error */ - -#define MCSR 0x40500018 /* Mic In Status Register */ -#define MCSR_FIFOE (1 << 4) /* FIFO error */ - -#define GSR 0x4050001C /* Global Status Register */ -#define GSR_CDONE (1 << 19) /* Command Done */ -#define GSR_SDONE (1 << 18) /* Status Done */ -#define GSR_RDCS (1 << 15) /* Read Completion Status */ -#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ -#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ -#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ -#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ -#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ -#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ -#define GSR_PCR (1 << 8) /* Primary Codec Ready */ -#define GSR_MINT (1 << 7) /* Mic In Interrupt */ -#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ -#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ -#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ -#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ -#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ - -#define CAR 0x40500020 /* CODEC Access Register */ -#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ - -#define PCDR 0x40500040 /* PCM FIFO Data Register */ -#define MCDR 0x40500060 /* Mic-in FIFO Data Register */ - -#define MOCR 0x40500100 /* Modem Out Control Register */ -#define MOCR_FEIE (1 << 3) /* FIFO Error */ - -#define MICR 0x40500108 /* Modem In Control Register */ -#define MICR_FEIE (1 << 3) /* FIFO Error */ - -#define MOSR 0x40500110 /* Modem Out Status Register */ -#define MOSR_FIFOE (1 << 4) /* FIFO error */ - -#define MISR 0x40500118 /* Modem In Status Register */ -#define MISR_FIFOE (1 << 4) /* FIFO error */ - -#define MODR 0x40500140 /* Modem FIFO Data Register */ - -#define PAC_REG_BASE 0x40500200 /* Primary Audio Codec */ -#define SAC_REG_BASE 0x40500300 /* Secondary Audio Codec */ -#define PMC_REG_BASE 0x40500400 /* Primary Modem Codec */ -#define SMC_REG_BASE 0x40500500 /* Secondary Modem Codec */ - - -/* - * USB Device Controller - */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - -#define UDCCR 0x40600000 /* UDC Control Register */ -#define UDCCR_UDE (1 << 0) /* UDC enable */ -#define UDCCR_UDA (1 << 1) /* UDC active */ -#define UDCCR_RSM (1 << 2) /* Device resume */ -#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ -#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active Configuration */ -#define UDCCR_RESIR (1 << 29) /* Resume interrupt request */ -#define UDCCR_SUSIR (1 << 28) /* Suspend interrupt request */ -#define UDCCR_SM (1 << 28) /* Suspend interrupt mask */ -#define UDCCR_RSTIR (1 << 27) /* Reset interrupt request */ -#define UDCCR_REM (1 << 27) /* Reset interrupt mask */ -#define UDCCR_RM (1 << 29) /* resume interrupt mask */ -#define UDCCR_SRM (UDCCR_SM|UDCCR_RM) -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */ -#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */ -#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */ -#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ -#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ -#define UDCCR_ACN_S 11 -#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ -#define UDCCR_AIN_S 8 -#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */ -#define UDCCR_AAISN_S 5 - -#define UDCCS0 0x40600100 /* UDC Endpoint 0 Control/Status Register */ -#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ -#define UDCCS0_IPR (1 << 1) /* IN packet ready */ -#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS0_DRWF (1 << 16) /* Device remote wakeup feature */ -#define UDCCS0_SST (1 << 4) /* Sent stall */ -#define UDCCS0_FST (1 << 5) /* Force stall */ -#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ -#define UDCCS0_SA (1 << 7) /* Setup active */ - -/* Bulk IN - Endpoint 1,6,11 */ -#define UDCCS1 0x40600104 /* UDC Endpoint 1 (IN) Control/Status Register */ -#define UDCCS6 0x40600028 /* UDC Endpoint 6 (IN) Control/Status Register */ -#define UDCCS11 0x4060003C /* UDC Endpoint 11 (IN) Control/Status Register */ - -#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_BI_FTF (1 << 8) /* Flush Tx FIFO */ -#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_BI_SST (1 << 4) /* Sent stall */ -#define UDCCS_BI_FST (1 << 5) /* Force stall */ -#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ - -/* Bulk OUT - Endpoint 2,7,12 */ -#define UDCCS2 0x40600108 /* UDC Endpoint 2 (OUT) Control/Status Register */ -#define UDCCS7 0x4060002C /* UDC Endpoint 7 (OUT) Control/Status Register */ -#define UDCCS12 0x40600040 /* UDC Endpoint 12 (OUT) Control/Status Register */ - -#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_BO_DME (1 << 3) /* DMA enable */ -#define UDCCS_BO_SST (1 << 4) /* Sent stall */ -#define UDCCS_BO_FST (1 << 5) /* Force stall */ -#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ - -/* Isochronous IN - Endpoint 3,8,13 */ -#define UDCCS3 0x4060001C /* UDC Endpoint 3 (IN) Control/Status Register */ -#define UDCCS8 0x40600030 /* UDC Endpoint 8 (IN) Control/Status Register */ -#define UDCCS13 0x40600044 /* UDC Endpoint 13 (IN) Control/Status Register */ - -#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ - -/* Isochronous OUT - Endpoint 4,9,14 */ -#define UDCCS4 0x40600020 /* UDC Endpoint 4 (OUT) Control/Status Register */ -#define UDCCS9 0x40600034 /* UDC Endpoint 9 (OUT) Control/Status Register */ -#define UDCCS14 0x40600048 /* UDC Endpoint 14 (OUT) Control/Status Register */ - -#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ -#define UDCCS_IO_DME (1 << 3) /* DMA enable */ -#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ - -/* Interrupt IN - Endpoint 5,10,15 */ -#define UDCCS5 0x40600024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */ -#define UDCCS10 0x40600038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */ -#define UDCCS15 0x4060004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */ - -#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_INT_SST (1 << 4) /* Sent stall */ -#define UDCCS_INT_FST (1 << 5) /* Force stall */ -#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ - -#define UFNRH 0x40600060 /* UDC Frame Number Register High */ -#define UFNRL 0x40600014 /* UDC Frame Number Register Low */ -#define UBCR2 0x40600208 /* UDC Byte Count Reg 2 */ -#define UBCR4 0x4060006c /* UDC Byte Count Reg 4 */ -#define UBCR7 0x40600070 /* UDC Byte Count Reg 7 */ -#define UBCR9 0x40600074 /* UDC Byte Count Reg 9 */ -#define UBCR12 0x40600078 /* UDC Byte Count Reg 12 */ -#define UBCR14 0x4060007c /* UDC Byte Count Reg 14 */ -#define UDDR0 0x40600300 /* UDC Endpoint 0 Data Register */ -#define UDDR1 0x40600304 /* UDC Endpoint 1 Data Register */ -#define UDDR2 0x40600308 /* UDC Endpoint 2 Data Register */ -#define UDDR3 0x40600200 /* UDC Endpoint 3 Data Register */ -#define UDDR4 0x40600400 /* UDC Endpoint 4 Data Register */ -#define UDDR5 0x406000A0 /* UDC Endpoint 5 Data Register */ -#define UDDR6 0x40600600 /* UDC Endpoint 6 Data Register */ -#define UDDR7 0x40600680 /* UDC Endpoint 7 Data Register */ -#define UDDR8 0x40600700 /* UDC Endpoint 8 Data Register */ -#define UDDR9 0x40600900 /* UDC Endpoint 9 Data Register */ -#define UDDR10 0x406000C0 /* UDC Endpoint 10 Data Register */ -#define UDDR11 0x40600B00 /* UDC Endpoint 11 Data Register */ -#define UDDR12 0x40600B80 /* UDC Endpoint 12 Data Register */ -#define UDDR13 0x40600C00 /* UDC Endpoint 13 Data Register */ -#define UDDR14 0x40600E00 /* UDC Endpoint 14 Data Register */ -#define UDDR15 0x406000E0 /* UDC Endpoint 15 Data Register */ - -#define UICR0 0x40600004 /* UDC Interrupt Control Register 0 */ - -#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ -#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ -#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ -#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ -#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ -#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ -#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ -#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ - -#define UICR1 0x40600008 /* UDC Interrupt Control Register 1 */ - -#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ -#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ -#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ -#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ -#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ -#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ -#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ -#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ - -#define USIR0 0x4060000C /* UDC Status Interrupt Register 0 */ - -#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ -#define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */ -#define USIR0_IR2 (1 << 4) /* Interrup request ep 2 */ -#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ -#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ -#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ -#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ -#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ - -#define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */ - -#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ -#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ -#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ -#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ -#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ -#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ -#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ -#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ - - -#define UDCICR0 0x40600004 /* UDC Interrupt Control Register0 */ -#define UDCICR1 0x40600008 /* UDC Interrupt Control Register1 */ -#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ -#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ - -#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ -#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ -#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ -#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ - -#define UDCISR0 0x4060000C /* UDC Interrupt Status Register 0 */ -#define UDCISR1 0x40600010 /* UDC Interrupt Status Register 1 */ -#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */ -#define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */ -#define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */ -#define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */ - - -#define UDCFNR 0x40600014 /* UDC Frame Number Register */ -#define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */ -#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ -#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */ -#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge Interrupt Enable */ -#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge Interrupt Enable */ -#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */ -#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */ - -#define UDCCSN(x) (0x40600100 + ((x) << 2)) -#define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */ - -#define UDCCSR0_SA (1 << 7) /* Setup Active */ -#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ -#define UDCCSR0_FST (1 << 5) /* Force Stall */ -#define UDCCSR0_SST (1 << 4) /* Sent Stall */ -#define UDCCSR0_DME (1 << 3) /* DMA Enable */ -#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ -#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ -#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ - -#define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */ -#define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */ -#define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */ -#define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */ -#define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */ -#define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */ -#define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */ -#define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */ -#define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */ -#define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */ -#define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */ -#define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */ -#define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */ -#define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */ -#define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */ -#define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */ -#define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */ -#define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */ -#define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */ -#define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */ -#define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */ -#define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */ -#define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */ - -#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ -#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ -#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ -#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ -#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ -#define UDCCSR_FST (1 << 5) /* Force STALL */ -#define UDCCSR_SST (1 << 4) /* Sent STALL */ -#define UDCCSR_DME (1 << 3) /* DMA Enable */ -#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ -#define UDCCSR_PC (1 << 1) /* Packet Complete */ -#define UDCCSR_FS (1 << 0) /* FIFO needs service */ - -#define UDCBCN(x) (0x40600200 + ((x) << 2)) -#define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */ -#define UDCBCRA 0x40600204 /* Byte Count Register - EPA */ -#define UDCBCRB 0x40600208 /* Byte Count Register - EPB */ -#define UDCBCRC 0x4060020C /* Byte Count Register - EPC */ -#define UDCBCRD 0x40600210 /* Byte Count Register - EPD */ -#define UDCBCRE 0x40600214 /* Byte Count Register - EPE */ -#define UDCBCRF 0x40600218 /* Byte Count Register - EPF */ -#define UDCBCRG 0x4060021C /* Byte Count Register - EPG */ -#define UDCBCRH 0x40600220 /* Byte Count Register - EPH */ -#define UDCBCRI 0x40600224 /* Byte Count Register - EPI */ -#define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */ -#define UDCBCRK 0x4060022C /* Byte Count Register - EPK */ -#define UDCBCRL 0x40600230 /* Byte Count Register - EPL */ -#define UDCBCRM 0x40600234 /* Byte Count Register - EPM */ -#define UDCBCRN 0x40600238 /* Byte Count Register - EPN */ -#define UDCBCRP 0x4060023C /* Byte Count Register - EPP */ -#define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */ -#define UDCBCRR 0x40600244 /* Byte Count Register - EPR */ -#define UDCBCRS 0x40600248 /* Byte Count Register - EPS */ -#define UDCBCRT 0x4060024C /* Byte Count Register - EPT */ -#define UDCBCRU 0x40600250 /* Byte Count Register - EPU */ -#define UDCBCRV 0x40600254 /* Byte Count Register - EPV */ -#define UDCBCRW 0x40600258 /* Byte Count Register - EPW */ -#define UDCBCRX 0x4060025C /* Byte Count Register - EPX */ - -#define UDCDN(x) (0x40600300 + ((x) << 2)) -#define UDCDR0 0x40600300 /* Data Register - EP0 */ -#define UDCDRA 0x40600304 /* Data Register - EPA */ -#define UDCDRB 0x40600308 /* Data Register - EPB */ -#define UDCDRC 0x4060030C /* Data Register - EPC */ -#define UDCDRD 0x40600310 /* Data Register - EPD */ -#define UDCDRE 0x40600314 /* Data Register - EPE */ -#define UDCDRF 0x40600318 /* Data Register - EPF */ -#define UDCDRG 0x4060031C /* Data Register - EPG */ -#define UDCDRH 0x40600320 /* Data Register - EPH */ -#define UDCDRI 0x40600324 /* Data Register - EPI */ -#define UDCDRJ 0x40600328 /* Data Register - EPJ */ -#define UDCDRK 0x4060032C /* Data Register - EPK */ -#define UDCDRL 0x40600330 /* Data Register - EPL */ -#define UDCDRM 0x40600334 /* Data Register - EPM */ -#define UDCDRN 0x40600338 /* Data Register - EPN */ -#define UDCDRP 0x4060033C /* Data Register - EPP */ -#define UDCDRQ 0x40600340 /* Data Register - EPQ */ -#define UDCDRR 0x40600344 /* Data Register - EPR */ -#define UDCDRS 0x40600348 /* Data Register - EPS */ -#define UDCDRT 0x4060034C /* Data Register - EPT */ -#define UDCDRU 0x40600350 /* Data Register - EPU */ -#define UDCDRV 0x40600354 /* Data Register - EPV */ -#define UDCDRW 0x40600358 /* Data Register - EPW */ -#define UDCDRX 0x4060035C /* Data Register - EPX */ - -#define UDCCN(x) (0x40600400 + ((x) << 2)) -#define UDCCRA 0x40600404 /* Configuration register EPA */ -#define UDCCRB 0x40600408 /* Configuration register EPB */ -#define UDCCRC 0x4060040C /* Configuration register EPC */ -#define UDCCRD 0x40600410 /* Configuration register EPD */ -#define UDCCRE 0x40600414 /* Configuration register EPE */ -#define UDCCRF 0x40600418 /* Configuration register EPF */ -#define UDCCRG 0x4060041C /* Configuration register EPG */ -#define UDCCRH 0x40600420 /* Configuration register EPH */ -#define UDCCRI 0x40600424 /* Configuration register EPI */ -#define UDCCRJ 0x40600428 /* Configuration register EPJ */ -#define UDCCRK 0x4060042C /* Configuration register EPK */ -#define UDCCRL 0x40600430 /* Configuration register EPL */ -#define UDCCRM 0x40600434 /* Configuration register EPM */ -#define UDCCRN 0x40600438 /* Configuration register EPN */ -#define UDCCRP 0x4060043C /* Configuration register EPP */ -#define UDCCRQ 0x40600440 /* Configuration register EPQ */ -#define UDCCRR 0x40600444 /* Configuration register EPR */ -#define UDCCRS 0x40600448 /* Configuration register EPS */ -#define UDCCRT 0x4060044C /* Configuration register EPT */ -#define UDCCRU 0x40600450 /* Configuration register EPU */ -#define UDCCRV 0x40600454 /* Configuration register EPV */ -#define UDCCRW 0x40600458 /* Configuration register EPW */ -#define UDCCRX 0x4060045C /* Configuration register EPX */ - -#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ -#define UDCCONR_CN_S (25) -#define UDCCONR_IN (0x07 << 22) /* Interface Number */ -#define UDCCONR_IN_S (22) -#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ -#define UDCCONR_AISN_S (19) -#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ -#define UDCCONR_EN_S (15) -#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ -#define UDCCONR_ET_S (13) -#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ -#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ -#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ -#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ -#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ -#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ -#define UDCCONR_MPS_S (2) -#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ -#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ - - -#define UDC_INT_FIFOERROR (0x2) -#define UDC_INT_PACKETCMP (0x1) -#define UDC_FNR_MASK (0x7ff) -#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) -#define UDC_BCR_MASK (0x3ff) - -#endif /* CONFIG_CPU_PXA27X */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - -/******************************************************************************/ -/* - * USB Host Controller - */ -#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */ -#define UHCREV 0x4C000000 -#define UHCHCON 0x4C000004 -#define UHCCOMS 0x4C000008 -#define UHCINTS 0x4C00000C -#define UHCINTE 0x4C000010 -#define UHCINTD 0x4C000014 -#define UHCHCCA 0x4C000018 -#define UHCPCED 0x4C00001C -#define UHCCHED 0x4C000020 -#define UHCCCED 0x4C000024 -#define UHCBHED 0x4C000028 -#define UHCBCED 0x4C00002C -#define UHCDHEAD 0x4C000030 -#define UHCFMI 0x4C000034 -#define UHCFMR 0x4C000038 -#define UHCFMN 0x4C00003C -#define UHCPERS 0x4C000040 -#define UHCLST 0x4C000044 -#define UHCRHDA 0x4C000048 -#define UHCRHDB 0x4C00004C -#define UHCRHS 0x4C000050 -#define UHCRHPS1 0x4C000054 -#define UHCRHPS2 0x4C000058 -#define UHCRHPS3 0x4C00005C -#define UHCSTAT 0x4C000060 -#define UHCHR 0x4C000064 -#define UHCHIE 0x4C000068 -#define UHCHIT 0x4C00006C - -#define UHCCOMS_HCR (1<<0) - -#define UHCHR_FSBIR (1<<0) -#define UHCHR_FHR (1<<1) -#define UHCHR_CGR (1<<2) -#define UHCHR_SSDC (1<<3) -#define UHCHR_UIT (1<<4) -#define UHCHR_SSE (1<<5) -#define UHCHR_PSPL (1<<6) -#define UHCHR_PCPL (1<<7) -#define UHCHR_SSEP0 (1<<9) -#define UHCHR_SSEP1 (1<<10) -#define UHCHR_SSEP2 (1<<11) - -#define UHCHIE_UPRIE (1<<13) -#define UHCHIE_UPS2IE (1<<12) -#define UHCHIE_UPS1IE (1<<11) -#define UHCHIE_TAIE (1<<10) -#define UHCHIE_HBAIE (1<<8) -#define UHCHIE_RWIE (1<<7) - -#define UP2OCR 0x40600020 - -#define UP2OCR_HXOE (1<<17) -#define UP2OCR_HXS (1<<16) -#define UP2OCR_IDON (1<<10) -#define UP2OCR_EXSUS (1<<9) -#define UP2OCR_EXSP (1<<8) -#define UP2OCR_DMSTATE (1<<7) -#define UP2OCR_VPM (1<<6) -#define UP2OCR_DPSTATE (1<<5) -#define UP2OCR_DPPUE (1<<4) -#define UP2OCR_DMPDE (1<<3) -#define UP2OCR_DPPDE (1<<2) -#define UP2OCR_CPVPE (1<<1) -#define UP2OCR_CPVEN (1<<0) - -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * Fast Infrared Communication Port - */ -#define ICCR0 0x40800000 /* ICP Control Register 0 */ -#define ICCR1 0x40800004 /* ICP Control Register 1 */ -#define ICCR2 0x40800008 /* ICP Control Register 2 */ -#define ICDR 0x4080000c /* ICP Data Register */ -#define ICSR0 0x40800014 /* ICP Status Register 0 */ -#define ICSR1 0x40800018 /* ICP Status Register 1 */ - -/* - * Real Time Clock - */ -#define RCNR 0x40900000 /* RTC Count Register */ -#define RTAR 0x40900004 /* RTC Alarm Register */ -#define RTSR 0x40900008 /* RTC Status Register */ -#define RTTR 0x4090000C /* RTC Timer Trim Register */ -#define RDAR1 0x40900018 /* Wristwatch Day Alarm Reg 1 */ -#define RDAR2 0x40900020 /* Wristwatch Day Alarm Reg 2 */ -#define RYAR1 0x4090001C /* Wristwatch Year Alarm Reg 1 */ -#define RYAR2 0x40900024 /* Wristwatch Year Alarm Reg 2 */ -#define SWAR1 0x4090002C /* Stopwatch Alarm Register 1 */ -#define SWAR2 0x40900030 /* Stopwatch Alarm Register 2 */ -#define PIAR 0x40900038 /* Periodic Interrupt Alarm Register */ -#define RDCR 0x40900010 /* RTC Day Count Register. */ -#define RYCR 0x40900014 /* RTC Year Count Register. */ -#define SWCR 0x40900028 /* Stopwatch Count Register */ -#define RTCPICR 0x40900034 /* Periodic Interrupt Counter Register */ - -#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ -#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ -#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */ -#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ -#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ -#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ -#define RTSR_AL (1 << 0) /* RTC alarm detected */ - -/******************************************************************************/ -/* - * OS Timer & Match Registers - */ -#define OSMR0 0x40A00000 /* OS Timer Match Register 0 */ -#define OSMR1 0x40A00004 /* OS Timer Match Register 1 */ -#define OSMR2 0x40A00008 /* OS Timer Match Register 2 */ -#define OSMR3 0x40A0000C /* OS Timer Match Register 3 */ -#define OSCR 0x40A00010 /* OS Timer Counter Register */ -#define OSSR 0x40A00014 /* OS Timer Status Register */ -#define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */ -#define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */ -#define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */ -#define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */ -#define OSCR7 0x40A0004C /* OS Timer Counter Register 7 */ -#define OSCR8 0x40A00050 /* OS Timer Counter Register 8 */ -#define OSCR9 0x40A00054 /* OS Timer Counter Register 9 */ -#define OSCR10 0x40A00058 /* OS Timer Counter Register 10 */ -#define OSCR11 0x40A0005C /* OS Timer Counter Register 11 */ - -#define OSMR4 0x40A00080 /* OS Timer Match Register 4 */ -#define OSMR5 0x40A00084 /* OS Timer Match Register 5 */ -#define OSMR6 0x40A00088 /* OS Timer Match Register 6 */ -#define OSMR7 0x40A0008C /* OS Timer Match Register 7 */ -#define OSMR8 0x40A00090 /* OS Timer Match Register 8 */ -#define OSMR9 0x40A00094 /* OS Timer Match Register 9 */ -#define OSMR10 0x40A00098 /* OS Timer Match Register 10 */ -#define OSMR11 0x40A0009C /* OS Timer Match Register 11 */ - -#define OMCR4 0x40A000C0 /* OS Match Control Register 4 */ -#define OMCR5 0x40A000C4 /* OS Match Control Register 5 */ -#define OMCR6 0x40A000C8 /* OS Match Control Register 6 */ -#define OMCR7 0x40A000CC /* OS Match Control Register 7 */ -#define OMCR8 0x40A000D0 /* OS Match Control Register 8 */ -#define OMCR9 0x40A000D4 /* OS Match Control Register 9 */ -#define OMCR10 0x40A000D8 /* OS Match Control Register 10 */ -#define OMCR11 0x40A000DC /* OS Match Control Register 11 */ - -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#define OSSR_M4 (1 << 4) /* Match status channel 4 */ -#define OSSR_M3 (1 << 3) /* Match status channel 3 */ -#define OSSR_M2 (1 << 2) /* Match status channel 2 */ -#define OSSR_M1 (1 << 1) /* Match status channel 1 */ -#define OSSR_M0 (1 << 0) /* Match status channel 0 */ - -#define OWER_WME (1 << 0) /* Watchdog Match Enable */ - -#define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */ -#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ -#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ -#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ -#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ - -#define OSCR_CLK_FREQ 3250 - -/******************************************************************************/ -/* - * Core Clock - */ - -#if defined(CONFIG_CPU_MONAHANS) -#define ACCR 0x41340000 /* Application Subsystem Clock Configuration Register */ -#define ACSR 0x41340004 /* Application Subsystem Clock Status Register */ -#define AICSR 0x41340008 /* Application Subsystem Interrupt Control/Status Register */ -#define CKENA 0x4134000C /* A Clock Enable Register */ -#define CKENB 0x41340010 /* B Clock Enable Register */ -#define AC97_DIV 0x41340014 /* AC97 clock divisor value register */ - -#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ -#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ -#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ -#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ -#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ -#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define ACCR_XPDIS (1 << 31) -#define ACCR_SPDIS (1 << 30) -#define ACCR_13MEND1 (1 << 27) -#define ACCR_D0CS (1 << 26) -#define ACCR_13MEND2 (1 << 21) -#define ACCR_PCCE (1 << 11) - -#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ -#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ -#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ -#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ -#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ -#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ -#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ -#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ -#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ -#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ -#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ -#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ -#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ -#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ -#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ -#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ -#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ -#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ -#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ -#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ -#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ -#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ -#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ -#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ -#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ -#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ -#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ -#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ - -#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ -#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ - -#else /* if defined CONFIG_CPU_MONAHANS */ - -#define CCCR 0x41300000 /* Core Clock Configuration Register */ -#define CKEN 0x41300004 /* Clock Enable Register */ -#define OSCC 0x41300008 /* Oscillator Configuration Register */ -#define CCSR 0x4130000C /* Core Clock Status Register */ - -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controler */ -#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ -#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ -#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ -#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_CPU_PXA27X) -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#endif -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ - -#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ -#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ -#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ -#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_CPU_PXA27X) -#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ -#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ -#endif -#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - -#if !defined(CONFIG_CPU_PXA27X) -#define CCCR_L09 (0x1F) -#define CCCR_L27 (0x1) -#define CCCR_L32 (0x2) -#define CCCR_L36 (0x3) -#define CCCR_L40 (0x4) -#define CCCR_L45 (0x5) - -#define CCCR_M1 (0x1 << 5) -#define CCCR_M2 (0x2 << 5) -#define CCCR_M4 (0x3 << 5) - -#define CCCR_N10 (0x2 << 7) -#define CCCR_N15 (0x3 << 7) -#define CCCR_N20 (0x4 << 7) -#define CCCR_N25 (0x5 << 7) -#define CCCR_N30 (0x6 << 7) -#endif - -#endif /* CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * Pulse Width Modulator - */ -#define PWM_CTRL0 0x40B00000 /* PWM 0 Control Register */ -#define PWM_PWDUTY0 0x40B00004 /* PWM 0 Duty Cycle Register */ -#define PWM_PERVAL0 0x40B00008 /* PWM 0 Period Control Register */ - -#define PWM_CTRL1 0x40C00000 /* PWM 1 Control Register */ -#define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */ -#define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */ -#define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */ -#define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */ - -#define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */ -#define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */ -#define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/* - * Interrupt Controller - */ -#define ICIP 0x40D00000 /* Interrupt Controller IRQ Pending Register */ -#define ICMR 0x40D00004 /* Interrupt Controller Mask Register */ -#define ICLR 0x40D00008 /* Interrupt Controller Level Register */ -#define ICFP 0x40D0000C /* Interrupt Controller FIQ Pending Register */ -#define ICPR 0x40D00010 /* Interrupt Controller Pending Register */ -#define ICCR 0x40D00014 /* Interrupt Controller Control Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */ -#define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */ -#define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */ -#define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * General Purpose I/O - */ -#define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ -#define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */ -#define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */ - -#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */ -#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */ -#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */ - -#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */ -#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */ -#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */ - -#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */ -#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ - -#define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */ -#define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */ -#define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */ - -#define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */ -#define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */ - -#define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */ -#define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */ -#define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */ - -#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */ -#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */ -#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */ -#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */ -#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ -#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */ -#define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */ -#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ -#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ -#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#ifdef CONFIG_CPU_MONAHANS -#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ -#define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */ -#define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */ -#define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */ - -#define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */ -#define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */ -#define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */ -#define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */ - -#define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */ -#define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */ -#define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */ -#define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */ - -#define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */ -#define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */ -#define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */ -#define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */ - -#define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */ -#define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */ -#define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */ -#define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */ - -#define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */ -#define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */ -#define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */ -#define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */ - -#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3) -#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3) -#endif - -#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3)) -#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3)) -#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3)) -#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3)) -#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3)) -#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3)) -#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) -#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) -#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) -#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) -#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)) -#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)) -#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)) -#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)) -#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))) -#else -#define GPLR(x) _GPLR(x) -#define GPDR(x) _GPDR(x) -#define GPSR(x) _GPSR(x) -#define GPCR(x) _GPCR(x) -#define GRER(x) _GRER(x) -#define GFER(x) _GFER(x) -#define GEDR(x) _GEDR(x) -#define GAFR(x) _GAFR(x) -#endif - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -/******************************************************************************/ -/* - * Multi-function Pin Registers: - */ -/* PXA320 */ -#if defined(CONFIG_CPU_PXA320) -#define DF_IO0 0x40e1024c -#define DF_IO1 0x40e10254 -#define DF_IO2 0x40e1025c -#define DF_IO3 0x40e10264 -#define DF_IO4 0x40e1026c -#define DF_IO5 0x40e10274 -#define DF_IO6 0x40e1027c -#define DF_IO7 0x40e10284 -#define DF_IO8 0x40e10250 -#define DF_IO9 0x40e10258 -#define DF_IO10 0x40e10260 -#define DF_IO11 0x40e10268 -#define DF_IO12 0x40e10270 -#define DF_IO13 0x40e10278 -#define DF_IO14 0x40e10280 -#define DF_IO15 0x40e10288 -#define DF_CLE_nOE 0x40e10204 -#define DF_ALE_nWE1 0x40e10208 -#define DF_ALE_nWE2 0x40e1021c -#define DF_SCLK_E 0x40e10210 -#define DF_nCS0 0x40e10224 -#define DF_nCS1 0x40e10228 -#define nBE0 0x40e10214 -#define nBE1 0x40e10218 -#define nLUA 0x40e10234 -#define nLLA 0x40e10238 -#define DF_ADDR0 0x40e1023c -#define DF_ADDR1 0x40e10240 -#define DF_ADDR2 0x40e10244 -#define DF_ADDR3 0x40e10248 -#define DF_INT_RnB 0x40e10220 -#define DF_nCS0 0x40e10224 -#define DF_nCS1 0x40e10228 -#define DF_nWE 0x40e1022c -#define DF_nRE 0x40e10230 - -#define nXCVREN 0x40e10138 - -#define GPIO0 0x40e10124 -#define GPIO1 0x40e10128 -#define GPIO2 0x40e1012c -#define GPIO3 0x40e10130 -#define GPIO4 0x40e10134 -#define GPIO5 0x40e1028c -#define GPIO6 0x40e10290 -#define GPIO7 0x40e10294 -#define GPIO8 0x40e10298 -#define GPIO9 0x40e1029c -#define GPIO10 0x40e10458 -#define GPIO11 0x40e102a0 -#define GPIO12 0x40e102a4 -#define GPIO13 0x40e102a8 -#define GPIO14 0x40e102ac -#define GPIO15 0x40e102b0 -#define GPIO16 0x40e102b4 -#define GPIO17 0x40e102b8 -#define GPIO18 0x40e102bc -#define GPIO19 0x40e102c0 -#define GPIO20 0x40e102c4 -#define GPIO21 0x40e102c8 -#define GPIO22 0x40e102cc -#define GPIO23 0x40e102d0 -#define GPIO24 0x40e102d4 -#define GPIO25 0x40e102d8 -#define GPIO26 0x40e102dc - -#define GPIO27 0x40e10400 -#define GPIO28 0x40e10404 -#define GPIO29 0x40e10408 -#define GPIO30 0x40e1040c -#define GPIO31 0x40e10410 -#define GPIO32 0x40e10414 -#define GPIO33 0x40e10418 -#define GPIO34 0x40e1041c -#define GPIO35 0x40e10420 -#define GPIO36 0x40e10424 -#define GPIO37 0x40e10428 -#define GPIO38 0x40e1042c -#define GPIO39 0x40e10430 -#define GPIO40 0x40e10434 -#define GPIO41 0x40e10438 -#define GPIO42 0x40e1043c -#define GPIO43 0x40e10440 -#define GPIO44 0x40e10444 -#define GPIO45 0x40e10448 -#define GPIO46 0x40e1044c -#define GPIO47 0x40e10450 -#define GPIO48 0x40e10454 -#define GPIO49 0x40e1045c -#define GPIO50 0x40e10460 -#define GPIO51 0x40e10464 -#define GPIO52 0x40e10468 -#define GPIO53 0x40e1046c -#define GPIO54 0x40e10470 -#define GPIO55 0x40e10474 -#define GPIO56 0x40e10478 -#define GPIO57 0x40e1047c -#define GPIO58 0x40e10480 -#define GPIO59 0x40e10484 -#define GPIO60 0x40e10488 -#define GPIO61 0x40e1048c -#define GPIO62 0x40e10490 - -#define GPIO6_2 0x40e10494 -#define GPIO7_2 0x40e10498 -#define GPIO8_2 0x40e1049c -#define GPIO9_2 0x40e104a0 -#define GPIO10_2 0x40e104a4 -#define GPIO11_2 0x40e104a8 -#define GPIO12_2 0x40e104ac -#define GPIO13_2 0x40e104b0 - -#define GPIO63 0x40e104b4 -#define GPIO64 0x40e104b8 -#define GPIO65 0x40e104bc -#define GPIO66 0x40e104c0 -#define GPIO67 0x40e104c4 -#define GPIO68 0x40e104c8 -#define GPIO69 0x40e104cc -#define GPIO70 0x40e104d0 -#define GPIO71 0x40e104d4 -#define GPIO72 0x40e104d8 -#define GPIO73 0x40e104dc - -#define GPIO14_2 0x40e104e0 -#define GPIO15_2 0x40e104e4 -#define GPIO16_2 0x40e104e8 -#define GPIO17_2 0x40e104ec - -#define GPIO74 0x40e104f0 -#define GPIO75 0x40e104f4 -#define GPIO76 0x40e104f8 -#define GPIO77 0x40e104fc -#define GPIO78 0x40e10500 -#define GPIO79 0x40e10504 -#define GPIO80 0x40e10508 -#define GPIO81 0x40e1050c -#define GPIO82 0x40e10510 -#define GPIO83 0x40e10514 -#define GPIO84 0x40e10518 -#define GPIO85 0x40e1051c -#define GPIO86 0x40e10520 -#define GPIO87 0x40e10524 -#define GPIO88 0x40e10528 -#define GPIO89 0x40e1052c -#define GPIO90 0x40e10530 -#define GPIO91 0x40e10534 -#define GPIO92 0x40e10538 -#define GPIO93 0x40e1053c -#define GPIO94 0x40e10540 -#define GPIO95 0x40e10544 -#define GPIO96 0x40e10548 -#define GPIO97 0x40e1054c -#define GPIO98 0x40e10550 - -#define GPIO99 0x40e10600 -#define GPIO100 0x40e10604 -#define GPIO101 0x40e10608 -#define GPIO102 0x40e1060c -#define GPIO103 0x40e10610 -#define GPIO104 0x40e10614 -#define GPIO105 0x40e10618 -#define GPIO106 0x40e1061c -#define GPIO107 0x40e10620 -#define GPIO108 0x40e10624 -#define GPIO109 0x40e10628 -#define GPIO110 0x40e1062c -#define GPIO111 0x40e10630 -#define GPIO112 0x40e10634 - -#define GPIO113 0x40e10638 -#define GPIO114 0x40e1063c -#define GPIO115 0x40e10640 -#define GPIO116 0x40e10644 -#define GPIO117 0x40e10648 -#define GPIO118 0x40e1064c -#define GPIO119 0x40e10650 -#define GPIO120 0x40e10654 -#define GPIO121 0x40e10658 -#define GPIO122 0x40e1065c -#define GPIO123 0x40e10660 -#define GPIO124 0x40e10664 -#define GPIO125 0x40e10668 -#define GPIO126 0x40e1066c -#define GPIO127 0x40e10670 - -#define GPIO0_2 0x40e10674 -#define GPIO1_2 0x40e10678 -#define GPIO2_2 0x40e1067c -#define GPIO3_2 0x40e10680 -#define GPIO4_2 0x40e10684 -#define GPIO5_2 0x40e10688 - -/* PXA300 and PXA310 */ -#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310) -#define DF_IO0 0x40e10220 -#define DF_IO1 0x40e10228 -#define DF_IO2 0x40e10230 -#define DF_IO3 0x40e10238 -#define DF_IO4 0x40e10258 -#define DF_IO5 0x40e10260 -#define DF_IO7 0x40e10270 -#define DF_IO6 0x40e10268 -#define DF_IO8 0x40e10224 -#define DF_IO9 0x40e1022c -#define DF_IO10 0x40e10234 -#define DF_IO11 0x40e1023c -#define DF_IO12 0x40e1025c -#define DF_IO13 0x40e10264 -#define DF_IO14 0x40e1026c -#define DF_IO15 0x40e10274 -#define DF_CLE_NOE 0x40e10240 -#define DF_ALE_nWE 0x40e1020c -#define DF_SCLK_E 0x40e10250 -#define nCS0 0x40e100c4 -#define nCS1 0x40e100c0 -#define nBE0 0x40e10204 -#define nBE1 0x40e10208 -#define nLUA 0x40e10244 -#define nLLA 0x40e10254 -#define DF_ADDR0 0x40e10210 -#define DF_ADDR1 0x40e10214 -#define DF_ADDR2 0x40e10218 -#define DF_ADDR3 0x40e1021c -#define DF_INT_RnB 0x40e100c8 -#define DF_nCS0 0x40e10248 -#define DF_nCS1 0x40e10278 -#define DF_nWE 0x40e100cc -#define DF_nRE 0x40e10200 - -#define GPIO0 0x40e100b4 -#define GPIO1 0x40e100b8 -#define GPIO2 0x40e100bc -#define GPIO3 0x40e1027c -#define GPIO4 0x40e10280 - -#define GPIO5 0x40e10284 -#define GPIO6 0x40e10288 -#define GPIO7 0x40e1028c -#define GPIO8 0x40e10290 -#define GPIO9 0x40e10294 -#define GPIO10 0x40e10298 -#define GPIO11 0x40e1029c -#define GPIO12 0x40e102a0 -#define GPIO13 0x40e102a4 -#define GPIO14 0x40e102a8 -#define GPIO15 0x40e102ac -#define GPIO16 0x40e102b0 -#define GPIO17 0x40e102b4 -#define GPIO18 0x40e102b8 -#define GPIO19 0x40e102bc -#define GPIO20 0x40e102c0 -#define GPIO21 0x40e102c4 -#define GPIO22 0x40e102c8 -#define GPIO23 0x40e102cc -#define GPIO24 0x40e102d0 -#define GPIO25 0x40e102d4 -#define GPIO26 0x40e102d8 - -#define GPIO27 0x40e10400 -#define GPIO28 0x40e10404 -#define GPIO29 0x40e10408 -#define ULPI_STP 0x40e1040c -#define ULPI_NXT 0x40e10410 -#define ULPI_DIR 0x40e10414 -#define GPIO30 0x40e10418 -#define GPIO31 0x40e1041c -#define GPIO32 0x40e10420 -#define GPIO33 0x40e10424 -#define GPIO34 0x40e10428 -#define GPIO35 0x40e1042c -#define GPIO36 0x40e10430 -#define GPIO37 0x40e10434 -#define GPIO38 0x40e10438 -#define GPIO39 0x40e1043c -#define GPIO40 0x40e10440 -#define GPIO41 0x40e10444 -#define GPIO42 0x40e10448 -#define GPIO43 0x40e1044c -#define GPIO44 0x40e10450 -#define GPIO45 0x40e10454 -#define GPIO46 0x40e10458 -#define GPIO47 0x40e1045c -#define GPIO48 0x40e10460 - -#define GPIO49 0x40e10464 -#define GPIO50 0x40e10468 -#define GPIO51 0x40e1046c -#define GPIO52 0x40e10470 -#define GPIO53 0x40e10474 -#define GPIO54 0x40e10478 -#define GPIO55 0x40e1047c -#define GPIO56 0x40e10480 -#define GPIO57 0x40e10484 -#define GPIO58 0x40e10488 -#define GPIO59 0x40e1048c -#define GPIO60 0x40e10490 -#define GPIO61 0x40e10494 -#define GPIO62 0x40e10498 -#define GPIO63 0x40e1049c -#define GPIO64 0x40e104a0 -#define GPIO65 0x40e104a4 -#define GPIO66 0x40e104a8 -#define GPIO67 0x40e104ac -#define GPIO68 0x40e104b0 -#define GPIO69 0x40e104b4 -#define GPIO70 0x40e104b8 -#define GPIO71 0x40e104bc -#define GPIO72 0x40e104c0 -#define GPIO73 0x40e104c4 -#define GPIO74 0x40e104c8 -#define GPIO75 0x40e104cc -#define GPIO76 0x40e104d0 -#define GPIO77 0x40e104d4 -#define GPIO78 0x40e104d8 -#define GPIO79 0x40e104dc -#define GPIO80 0x40e104e0 -#define GPIO81 0x40e104e4 -#define GPIO82 0x40e104e8 -#define GPIO83 0x40e104ec -#define GPIO84 0x40e104f0 -#define GPIO85 0x40e104f4 -#define GPIO86 0x40e104f8 -#define GPIO87 0x40e104fc -#define GPIO88 0x40e10500 -#define GPIO89 0x40e10504 -#define GPIO90 0x40e10508 -#define GPIO91 0x40e1050c -#define GPIO92 0x40e10510 -#define GPIO93 0x40e10514 -#define GPIO94 0x40e10518 -#define GPIO95 0x40e1051c -#define GPIO96 0x40e10520 -#define GPIO97 0x40e10524 -#define GPIO98 0x40e10528 - -#define GPIO99 0x40e10600 -#define GPIO100 0x40e10604 -#define GPIO101 0x40e10608 -#define GPIO102 0x40e1060c -#define GPIO103 0x40e10610 -#define GPIO104 0x40e10614 -#define GPIO105 0x40e10618 -#define GPIO106 0x40e1061c -#define GPIO107 0x40e10620 -#define GPIO108 0x40e10624 -#define GPIO109 0x40e10628 -#define GPIO110 0x40e1062c -#define GPIO111 0x40e10630 -#define GPIO112 0x40e10634 - -#define GPIO113 0x40e10638 -#define GPIO114 0x40e1063c -#define GPIO115 0x40e10640 -#define GPIO116 0x40e10644 -#define GPIO117 0x40e10648 -#define GPIO118 0x40e1064c -#define GPIO119 0x40e10650 -#define GPIO120 0x40e10654 -#define GPIO121 0x40e10658 -#define GPIO122 0x40e1065c -#define GPIO123 0x40e10660 -#define GPIO124 0x40e10664 -#define GPIO125 0x40e10668 -#define GPIO126 0x40e1066c -#define GPIO127 0x40e10670 - -#define GPIO0_2 0x40e10674 -#define GPIO1_2 0x40e10678 -#define GPIO2_2 0x40e102dc -#define GPIO3_2 0x40e102e0 -#define GPIO4_2 0x40e102e4 -#define GPIO5_2 0x40e102e8 -#define GPIO6_2 0x40e102ec - -#ifndef CONFIG_CPU_PXA300 /* PXA310 only */ -#define GPIO7_2 0x40e1052c -#define GPIO8_2 0x40e10530 -#define GPIO9_2 0x40e10534 -#define GPIO10_2 0x40e10538 -#endif -#endif - -#ifdef CONFIG_CPU_MONAHANS -/* MFPR Bit Definitions, see 4-10, Vol. 1 */ -#define PULL_SEL 0x8000 -#define PULLUP_EN 0x4000 -#define PULLDOWN_EN 0x2000 - -#define DRIVE_FAST_1mA 0x0 -#define DRIVE_FAST_2mA 0x400 -#define DRIVE_FAST_3mA 0x800 -#define DRIVE_FAST_4mA 0xC00 -#define DRIVE_SLOW_6mA 0x1000 -#define DRIVE_FAST_6mA 0x1400 -#define DRIVE_SLOW_10mA 0x1800 -#define DRIVE_FAST_10mA 0x1C00 - -#define SLEEP_SEL 0x200 -#define SLEEP_DATA 0x100 -#define SLEEP_OE_N 0x80 -#define EDGE_CLEAR 0x40 -#define EDGE_FALL_EN 0x20 -#define EDGE_RISE_EN 0x10 - -#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */ -#define AF_SEL_1 0x1 /* Alternate function 1 */ -#define AF_SEL_2 0x2 /* Alternate function 2 */ -#define AF_SEL_3 0x3 /* Alternate function 3 */ -#define AF_SEL_4 0x4 /* Alternate function 4 */ -#define AF_SEL_5 0x5 /* Alternate function 5 */ -#define AF_SEL_6 0x6 /* Alternate function 6 */ -#define AF_SEL_7 0x7 /* Alternate function 7 */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* GPIO alternate function assignments */ - -#define GPIO1_RST 1 /* reset */ -#define GPIO6_MMCCLK 6 /* MMC Clock */ -#define GPIO8_48MHz 7 /* 48 MHz clock output */ -#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ -#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ -#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ -#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ -#define GPIO12_32KHz 12 /* 32 kHz out */ -#define GPIO13_MBGNT 13 /* memory controller grant */ -#define GPIO14_MBREQ 14 /* alternate bus master request */ -#define GPIO15_nCS_1 15 /* chip select 1 */ -#define GPIO16_PWM0 16 /* PWM0 output */ -#define GPIO17_PWM1 17 /* PWM1 output */ -#define GPIO18_RDY 18 /* Ext. Bus Ready */ -#define GPIO19_DREQ1 19 /* External DMA Request */ -#define GPIO20_DREQ0 20 /* External DMA Request */ -#define GPIO23_SCLK 23 /* SSP clock */ -#define GPIO24_SFRM 24 /* SSP Frame */ -#define GPIO25_STXD 25 /* SSP transmit */ -#define GPIO26_SRXD 26 /* SSP receive */ -#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ -#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ -#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ -#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ -#define GPIO31_SYNC 31 /* AC97/I2S sync */ -#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ -#define GPIO33_nCS_5 33 /* chip select 5 */ -#define GPIO34_FFRXD 34 /* FFUART receive */ -#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ -#define GPIO35_FFCTS 35 /* FFUART Clear to send */ -#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ -#define GPIO37_FFDSR 37 /* FFUART data set ready */ -#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ -#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ -#define GPIO39_FFTXD 39 /* FFUART transmit data */ -#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ -#define GPIO41_FFRTS 41 /* FFUART request to send */ -#define GPIO42_BTRXD 42 /* BTUART receive data */ -#define GPIO43_BTTXD 43 /* BTUART transmit data */ -#define GPIO44_BTCTS 44 /* BTUART clear to send */ -#define GPIO45_BTRTS 45 /* BTUART request to send */ -#define GPIO46_ICPRXD 46 /* ICP receive data */ -#define GPIO46_STRXD 46 /* STD_UART receive data */ -#define GPIO47_ICPTXD 47 /* ICP transmit data */ -#define GPIO47_STTXD 47 /* STD_UART transmit data */ -#define GPIO48_nPOE 48 /* Output Enable for Card Space */ -#define GPIO49_nPWE 49 /* Write Enable for Card Space */ -#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ -#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ -#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ -#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ -#define GPIO53_MMCCLK 53 /* MMC Clock */ -#define GPIO54_MMCCLK 54 /* MMC Clock */ -#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ -#define GPIO55_nPREG 55 /* Card Address bit 26 */ -#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ -#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ -#define GPIO58_LDD_0 58 /* LCD data pin 0 */ -#define GPIO59_LDD_1 59 /* LCD data pin 1 */ -#define GPIO60_LDD_2 60 /* LCD data pin 2 */ -#define GPIO61_LDD_3 61 /* LCD data pin 3 */ -#define GPIO62_LDD_4 62 /* LCD data pin 4 */ -#define GPIO63_LDD_5 63 /* LCD data pin 5 */ -#define GPIO64_LDD_6 64 /* LCD data pin 6 */ -#define GPIO65_LDD_7 65 /* LCD data pin 7 */ -#define GPIO66_LDD_8 66 /* LCD data pin 8 */ -#define GPIO66_MBREQ 66 /* alternate bus master req */ -#define GPIO67_LDD_9 67 /* LCD data pin 9 */ -#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ -#define GPIO68_LDD_10 68 /* LCD data pin 10 */ -#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ -#define GPIO69_LDD_11 69 /* LCD data pin 11 */ -#define GPIO69_MMCCLK 69 /* MMC_CLK */ -#define GPIO70_LDD_12 70 /* LCD data pin 12 */ -#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ -#define GPIO71_LDD_13 71 /* LCD data pin 13 */ -#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ -#define GPIO72_LDD_14 72 /* LCD data pin 14 */ -#define GPIO72_32kHz 72 /* 32 kHz clock */ -#define GPIO73_LDD_15 73 /* LCD data pin 15 */ -#define GPIO73_MBGNT 73 /* Memory controller grant */ -#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ -#define GPIO75_LCD_LCLK 75 /* LCD line clock */ -#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ -#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ -#define GPIO78_nCS_2 78 /* chip select 2 */ -#define GPIO79_nCS_3 79 /* chip select 3 */ -#define GPIO80_nCS_4 80 /* chip select 4 */ - -/* GPIO alternate function mode & direction */ - -#define GPIO_IN 0x000 -#define GPIO_OUT 0x080 -#define GPIO_ALT_FN_1_IN 0x100 -#define GPIO_ALT_FN_1_OUT 0x180 -#define GPIO_ALT_FN_2_IN 0x200 -#define GPIO_ALT_FN_2_OUT 0x280 -#define GPIO_ALT_FN_3_IN 0x300 -#define GPIO_ALT_FN_3_OUT 0x380 -#define GPIO_MD_MASK_NR 0x07f -#define GPIO_MD_MASK_DIR 0x080 -#define GPIO_MD_MASK_FN 0x300 - -#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) -#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) -#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) -#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) -#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) -#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) -#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) -#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) -#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) -#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) -#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) -#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) -#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) -#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) -#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) -#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) -#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) -#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) -#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) -#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) -#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) -#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) -#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) -#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) -#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) -#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) -#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) -#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) -#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) -#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) -#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) -#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) -#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) -#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) -#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) -#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) -#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) -#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) -#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) -#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) -#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) -#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) -#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) -#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) -#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) -#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) -#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) -#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) -#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) -#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) -#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) -#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) -#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) -#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) -#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) -#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) -#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) -#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) -#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) -#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) -#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) -#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) -#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) -#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) -#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) -#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) -#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) -#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) -#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) -#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) -#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) -#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) -#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) -#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) -#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) -#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) -#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) -#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) -#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) -#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) -#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) -#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) - -#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) -#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) - -/* - * Power Manager - */ -#ifdef CONFIG_CPU_MONAHANS - -#define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */ -#define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */ -#define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */ -#define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */ -#define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */ -#define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */ -#define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */ -#define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */ -#define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */ -#define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */ -#define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */ -#define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */ -#define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */ -#define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */ - -#define PMCR 0x40F50000 /* Power Manager Control Register */ -#define PSR 0x40F50004 /* Power Manager S2 Status Register */ -#define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */ -#define PCFR 0x40F5000C /* Power Manager General Configuration Register */ -#define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */ -#define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */ -#define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */ -#define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */ -#define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */ -#define PCMD(x) (0x40F50110 + x*4) -#define PCMD0 (0x40F50110 + 0 * 4) -#define PCMD1 (0x40F50110 + 1 * 4) -#define PCMD2 (0x40F50110 + 2 * 4) -#define PCMD3 (0x40F50110 + 3 * 4) -#define PCMD4 (0x40F50110 + 4 * 4) -#define PCMD5 (0x40F50110 + 5 * 4) -#define PCMD6 (0x40F50110 + 6 * 4) -#define PCMD7 (0x40F50110 + 7 * 4) -#define PCMD8 (0x40F50110 + 8 * 4) -#define PCMD9 (0x40F50110 + 9 * 4) -#define PCMD10 (0x40F50110 + 10 * 4) -#define PCMD11 (0x40F50110 + 11 * 4) -#define PCMD12 (0x40F50110 + 12 * 4) -#define PCMD13 (0x40F50110 + 13 * 4) -#define PCMD14 (0x40F50110 + 14 * 4) -#define PCMD15 (0x40F50110 + 15 * 4) -#define PCMD16 (0x40F50110 + 16 * 4) -#define PCMD17 (0x40F50110 + 17 * 4) -#define PCMD18 (0x40F50110 + 18 * 4) -#define PCMD19 (0x40F50110 + 19 * 4) -#define PCMD20 (0x40F50110 + 20 * 4) -#define PCMD21 (0x40F50110 + 21 * 4) -#define PCMD22 (0x40F50110 + 22 * 4) -#define PCMD23 (0x40F50110 + 23 * 4) -#define PCMD24 (0x40F50110 + 24 * 4) -#define PCMD25 (0x40F50110 + 25 * 4) -#define PCMD26 (0x40F50110 + 26 * 4) -#define PCMD27 (0x40F50110 + 27 * 4) -#define PCMD28 (0x40F50110 + 28 * 4) -#define PCMD29 (0x40F50110 + 29 * 4) -#define PCMD30 (0x40F50110 + 30 * 4) -#define PCMD31 (0x40F50110 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */ - -#define PVCR_FVC (0x1 << 28) -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -#define PVCR_ReadPointer 0x01f00000 -#define PVCR_SlaveAddress (0x7f) - -#else /* ifdef CONFIG_CPU_MONAHANS */ - -#define PMCR 0x40F00000 /* Power Manager Control Register */ -#define PSSR 0x40F00004 /* Power Manager Sleep Status Register */ -#define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */ -#define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */ -#define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR 0x40F0001C /* Power Manager General Configuration Register */ -#define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR 0x40F00030 /* Reset Controller Status Register */ - -#define PSLR 0x40F00034 /* Power Manager Sleep Config Register */ -#define PSTR 0x40F00038 /* Power Manager Standby Config Register */ -#define PSNR 0x40F0003C /* Power Manager Sense Config Register */ -#define PVCR 0x40F00040 /* Power Manager VoltageControl Register */ -#define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */ -#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */ -#define PCMD(x) (0x40F00080 + x*4) -#define PCMD0 (0x40F00080 + 0 * 4) -#define PCMD1 (0x40F00080 + 1 * 4) -#define PCMD2 (0x40F00080 + 2 * 4) -#define PCMD3 (0x40F00080 + 3 * 4) -#define PCMD4 (0x40F00080 + 4 * 4) -#define PCMD5 (0x40F00080 + 5 * 4) -#define PCMD6 (0x40F00080 + 6 * 4) -#define PCMD7 (0x40F00080 + 7 * 4) -#define PCMD8 (0x40F00080 + 8 * 4) -#define PCMD9 (0x40F00080 + 9 * 4) -#define PCMD10 (0x40F00080 + 10 * 4) -#define PCMD11 (0x40F00080 + 11 * 4) -#define PCMD12 (0x40F00080 + 12 * 4) -#define PCMD13 (0x40F00080 + 13 * 4) -#define PCMD14 (0x40F00080 + 14 * 4) -#define PCMD15 (0x40F00080 + 15 * 4) -#define PCMD16 (0x40F00080 + 16 * 4) -#define PCMD17 (0x40F00080 + 17 * 4) -#define PCMD18 (0x40F00080 + 18 * 4) -#define PCMD19 (0x40F00080 + 19 * 4) -#define PCMD20 (0x40F00080 + 20 * 4) -#define PCMD21 (0x40F00080 + 21 * 4) -#define PCMD22 (0x40F00080 + 22 * 4) -#define PCMD23 (0x40F00080 + 23 * 4) -#define PCMD24 (0x40F00080 + 24 * 4) -#define PCMD25 (0x40F00080 + 25 * 4) -#define PCMD26 (0x40F00080 + 26 * 4) -#define PCMD27 (0x40F00080 + 27 * 4) -#define PCMD28 (0x40F00080 + 28 * 4) -#define PCMD29 (0x40F00080 + 29 * 4) -#define PCMD30 (0x40F00080 + 30 * 4) -#define PCMD31 (0x40F00080 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -/* FIXME: PCMD_SQC need be checked. */ -#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */ - /* bit 9 should be 0 all day. */ -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -/* define MACRO for Power Manager General Configuration Register (PCFR) */ -#define PCFR_FVC (0x1 << 10) -#define PCFR_PI2C_EN (0x1 << 6) - -#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ - -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ - -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * SSP Serial Port Registers - */ -#define SSCR0 0x41000000 /* SSP Control Register 0 */ -#define SSCR1 0x41000004 /* SSP Control Register 1 */ -#define SSSR 0x41000008 /* SSP Status Register */ -#define SSITR 0x4100000C /* SSP Interrupt Test Register */ -#define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ - -/* - * MultiMediaCard (MMC) controller - */ -#define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */ -#define MMC_STAT 0x41100004 /* MMC Status Register (read only) */ -#define MMC_CLKRT 0x41100008 /* MMC clock rate */ -#define MMC_SPI 0x4110000c /* SPI mode control bits */ -#define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */ -#define MMC_RESTO 0x41100014 /* Expected response time out */ -#define MMC_RDTO 0x41100018 /* Expected data read time out */ -#define MMC_BLKLEN 0x4110001c /* Block length of data transaction */ -#define MMC_NOB 0x41100020 /* Number of blocks, for block mode */ -#define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK 0x41100028 /* Interrupt Mask */ -#define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */ -#define MMC_CMD 0x41100030 /* Index of current command */ -#define MMC_ARGH 0x41100034 /* MSW part of the current command argument */ -#define MMC_ARGL 0x41100038 /* LSW part of the current command argument */ -#define MMC_RES 0x4110003c /* Response FIFO (read only) */ -#define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */ -#define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */ - - -/* - * LCD - */ -#define LCCR0 0x44000000 /* LCD Controller Control Register 0 */ -#define LCCR1 0x44000004 /* LCD Controller Control Register 1 */ -#define LCCR2 0x44000008 /* LCD Controller Control Register 2 */ -#define LCCR3 0x4400000C /* LCD Controller Control Register 3 */ -#define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ -#define LCSR0 0x44000038 /* LCD Controller Status Register */ -#define LCSR1 0x44000034 /* LCD Controller Status Register */ -#define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */ -#define TMEDCR 0x44000044 /* TMED Control Register */ - -#define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */ -#define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */ - -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ -#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ -#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ -#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ -#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ -#define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_CPU_PXA27X) -#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ -#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ -#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ -#endif - -#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ - (((Pixel) - 1) << FShft (LCCR1_PPL)) - -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [1..64 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_HSW)) - -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) - -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) - -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) - -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) - -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ -#define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ -#define LCCR3_OEP (1 << 23) /* output enable polarity */ -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ - -#define LCCR3_PDFOR_0 (0 << 30) -#define LCCR3_PDFOR_1 (1 << 30) -#define LCCR3_PDFOR_2 (2 << 30) -#define LCCR3_PDFOR_3 (3 << 30) - - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ - (((Div) << FShft (LCCR3_PCD))) - - -#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ -#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ - ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26))) - -#define LCCR3_ACB Fld (8, 8) /* AC Bias */ -#define LCCR3_Acb(Acb) /* BAC Bias */ \ - (((Acb) << FShft (LCCR3_ACB))) - -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ - -#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR0_SOF (1 << 1) /* Start of frame */ -#define LCSR0_BER (1 << 2) /* Bus error */ -#define LCSR0_ABC (1 << 3) /* AC Bias count */ -#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR0_OU (1 << 6) /* output FIFO underrun */ -#define LCSR0_QD (1 << 7) /* quick disable */ -#define LCSR0_EOF0 (1 << 8) /* end of frame */ -#define LCSR0_BS (1 << 9) /* branch status */ -#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ - -#define LCSR1_SOF1 (1 << 0) -#define LCSR1_SOF2 (1 << 1) -#define LCSR1_SOF3 (1 << 2) -#define LCSR1_SOF4 (1 << 3) -#define LCSR1_SOF5 (1 << 4) -#define LCSR1_SOF6 (1 << 5) - -#define LCSR1_EOF1 (1 << 8) -#define LCSR1_EOF2 (1 << 9) -#define LCSR1_EOF3 (1 << 10) -#define LCSR1_EOF4 (1 << 11) -#define LCSR1_EOF5 (1 << 12) -#define LCSR1_EOF6 (1 << 13) - -#define LCSR1_BS1 (1 << 16) -#define LCSR1_BS2 (1 << 17) -#define LCSR1_BS3 (1 << 18) -#define LCSR1_BS4 (1 << 19) -#define LCSR1_BS5 (1 << 20) -#define LCSR1_BS6 (1 << 21) - -#define LCSR1_IU2 (1 << 25) -#define LCSR1_IU3 (1 << 26) -#define LCSR1_IU4 (1 << 27) -#define LCSR1_IU5 (1 << 28) -#define LCSR1_IU6 (1 << 29) - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_CPU_PXA27X) -#define LDCMD_SOFINT (1 << 22) -#define LDCMD_EOFINT (1 << 21) -#endif - -/* - * Memory controller - */ - -#ifdef CONFIG_CPU_MONAHANS - -/* PXA3xx */ - -/* Static Memory Controller Registers */ -#define MSC0 0x4A000008 /* Static Memory Control Register 0 */ -#define MSC1 0x4A00000C /* Static Memory Control Register 1 */ -#define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */ -#define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */ -#define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */ -#define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */ -#define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */ -#define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */ -#define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */ -#define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */ -#define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */ -#define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */ -#define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */ - -/* Dynamic Memory Controller Registers */ -#define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */ -#define MDREFR 0x48100004 /* SDRAM Refresh Control Register */ -#define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */ -#define MDMRS 0x48100040 /* MRS value to be written to SDRAM */ -#define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */ -#define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */ -#define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */ -#define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */ -#define EMPI 0x48100090 /* EMPI Control Register */ -#define RCOMP 0x48100100 -#define PAD_MA 0x48100110 -#define PAD_MDMSB 0x48100114 -#define PAD_MDLSB 0x48100118 -#define PAD_DMEM 0x4810011c -#define PAD_SDCLK 0x48100120 -#define PAD_SDCS 0x48100124 -#define PAD_SMEM 0x48100128 -#define PAD_SCLK 0x4810012C -#define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */ - -/* Some frequently used bits */ -#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ -#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */ -#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */ -#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */ - -#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */ -#define MDCNFG_DTC_1 0x100 -#define MDCNFG_DTC_2 0x200 -#define MDCNFG_DTC_3 0x300 - -#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */ -#define MDCNFG_DRAC_13 0x20 -#define MDCNFG_DRAC_14 0x40 - -#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */ -#define MDCNFG_DCAC_10 0x08 -#define MDCNFG_DCAC_11 0x10 - -#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */ -#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */ -#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */ - - -/* Data Flash Controller Registers */ - -#define NDCR 0x43100000 /* Data Flash Control register */ -#define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ -/* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ -#define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ -/* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ -#define NDSR 0x43100014 /* Data Controller Status Register */ -#define NDPCR 0x43100018 /* Data Controller Page Count Register */ -#define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */ -#define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */ -#define NDDB 0x43100040 /* Data Controller Data Buffer */ -#define NDCB0 0x43100048 /* Data Controller Command Buffer0 */ -#define NDCB1 0x4310004C /* Data Controller Command Buffer1 */ -#define NDCB2 0x43100050 /* Data Controller Command Buffer2 */ - -#define NDCR_SPARE_EN (0x1<<31) -#define NDCR_ECC_EN (0x1<<30) -#define NDCR_DMA_EN (0x1<<29) -#define NDCR_ND_RUN (0x1<<28) -#define NDCR_DWIDTH_C (0x1<<27) -#define NDCR_DWIDTH_M (0x1<<26) -#define NDCR_PAGE_SZ (0x3<<24) -#define NDCR_NCSX (0x1<<23) -#define NDCR_ND_STOP (0x1<<22) -/* reserved: - * #define NDCR_ND_MODE (0x3<<21) - * #define NDCR_NAND_MODE 0x0 */ -#define NDCR_CLR_PG_CNT (0x1<<20) -#define NDCR_CLR_ECC (0x1<<19) -#define NDCR_RD_ID_CNT (0x7<<16) -#define NDCR_RA_START (0x1<<15) -#define NDCR_PG_PER_BLK (0x1<<14) -#define NDCR_ND_ARB_EN (0x1<<12) -#define NDCR_RDYM (0x1<<11) -#define NDCR_CS0_PAGEDM (0x1<<10) -#define NDCR_CS1_PAGEDM (0x1<<9) -#define NDCR_CS0_CMDDM (0x1<<8) -#define NDCR_CS1_CMDDM (0x1<<7) -#define NDCR_CS0_BBDM (0x1<<6) -#define NDCR_CS1_BBDM (0x1<<5) -#define NDCR_DBERRM (0x1<<4) -#define NDCR_SBERRM (0x1<<3) -#define NDCR_WRDREQM (0x1<<2) -#define NDCR_RDDREQM (0x1<<1) -#define NDCR_WRCMDREQM (0x1) - -#define NDSR_RDY (0x1<<11) -#define NDSR_CS0_PAGED (0x1<<10) -#define NDSR_CS1_PAGED (0x1<<9) -#define NDSR_CS0_CMDD (0x1<<8) -#define NDSR_CS1_CMDD (0x1<<7) -#define NDSR_CS0_BBD (0x1<<6) -#define NDSR_CS1_BBD (0x1<<5) -#define NDSR_DBERR (0x1<<4) -#define NDSR_SBERR (0x1<<3) -#define NDSR_WRDREQ (0x1<<2) -#define NDSR_RDDREQ (0x1<<1) -#define NDSR_WRCMDREQ (0x1) - -#define NDCB0_AUTO_RS (0x1<<25) -#define NDCB0_CSEL (0x1<<24) -#define NDCB0_CMD_TYPE (0x7<<21) -#define NDCB0_NC (0x1<<20) -#define NDCB0_DBC (0x1<<19) -#define NDCB0_ADDR_CYC (0x7<<16) -#define NDCB0_CMD2 (0xff<<8) -#define NDCB0_CMD1 (0xff) -#define MCMEM(s) MCMEM0 -#define MCATT(s) MCATT0 -#define MCIO(s) MCIO0 -#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ - -/* Maximum values for NAND Interface Timing Registers in DFC clock - * periods */ -#define DFC_MAX_tCH 7 -#define DFC_MAX_tCS 7 -#define DFC_MAX_tWH 7 -#define DFC_MAX_tWP 7 -#define DFC_MAX_tRH 7 -#define DFC_MAX_tRP 15 -#define DFC_MAX_tR 65535 -#define DFC_MAX_tWHR 15 -#define DFC_MAX_tAR 15 - -#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */ -#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */ - -#else /* CONFIG_CPU_MONAHANS */ - -/* PXA2xx */ - -#define MEMC_BASE 0x48000000 /* Base of Memory Controller */ -#define MDCNFG_OFFSET 0x0 -#define MDREFR_OFFSET 0x4 -#define MSC0_OFFSET 0x8 -#define MSC1_OFFSET 0xC -#define MSC2_OFFSET 0x10 -#define MECR_OFFSET 0x14 -#define SXLCR_OFFSET 0x18 -#define SXCNFG_OFFSET 0x1C -#define FLYCNFG_OFFSET 0x20 -#define SXMRS_OFFSET 0x24 -#define MCMEM0_OFFSET 0x28 -#define MCMEM1_OFFSET 0x2C -#define MCATT0_OFFSET 0x30 -#define MCATT1_OFFSET 0x34 -#define MCIO0_OFFSET 0x38 -#define MCIO1_OFFSET 0x3C -#define MDMRS_OFFSET 0x40 - -#define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */ -#define MDCNFG_DE0 0x00000001 -#define MDCNFG_DE1 0x00000002 -#define MDCNFG_DE2 0x00010000 -#define MDCNFG_DE3 0x00020000 -#define MDCNFG_DWID0 0x00000004 - -#define MDREFR 0x48000004 /* SDRAM Refresh Control Register */ -#define MSC0 0x48000008 /* Static Memory Control Register 0 */ -#define MSC1 0x4800000C /* Static Memory Control Register 1 */ -#define MSC2 0x48000010 /* Static Memory Control Register 2 */ -#define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */ -#define FLYCNFG 0x48000020 -#define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS 0x48000040 /* MRS value to be written to SDRAM */ -#define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ -#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -#if defined(CONFIG_CPU_PXA27X) - -#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ - -#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ -#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ -#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ -#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ -#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ -#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ -#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ -#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ -#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ - -#endif /* CONFIG_CPU_PXA27X */ - -/* LCD registers */ -#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ -#define LCCR5 0x44000014 /* LCD Controller Control Register 5 */ -#define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ -#define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ -#define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */ -#define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */ -#define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */ -#define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */ -#define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */ -#define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */ -#define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */ -#define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */ -#define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */ -#define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */ -#define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */ -#define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */ -#define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */ -#define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */ -#define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */ -#define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */ -#define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */ -#define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */ -#define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */ - -#define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */ -#define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */ -#define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */ -#define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */ -#define CCR 0x44000090 /* Cursor Control Register */ - -#define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ -#define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */ - -#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ -#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ - -#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */ -#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */ - -#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */ -#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */ - -#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */ -#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */ -#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */ -#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */ -#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */ -#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */ - -#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ -#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */ -#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */ - -#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */ -#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */ -#define CCR_CEN (1<<31) /* Enable bit for Cursor */ - -/* Keypad controller */ - -#define KPC 0x41500000 /* Keypad Interface Control register */ -#define KPDK 0x41500008 /* Keypad Interface Direct Key register */ -#define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */ -#define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */ -#define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */ -#define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ -#define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ -#define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ -#define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ -#define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */ - -#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ -#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ -#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ -#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ -#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ -#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ -#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ -#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ -#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ -#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ -#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ -#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ -#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ -#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ -#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */ -#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ -#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */ -#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ -#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ - -#define KPDK_DKP (0x1 << 31) -#define KPDK_DK7 (0x1 << 7) -#define KPDK_DK6 (0x1 << 6) -#define KPDK_DK5 (0x1 << 5) -#define KPDK_DK4 (0x1 << 4) -#define KPDK_DK3 (0x1 << 3) -#define KPDK_DK2 (0x1 << 2) -#define KPDK_DK1 (0x1 << 1) -#define KPDK_DK0 (0x1 << 0) - -#define KPREC_OF1 (0x1 << 31) -#define kPREC_UF1 (0x1 << 30) -#define KPREC_OF0 (0x1 << 15) -#define KPREC_UF0 (0x1 << 14) - -#define KPMK_MKP (0x1 << 31) -#define KPAS_SO (0x1 << 31) -#define KPASMKPx_SO (0x1 << 31) - -#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ -#define PSLR 0x40F00034 -#define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */ -#define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */ -#define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */ -#define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */ -#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */ -#define OSMR4 0x40A00080 /* */ -#define OSCR4 0x40A00040 /* OS Timer Counter Register */ -#define OMCR4 0x40A000C0 /* */ - -#endif /* CONFIG_CPU_PXA27X */ - -#endif /* _PXA_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h deleted file mode 100644 index 428a848e15..0000000000 --- a/arch/arm/include/asm/arch-pxa/pxa.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA common functions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __PXA_H__ -#define __PXA_H__ - -#define PXA255_A0 0x00000106 -#define PXA250_C0 0x00000105 -#define PXA250_B2 0x00000104 -#define PXA250_B1 0x00000103 -#define PXA250_B0 0x00000102 -#define PXA250_A1 0x00000101 -#define PXA250_A0 0x00000100 -#define PXA210_C0 0x00000125 -#define PXA210_B2 0x00000124 -#define PXA210_B1 0x00000123 -#define PXA210_B0 0x00000122 - -int cpu_is_pxa25x(void); -int cpu_is_pxa27x(void); -uint32_t pxa_get_cpu_revision(void); -void pxa2xx_dram_init(void); - -#endif /* __PXA_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-mmc.h b/arch/arm/include/asm/arch-pxa/regs-mmc.h deleted file mode 100644 index 6d9a736d9c..0000000000 --- a/arch/arm/include/asm/arch-pxa/regs-mmc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __REGS_MMC_H__ -#define __REGS_MMC_H__ - -#define MMC0_BASE 0x41100000 -#define MMC1_BASE 0x42000000 - -int pxa_mmc_register(int card_index); - -struct pxa_mmc_regs { - uint32_t strpcl; - uint32_t stat; - uint32_t clkrt; - uint32_t spi; - uint32_t cmdat; - uint32_t resto; - uint32_t rdto; - uint32_t blklen; - uint32_t nob; - uint32_t prtbuf; - uint32_t i_mask; - uint32_t i_reg; - uint32_t cmd; - uint32_t argh; - uint32_t argl; - uint32_t res; - uint32_t rxfifo; - uint32_t txfifo; -}; - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (1 << 0) -#define MMC_STRPCL_START_CLK (1 << 1) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (1 << 13) -#define MMC_STAT_PRG_DONE (1 << 12) -#define MMC_STAT_DATA_TRAN_DONE (1 << 11) -#define MMC_STAT_CLK_EN (1 << 8) -#define MMC_STAT_RECV_FIFO_FULL (1 << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) -#define MMC_STAT_RES_CRC_ERROR (1 << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) -#define MMC_STAT_CRC_READ_ERROR (1 << 3) -#define MMC_STAT_CRC_WRITE_ERROR (1 << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) -#define MMC_STAT_READ_TIME_OUT (1 << 0) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ 0 -#define MMC_CLKRT_10MHZ 1 -#define MMC_CLKRT_5MHZ 2 -#define MMC_CLKRT_2_5MHZ 3 -#define MMC_CLKRT_1_25MHZ 4 -#define MMC_CLKRT_0_625MHZ 5 -#define MMC_CLKRT_0_3125MHZ 6 - -/* MMC_SPI */ -#define MMC_SPI_EN (1 << 0) -#define MMC_SPI_CS_EN (1 << 2) -#define MMC_SPI_CS_ADDRESS (1 << 3) -#define MMC_SPI_CRC_ON (1 << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (1 << 8) -#define MMC_CMDAT_MMC_DMA_EN (1 << 7) -#define MMC_CMDAT_INIT (1 << 6) -#define MMC_CMDAT_BUSY (1 << 5) -#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) -#define MMC_CMDAT_STREAM (1 << 4) -#define MMC_CMDAT_WRITE (1 << 3) -#define MMC_CMDAT_DATA_EN (1 << 2) -#define MMC_CMDAT_R0 0 -#define MMC_CMDAT_R1 1 -#define MMC_CMDAT_R2 2 -#define MMC_CMDAT_R3 3 - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX_MASK 0x7f - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX_MASK 0xffff - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX_MASK 0x3ff - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (1 << 0) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_MASK_CLK_IS_OFF (1 << 4) -#define MMC_I_MASK_STOP_CMD (1 << 3) -#define MMC_I_MASK_END_CMD_RES (1 << 2) -#define MMC_I_MASK_PRG_DONE (1 << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) -#define MMC_I_MASK_ALL 0x7f - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_REG_CLK_IS_OFF (1 << 4) -#define MMC_I_REG_STOP_CMD (1 << 3) -#define MMC_I_REG_END_CMD_RES (1 << 2) -#define MMC_I_REG_PRG_DONE (1 << 1) -#define MMC_I_REG_DATA_TRAN_DONE (1 << 0) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX 0x6f - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -#endif /* __REGS_MMC_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h deleted file mode 100644 index bdd0a4757b..0000000000 --- a/arch/arm/include/asm/arch-pxa/regs-uart.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __REGS_UART_H__ -#define __REGS_UART_H__ - -#define FFUART_BASE 0x40100000 -#define BTUART_BASE 0x40200000 -#define STUART_BASE 0x40700000 -#define HWUART_BASE 0x41600000 - -struct pxa_uart_regs { - union { - uint32_t thr; - uint32_t rbr; - uint32_t dll; - }; - union { - uint32_t ier; - uint32_t dlh; - }; - union { - uint32_t fcr; - uint32_t iir; - }; - uint32_t lcr; - uint32_t mcr; - uint32_t lsr; - uint32_t msr; - uint32_t spr; - uint32_t isr; -}; - -#define IER_DMAE (1 << 7) -#define IER_UUE (1 << 6) -#define IER_NRZE (1 << 5) -#define IER_RTIOE (1 << 4) -#define IER_MIE (1 << 3) -#define IER_RLSE (1 << 2) -#define IER_TIE (1 << 1) -#define IER_RAVIE (1 << 0) - -#define IIR_FIFOES1 (1 << 7) -#define IIR_FIFOES0 (1 << 6) -#define IIR_TOD (1 << 3) -#define IIR_IID2 (1 << 2) -#define IIR_IID1 (1 << 1) -#define IIR_IP (1 << 0) - -#define FCR_ITL2 (1 << 7) -#define FCR_ITL1 (1 << 6) -#define FCR_RESETTF (1 << 2) -#define FCR_RESETRF (1 << 1) -#define FCR_TRFIFOE (1 << 0) -#define FCR_ITL_1 0 -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) -#define LCR_SB (1 << 6) -#define LCR_STKYP (1 << 5) -#define LCR_EPS (1 << 4) -#define LCR_PEN (1 << 3) -#define LCR_STB (1 << 2) -#define LCR_WLS1 (1 << 1) -#define LCR_WLS0 (1 << 0) - -#define LSR_FIFOE (1 << 7) -#define LSR_TEMT (1 << 6) -#define LSR_TDRQ (1 << 5) -#define LSR_BI (1 << 4) -#define LSR_FE (1 << 3) -#define LSR_PE (1 << 2) -#define LSR_OE (1 << 1) -#define LSR_DR (1 << 0) - -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) -#define MCR_OUT1 (1 << 2) -#define MCR_RTS (1 << 1) -#define MCR_DTR (1 << 0) - -#define MSR_DCD (1 << 7) -#define MSR_RI (1 << 6) -#define MSR_DSR (1 << 5) -#define MSR_CTS (1 << 4) -#define MSR_DDCD (1 << 3) -#define MSR_TERI (1 << 2) -#define MSR_DDSR (1 << 1) -#define MSR_DCTS (1 << 0) - -#endif /* __REGS_UART_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-usb.h b/arch/arm/include/asm/arch-pxa/regs-usb.h deleted file mode 100644 index e46887c9ed..0000000000 --- a/arch/arm/include/asm/arch-pxa/regs-usb.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA25x UDC definitions - * - * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com> - */ - -#ifndef __REGS_USB_H__ -#define __REGS_USB_H__ - -struct pxa25x_udc_regs { - /* UDC Control Register */ - uint32_t udccr; /* 0x000 */ - uint32_t reserved1; - - /* UDC Control Function Register */ - uint32_t udccfr; /* 0x008 */ - uint32_t reserved2; - - /* UDC Endpoint Control/Status Registers */ - uint32_t udccs[16]; /* 0x010 - 0x04c */ - - /* UDC Interrupt Control/Status Registers */ - uint32_t uicr0; /* 0x050 */ - uint32_t uicr1; /* 0x054 */ - uint32_t usir0; /* 0x058 */ - uint32_t usir1; /* 0x05c */ - - /* UDC Frame Number/Byte Count Registers */ - uint32_t ufnrh; /* 0x060 */ - uint32_t ufnrl; /* 0x064 */ - uint32_t ubcr2; /* 0x068 */ - uint32_t ubcr4; /* 0x06c */ - uint32_t ubcr7; /* 0x070 */ - uint32_t ubcr9; /* 0x074 */ - uint32_t ubcr12; /* 0x078 */ - uint32_t ubcr14; /* 0x07c */ - - /* UDC Endpoint Data Registers */ - uint32_t uddr0; /* 0x080 */ - uint32_t reserved3[7]; - uint32_t uddr5; /* 0x0a0 */ - uint32_t reserved4[7]; - uint32_t uddr10; /* 0x0c0 */ - uint32_t reserved5[7]; - uint32_t uddr15; /* 0x0e0 */ - uint32_t reserved6[7]; - uint32_t uddr1; /* 0x100 */ - uint32_t reserved7[31]; - uint32_t uddr2; /* 0x180 */ - uint32_t reserved8[31]; - uint32_t uddr3; /* 0x200 */ - uint32_t reserved9[127]; - uint32_t uddr4; /* 0x400 */ - uint32_t reserved10[127]; - uint32_t uddr6; /* 0x600 */ - uint32_t reserved11[31]; - uint32_t uddr7; /* 0x680 */ - uint32_t reserved12[31]; - uint32_t uddr8; /* 0x700 */ - uint32_t reserved13[127]; - uint32_t uddr9; /* 0x900 */ - uint32_t reserved14[127]; - uint32_t uddr11; /* 0xb00 */ - uint32_t reserved15[31]; - uint32_t uddr12; /* 0xb80 */ - uint32_t reserved16[31]; - uint32_t uddr13; /* 0xc00 */ - uint32_t reserved17[127]; - uint32_t uddr14; /* 0xe00 */ - -}; - -#define PXA25X_UDC_BASE 0x40600000 - -#define UDCCR_UDE (1 << 0) -#define UDCCR_UDA (1 << 1) -#define UDCCR_RSM (1 << 2) -#define UDCCR_RESIR (1 << 3) -#define UDCCR_SUSIR (1 << 4) -#define UDCCR_SRM (1 << 5) -#define UDCCR_RSTIR (1 << 6) -#define UDCCR_REM (1 << 7) - -/* Bulk IN endpoint 1/6/11 */ -#define UDCCS_BI_TSP (1 << 7) -#define UDCCS_BI_FST (1 << 5) -#define UDCCS_BI_SST (1 << 4) -#define UDCCS_BI_TUR (1 << 3) -#define UDCCS_BI_FTF (1 << 2) -#define UDCCS_BI_TPC (1 << 1) -#define UDCCS_BI_TFS (1 << 0) - -/* Bulk OUT endpoint 2/7/12 */ -#define UDCCS_BO_RSP (1 << 7) -#define UDCCS_BO_RNE (1 << 6) -#define UDCCS_BO_FST (1 << 5) -#define UDCCS_BO_SST (1 << 4) -#define UDCCS_BO_DME (1 << 3) -#define UDCCS_BO_RPC (1 << 1) -#define UDCCS_BO_RFS (1 << 0) - -/* Isochronous OUT endpoint 4/9/14 */ -#define UDCCS_IO_RSP (1 << 7) -#define UDCCS_IO_RNE (1 << 6) -#define UDCCS_IO_DME (1 << 3) -#define UDCCS_IO_ROF (1 << 2) -#define UDCCS_IO_RPC (1 << 1) -#define UDCCS_IO_RFS (1 << 0) - -/* Control endpoint 0 */ -#define UDCCS0_OPR (1 << 0) -#define UDCCS0_IPR (1 << 1) -#define UDCCS0_FTF (1 << 2) -#define UDCCS0_DRWF (1 << 3) -#define UDCCS0_SST (1 << 4) -#define UDCCS0_FST (1 << 5) -#define UDCCS0_RNE (1 << 6) -#define UDCCS0_SA (1 << 7) - -#define UICR0_IM0 (1 << 0) - -#define USIR0_IR0 (1 << 0) -#define USIR0_IR1 (1 << 1) -#define USIR0_IR2 (1 << 2) -#define USIR0_IR3 (1 << 3) -#define USIR0_IR4 (1 << 4) -#define USIR0_IR5 (1 << 5) -#define USIR0_IR6 (1 << 6) -#define USIR0_IR7 (1 << 7) - -#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ -#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ -/* - * Intel(R) PXA255 Processor Specification, September 2003 (page 31) - * define new "must be one" bits in UDCCFR (see Table 12-13.) - */ -#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) - -#define UFNRH_SIR (1 << 7) /* SOF interrupt request */ -#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ -#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ -#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ -#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ - -#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 26f1877791..5870412c43 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -6,11 +6,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #if defined(CONFIG_ARCH_LS1021A) || \ - defined(CONFIG_CPU_PXA27X) || \ - defined(CONFIG_CPU_MONAHANS) || \ defined(CONFIG_FSL_LAYERSCAPE) #include <asm/arch/config.h> #endif diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b0c7599e41..a4f4961fc8 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,31 +8,6 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_CHAIN_OF_TRUST -#define CONFIG_FSL_SEC_MON - -#ifdef CONFIG_SPL_BUILD -/* - * Define the key hash for U-Boot here if public/private key pair used to - * sign U-boot are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_SPL_UBOOT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - * else leave it defined as NULL - */ - -#define CONFIG_SPL_UBOOT_KEY_HASH NULL -#endif /* ifdef CONFIG_SPL_BUILD */ - -#define CONFIG_KEY_REVOCATION - -#if defined(CONFIG_FSL_LAYERSCAPE) -/* - * For fsl layerscape based platforms, ESBC image Address in Header - * is 64 bit. - */ -#define CONFIG_ESBC_ADDR_64BIT -#endif - #ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images @@ -49,76 +24,6 @@ #endif -#ifdef CONFIG_ARCH_LS2080A -#define CONFIG_EXTRA_ENV \ - "setenv fdt_high 0xa0000000;" \ - "setenv initrd_high 0xcfffffff;" \ - "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -#else -#define CONFIG_EXTRA_ENV \ - "setenv fdt_high 0xffffffff;" \ - "setenv initrd_high 0xffffffff;" \ - "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" -#endif - -/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from - * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ - defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) -#define CONFIG_BOOTSCRIPT_COPY_RAM -#endif -/* The address needs to be modified according to NOR, NAND, SD and - * DDR memory map - */ -#ifdef CONFIG_FSL_LSCH3 -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_BS_ADDR_DEVICE 0x20600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000 -#else /* NOR BOOT */ -#define CONFIG_BS_ADDR_DEVICE 0x580600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000 -#endif /*ifdef CONFIG_QSPI_BOOT */ -#define CONFIG_BS_SIZE 0x00001000 -#define CONFIG_BS_HDR_SIZE 0x00004000 -#define CONFIG_BS_ADDR_RAM 0xa0600000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000 -#else -#ifdef CONFIG_SD_BOOT -/* For SD boot address and size are assigned in terms of sector - * offset and no. of sectors respectively. - */ -#define CONFIG_BS_ADDR_DEVICE 0x00003000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200 -#define CONFIG_BS_SIZE 0x00000008 -#define CONFIG_BS_HDR_SIZE 0x00000010 -#elif defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_ADDR_DEVICE 0x00600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000 -#define CONFIG_BS_SIZE 0x00001000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_BS_ADDR_DEVICE 0x40600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000 -#define CONFIG_BS_SIZE 0x00001000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#else /* Default NOR Boot */ -#define CONFIG_BS_ADDR_DEVICE 0x60600000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000 -#define CONFIG_BS_SIZE 0x00001000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#endif -#define CONFIG_BS_ADDR_RAM 0x81000000 -#define CONFIG_BS_HDR_ADDR_RAM 0x81020000 -#endif - -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#else -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE -/* BOOTSCRIPT_ADDR is not required */ -#endif - #ifdef CONFIG_FSL_LS_PPA /* Define the key hash here if SRK used for signing PPA image is * different from SRK hash put in SFP used for U-Boot. @@ -129,7 +34,6 @@ #define PPA_KEY_HASH NULL #endif /* ifdef CONFIG_FSL_LS_PPA */ -#include <config_fsl_chain_trust.h> #endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index b5790bd0bc..0ece4b0906 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -6,9 +6,8 @@ #ifndef _ASM_SPL_H_ #define _ASM_SPL_H_ -#if defined(CONFIG_ARCH_OMAP2PLUS) \ - || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ - || defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) || \ + defined(CONFIG_ARCH_K3) || defined(CONFIG_ARCH_OMAP2PLUS) /* Platform-specific defines */ #include <asm/arch/spl.h> diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds index 22b4e16d35..37f0ccd922 100644 --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -40,8 +40,8 @@ SECTIONS } > .nor . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); } > .nor . = ALIGN(4); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index b87639f8c0..11bfd5afe7 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -327,6 +327,13 @@ config AT91_EFLASH Enable the driver for the embedded flash used in the Atmel AT91SAM9XE devices. +config EFLASH_PROTSECTORS + int "Number of flash sectors to protect from erasing" + depends on AT91_EFLASH + help + If non-zero, this will be the number of sectors of the flash to disallow + U-Boot to ease, starting from the beginning of flash. + config AT91_GPIO_PULLUP bool "Keep pullups on peripheral pins" depends on CPU_ARM926EJS @@ -370,8 +377,4 @@ source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS - default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7A - endif diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c index 23c24936ed..043f06a827 100644 --- a/arch/arm/mach-at91/arm926ejs/eflash.c +++ b/arch/arm/mach-at91/arm926ejs/eflash.c @@ -120,7 +120,7 @@ unsigned long flash_init(void) if (i%32 == 0) tmp = readl(&eefc->frr); flash_info[0].protect[i] = (tmp >> (i%32)) & 1; -#if defined(CONFIG_EFLASH_PROTSECTORS) +#if CONFIG_VAL(EFLASH_PROTSECTORS) if (i < CONFIG_EFLASH_PROTSECTORS) flash_info[0].protect[i] = 1; #endif @@ -158,7 +158,7 @@ int flash_real_protect (flash_info_t *info, long sector, int prot) debug("protect sector=%ld prot=%d\n", sector, prot); -#if defined(CONFIG_EFLASH_PROTSECTORS) +#if CONFIG_VAL(EFLASH_PROTSECTORS) if (sector < CONFIG_EFLASH_PROTSECTORS) { if (!prot) { printf("eflash: sector %lu cannot be unprotected\n", diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h index c3bd9140df..b712be8051 100644 --- a/arch/arm/mach-at91/include/mach/atmel_pio4.h +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h @@ -74,6 +74,7 @@ struct atmel_pio4_port { #define AT91_PIO_PORTB 0x1 #define AT91_PIO_PORTC 0x2 #define AT91_PIO_PORTD 0x3 +#define AT91_PIO_PORTE 0x4 int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config); int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config); diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 6eca8db6d5..25c5db4991 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -134,7 +134,4 @@ endif source "board/davinci/da8xxevm/Kconfig" source "board/lego/ev3/Kconfig" -config SPL_LDSCRIPT - default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds" - endif diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f73dbbb507..8410290856 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -54,11 +54,15 @@ endchoice if ARCH_EXYNOS4 +config EXYNOS4210 + bool + choice prompt "EXYNOS4 board select" config TARGET_SMDKV310 bool "Exynos4210 SMDKV310 board" + select EXYNOS4210 select OF_CONTROL select SUPPORT_SPL @@ -70,6 +74,7 @@ config TARGET_S5PC210_UNIVERSAL config TARGET_ORIGEN bool "Exynos4412 Origen board" + select EXYNOS4210 select SUPPORT_SPL config TARGET_TRATS2 @@ -83,6 +88,15 @@ endif if ARCH_EXYNOS5 +config EXYNOS5250 + bool + +config EXYNOS5420 + bool + +config EXYNOS5_DT + bool + config SPL_GPIO default y @@ -97,6 +111,8 @@ choice config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL config TARGET_ARNDALE @@ -105,36 +121,49 @@ config TARGET_ARNDALE select ARM_ERRATA_774769 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SMDK5250 bool "SMDK5250 board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SNOW bool "Snow board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SPRING bool "Spring board" + select EXYNOS5_DT + select EXYNOS5250 select OF_CONTROL select SUPPORT_SPL config TARGET_SMDK5420 bool "SMDK5420 board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL config TARGET_PEACH_PI bool "Peach Pi board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL config TARGET_PEACH_PIT bool "Peach Pit board" + select EXYNOS5_DT + select EXYNOS5420 select OF_CONTROL select SUPPORT_SPL @@ -189,6 +218,16 @@ endif config SYS_SOC default "exynos" +config EXYNOS_ACE_SHA + bool "Advanced Crypto Engine SHA support" + depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && (LIB_HW_RAND || SHA_HW_ACCEL) + default y if ARCH_EXYNOS5 + +config EXYNOS_TMU + bool "Exynos5 thermal management unit support" + depends on ARCH_EXYNOS5 + default y + source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" @@ -201,7 +240,4 @@ source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" source "board/samsung/axy17lte/Kconfig" -config SPL_LDSCRIPT - default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 - endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index e895c13157..dd097cf541 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -10,8 +10,8 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o obj-$(CONFIG_EXYNOS5420) += sec_boot.o ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o -obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o +obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o +obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o obj-y += spl_boot.o tzpc.o obj-y += lowlevel_init.o diff --git a/arch/arm/mach-exynos/dmc_init_exynos4.c b/arch/arm/mach-exynos/dmc_init_exynos4.c index ecddc72684..58a3c82f68 100644 --- a/arch/arm/mach-exynos/dmc_init_exynos4.c +++ b/arch/arm/mach-exynos/dmc_init_exynos4.c @@ -175,7 +175,7 @@ void mem_ctrl_init(int reset) * 0: full_sync */ writel(1, ASYNC_CONFIG); -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE + APB_SFR_INTERLEAVE_CONF_OFFSET); diff --git a/arch/arm/mach-exynos/exynos4_setup.h b/arch/arm/mach-exynos/exynos4_setup.h index a08d64a8e2..fbb45eb897 100644 --- a/arch/arm/mach-exynos/exynos4_setup.h +++ b/arch/arm/mach-exynos/exynos4_setup.h @@ -420,7 +420,7 @@ struct mem_timings { #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830 -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ #define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507 #define APB_SFR_ARBRITATION_CONF_VAL 0x00000001 @@ -542,7 +542,7 @@ struct mem_timings { #define CONTROL2_VAL 0x00000000 -#ifdef CONFIG_ORIGEN +#ifdef CONFIG_TARGET_ORIGEN #define TIMINGREF_VAL 0x000000BB #define TIMINGROW_VAL 0x4046654f #define TIMINGDATA_VAL 0x46400506 diff --git a/arch/arm/mach-exynos/include/mach/pwm_backlight.h b/arch/arm/mach-exynos/include/mach/pwm_backlight.h deleted file mode 100644 index c7d3a91e31..0000000000 --- a/arch/arm/mach-exynos/include/mach/pwm_backlight.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - */ - -#ifndef _PWM_BACKLIGHT_H_ -#define _PWM_BACKLIGHT_H_ - -struct pwm_backlight_data { - int pwm_id; - int period; - int max_brightness; - int brightness; -}; - -extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd); - -#endif /* _PWM_BACKLIGHT_H_ */ diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 48f13c7648..5d0bebac57 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -116,6 +116,5 @@ struct exynos5_sysreg { void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); -int exynos_lcd_early_init(const void *blob); #endif /* _EXYNOS4_SYSTEM_H */ diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 2645a8ff49..1ff5fcac1b 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -49,6 +49,10 @@ enum { }; #ifdef CONFIG_EXYNOS5420 + +/* Address for relocating helper code (Last 4 KB of IRAM) */ +#define EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) + /* * Power up secondary CPUs. */ @@ -56,7 +60,7 @@ static void secondary_cpu_start(void) { v7_enable_smp(EXYNOS5420_INFORM_BASE); svc32_mode_en(); - branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE); + branch_bx(EXYNOS_RELOCATE_CODE_BASE); } /* @@ -153,7 +157,7 @@ static void power_down_core(void) static void secondary_cores_configure(void) { /* Clear secondary boot iRAM base */ - writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C)); + writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C)); /* set lowpower flag and address */ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S index 59d05e6c01..40c07209e4 100644 --- a/arch/arm/mach-exynos/sec_boot.S +++ b/arch/arm/mach-exynos/sec_boot.S @@ -21,7 +21,7 @@ relocate_wait_code: .ltorg /* * Secondary core waits here until Primary wake it up. - * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE. + * Below code is copied to (CONFIG_IRAM_TOP - 0x1000) * This is a workaround code which is supposed to act as a * substitute/supplement to the iROM code. * diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 5e1b20a422..2ba7454457 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -20,13 +20,13 @@ config MU_BASE_SPL config IMX8QM select IMX8 select SUPPORT_SPL - select SPL_RECOVER_DATA_SECTION + select SPL_RECOVER_DATA_SECTION if SPL bool config IMX8QXP select IMX8 select SUPPORT_SPL - select SPL_RECOVER_DATA_SECTION + select SPL_RECOVER_DATA_SECTION if SPL bool config SYS_SOC @@ -57,11 +57,13 @@ config TARGET_COLIBRI_IMX8X config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT + select FACTORYSET select IMX8QXP config TARGET_GIEDI bool "Support i.MX8QXP Capricorn Giedi board" select BOARD_LATE_INIT + select FACTORYSET select IMX8QXP config TARGET_IMX8QM_MEK diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b4b75f4e6c..70f6444e79 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -516,7 +516,7 @@ void spl_enable_dcache(void) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; - dram_init_banksize(); + dram_init(); /* reserve TLB table */ gd->arch.tlb_size = PGTABLE_SIZE; diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index f503f15f19..e56ca6d0f5 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -355,6 +355,17 @@ static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) return bootmode; } +u32 spl_spi_boot_bus(void) +{ + u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); + u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) | + ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT); + + return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0; +} + u32 spl_boot_device(void) { u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 988e758629..b3beeca947 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -324,9 +324,9 @@ static void *k3_sysfw_get_spi_addr(void) struct udevice *dev; fdt_addr_t addr; int ret; + unsigned int sf_bus = spl_spi_boot_bus(); - ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS, - &dev); + ret = uclass_find_device_by_seq(UCLASS_SPI, sf_bus, &dev); if (ret) return NULL; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index ca2da003b6..98bb10c2de 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -121,6 +121,18 @@ endchoice config SYS_SOC default "kirkwood" +config KIRKWOOD_RGMII_PAD_1V8 + bool "Configures the I/O voltage of the pads connected gigabit interface to 1.8V" + default y + +config KIRKWOOD_EGIGA_INIT + bool "Enable GbePort0/1 for kernel" + default y + +config KIRKWOOD_PCIE_INIT + bool "Enable PCIe Port0 for kernel" + default y + source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Synology/ds109/Kconfig" diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 45ee0272f7..90e86ab99b 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -23,9 +23,6 @@ #endif /* CONFIG_KW88F6281 */ #include <asm/arch/soc.h> -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE #define MV_UART_CONSOLE_BASE KW_UART0_BASE @@ -49,8 +46,6 @@ #define __io /* Data, registers and alternate blocks are at the same offset */ /* Each 8-bit ATA register is aligned to a 4-bytes address */ -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 /* CONFIG_IDE requires some #defines for ATA registers */ /* ATA registers base is at SATA controller base */ #endif /* CONFIG_IDE */ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index e1b9180a3b..fa41047476 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -169,6 +169,27 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE using hardware memory firewalls. This value must be smaller than the TI_SECURE_EMIF_TOTAL_REGION_SIZE value. +config SYS_AUTOMATIC_SDRAM_DETECTION + bool + +choice + depends on OMAP44XX || OMAP54XX + prompt "Static or dynamic DDR timing calculations" + default SYS_EMIF_PRECALCULATED_TIMING_REGS + help + For the DDR timing information we can either dynamically determine + the timings to use or use pre-determined timings (based on using the + dynamic method). Default to the static timing information. + +config SYS_EMIF_PRECALCULATED_TIMING_REGS + bool "Use precalcualted timing values" + +config SYS_DEFAULT_LPDDR2_TIMINGS + bool "Use default LPDDR2 timing values" + select SYS_AUTOMATIC_SDRAM_DETECTION + +endchoice + source "arch/arm/mach-omap2/omap3/Kconfig" source "arch/arm/mach-omap2/omap4/Kconfig" @@ -190,7 +211,4 @@ source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" source "board/phytec/phycore_am335x_r2/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - endif diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 23865d4c07..bd6b086552 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -138,6 +138,7 @@ config TARGET_DRACO select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_ETAMIN @@ -146,6 +147,7 @@ config TARGET_ETAMIN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_PCM051 @@ -168,6 +170,7 @@ config TARGET_PXM2 select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_RASTABAN @@ -176,6 +179,7 @@ config TARGET_RASTABAN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_RUT @@ -184,6 +188,7 @@ config TARGET_RUT select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_THUBAN @@ -192,6 +197,7 @@ config TARGET_THUBAN select DM select DM_GPIO select DM_SERIAL + select FACTORYSET imply CMD_DM config TARGET_PDU001 diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 25afd3cb60..c3249a7be4 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -65,9 +65,6 @@ source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" source "board/rockchip/evb_px5/Kconfig" -config SPL_LDSCRIPT - default "arch/arm/cpu/armv8/u-boot-spl.lds" - config SPL_STACK_R_ADDR default 0x04000000 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index e712a89534..71a7f8dcee 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,9 +1,5 @@ if ARCH_SUNXI -config SPL_LDSCRIPT - default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV - default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 - config IDENT_STRING default " Allwinner Technology" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 5309be9cc2..09ad2d6f5a 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -178,6 +178,10 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config TEGRA_GPU + bool "Enable setting up the GPU" + depends on TEGRA124 || TEGRA210 + config CMD_ENTERRCM bool "Enable 'enterrcm' command" default y diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 7b728ac110..000af974e8 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -58,6 +58,10 @@ struct rpu_regs { #define VERSAL_CRP_BASEADDR 0xF1260000 +#define VERSAL_SLCR_BASEADDR 0xF1060000 +#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504) +#define VERSAL_OSPI_LINEAR_MODE BIT(1) + struct crp_regs { u32 reserved0[128]; u32 boot_mode_usr; @@ -82,3 +86,14 @@ struct crp_regs { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 + +#define FLASH_RESET_GPIO 0xc +#define WPROT_CRP 0xF126001C +#define RST_GPIO 0xF1260318 +#define WPROT_LPD_MIO 0xFF080728 +#define WPROT_PMC_MIO 0xF1060828 +#define BOOT_MODE_DIR 0xF1020204 +#define BOOT_MODE_OUT 0xF1020208 +#define MIO_PIN_12 0xF1060030 +#define BANK0_OUTPUT 0xF1020040 +#define BANK0_TRI 0xF1060200 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index cf2e727916..b4c439b4cd 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,8 +1,5 @@ if ARCH_ZYNQ -config SPL_LDSCRIPT - default "arch/arm/mach-zynq/u-boot-spl.lds" - config SPL_FS_FAT default y diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile index ba90fc3c34..6a38c4838e 100644 --- a/arch/m68k/cpu/mcf5445x/Makefile +++ b/arch/m68k/cpu/mcf5445x/Makefile @@ -6,4 +6,4 @@ # ccflags-y += -DET_DEBUG extra-y = start.o -obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o +obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c deleted file mode 100644 index d487468d0b..0000000000 --- a/arch/m68k/cpu/mcf5445x/pci.c +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * PCI Configuration space access support - */ -#include <common.h> -#include <pci.h> -#include <asm/io.h> -#include <asm/immap.h> -#include <linux/delay.h> - -#if defined(CONFIG_PCI) -/* System RAM mapped over PCI */ -#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) - -#define cfg_read(val, addr, type, op) *val = op((type)(addr)); -#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); - -#define PCI_OP(rw, size, type, op, mask) \ -int pci_##rw##_cfg_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - u32 addr = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), \ - PCI_FUNC(dev), offset); \ - out_be32(hose->cfg_addr, addr); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - out_be32(hose->cfg_addr, addr & ~PCI_CONF1_ENABLE); \ - return 0; \ -} - -PCI_OP(read, byte, u8 *, in_8, 3) -PCI_OP(read, word, u16 *, in_le16, 2) -PCI_OP(read, dword, u32 *, in_le32, 0) -PCI_OP(write, byte, u8, out_8, 3) -PCI_OP(write, word, u16, out_le16, 2) -PCI_OP(write, dword, u32, out_le32, 0) - -void pci_mcf5445x_init(struct pci_controller *hose) -{ - pci_t *pci = (pci_t *)MMAP_PCI; - pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - u32 barEn = 0; - - out_be32(&pciarb->acr, 0x001f001f); - - /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, - PCIREQ2, PCIGNT2 */ - out_be16(&gpio->par_pci, - GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | - GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 | - GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | - GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0); - - /* Assert reset bit */ - setbits_be32(&pci->gscr, PCI_GSCR_PR); - - setbits_be32(&pci->tcr1, PCI_TCR1_P); - - /* Initiator windows */ - out_be32(&pci->iw0btar, - CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); - out_be32(&pci->iw1btar, - CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); - out_be32(&pci->iw2btar, - CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); - - out_be32(&pci->iwcr, - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); - - out_be32(&pci->icr, 0); - - /* Enable bus master and mem access */ - out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); - - /* Cache line size and master latency */ - out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8)); - out_be32(&pci->cr2, 0); - -#ifdef CONFIG_SYS_PCI_BAR0 - out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); - out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B0E; -#endif -#ifdef CONFIG_SYS_PCI_BAR1 - out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); - out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B1E; -#endif -#ifdef CONFIG_SYS_PCI_BAR2 - out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2)); - out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B2E; -#endif -#ifdef CONFIG_SYS_PCI_BAR3 - out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3)); - out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B3E; -#endif -#ifdef CONFIG_SYS_PCI_BAR4 - out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4)); - out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B4E; -#endif -#ifdef CONFIG_SYS_PCI_BAR5 - out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5)); - out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN); - barEn |= PCI_TCR2_B5E; -#endif - - out_be32(&pci->tcr2, barEn); - - /* Deassert reset bit */ - clrbits_be32(&pci->gscr, PCI_GSCR_PR); - udelay(1000); - - /* Enable PCI bus master support */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, - CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - - pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, - CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 3; - - hose->cfg_addr = &(pci->car); - hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; - - pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, - pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, - pci_write_cfg_dword); - - /* Hose scan */ - pci_register_hose(hose); - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCI */ diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index 221eb93d58..bad0026648 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index 221eb93d58..bad0026648 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h index 221eb93d58..bad0026648 100644 --- a/arch/mips/include/asm/config.h +++ b/arch/mips/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index d1b9ae4c3c..9a31604ba3 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -11,6 +11,11 @@ config E300 config SYS_CPU default "mpc83xx" +config SYS_83XX_DDR_USES_CS0 + bool + help + DDR should be configured using CS0 and CS1 instead of CS2 and CS3. + choice prompt "Target select" optional @@ -19,6 +24,7 @@ config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X select BOARD_EARLY_INIT_F + select SYS_83XX_DDR_USES_CS0 config TARGET_IDS8313 bool "Support ids8313" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index e3e1bfd65a..33835eeec2 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -251,19 +251,6 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif -#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X) - uint32_t temp; - struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - - /* Configure interface. */ - setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); - - /* Wait for clock to stabilize */ - do { - temp = __raw_readl(&ehci->control); - udelay(1000); - } while (!(temp & PHY_CLK_VALID)); -#endif } int cpu_init_r (void) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c1b4e94d91..915e28e110 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -109,6 +109,7 @@ config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" select ARCH_QEMU_E500 select PHYS_64BIT + select SYS_RAMBOOT imply OF_HAS_PRIOR_STAGE config TARGET_T1024RDB @@ -187,6 +188,7 @@ config ARCH_B4420 select E500MC select E6500 select FSL_LAW + select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 @@ -195,7 +197,7 @@ config ARCH_B4420 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 @@ -214,6 +216,7 @@ config ARCH_B4860 select E500MC select E6500 select FSL_LAW + select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 @@ -222,7 +225,7 @@ config ARCH_B4860 select SYS_FSL_ERRATUM_A006475 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007075 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 @@ -733,7 +736,7 @@ config ARCH_T2080 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -766,7 +769,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST select SYS_FSL_ERRATUM_A007798 select SYS_FSL_ERRATUM_A007815 select SYS_FSL_ERRATUM_A007907 @@ -822,11 +825,8 @@ config FSL_LAW help Use Freescale common code for Local Access Window -config NXP_ESBC - bool "NXP_ESBC" - help - Enable Freescale Secure Boot feature. Normally selected - by defconfig. If unsure, do not change. +config HETROGENOUS_CLUSTERS + bool config MAX_CPUS int "Maximum number of CPUs permitted for MPC85xx" @@ -1121,6 +1121,35 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs. +if HETROGENOUS_CLUSTERS + +config SYS_MAPLE + def_bool y + +config SYS_CPRI + def_bool y + +config PPC_CLUSTER_START + int + default 0 + +config DSP_CLUSTER_START + int + default 1 + +config SYS_CPRI_CLK + int + default 3 + +config SYS_ULB_CLK + int + default 4 + +config SYS_ETVPE_CLK + int + default 1 +endif + config BACKSIDE_L2_CACHE bool @@ -1185,6 +1214,45 @@ config SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). +config ENABLE_36BIT_PHYS + bool "Enable 36bit physical address space support" + +config SYS_BOOK3E_HV + bool "Category E.HV is supported" + depends on BOOKE + +config SYS_CPC_REINIT_F + bool + help + The CPC is configured as SRAM at the time of U-Boot entry and is + required to be re-initialized. + +config SYS_FSL_CPC + bool "Corenet Platform Cache support" + +config SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up" + depends on MPC85xx + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section. + +config SPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in SPL" + depends on MPC85xx && SPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + +config TPL_SYS_MPC85XX_NO_RESETVEC + bool "Discard resetvec section and move bootpg section up, in TPL" + depends on MPC85xx && TPL + help + If this variable is specified, the section .resetvec is not kept and + the section .bootpg is placed in the previous 4k of the .text section, + of the SPL portion of the binary. + config FSL_VIA bool diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9a28269020..8a6340d800 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1126,9 +1126,8 @@ switch_as: #else /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h - ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l - addi r3,r3,_start_cont - _start_cont + lis r3,_start_cont@h + ori r3,r3,_start_cont@l mtlr r3 blr #endif @@ -1600,7 +1599,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0,r10,in_ram - _start_cont + addi r0,r10,in_ram - CONFIG_VAL(SYS_MONITOR_BASE) /* * As IVPR is going to point RAM address, diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 06a70ff2af..62c3c51dea 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -9,24 +9,15 @@ #include "config.h" OUTPUT_ARCH(powerpc) -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} -#endif + SECTIONS { + . = IMAGE_TEXT_BASE; + .text : { /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg IMAGE_TEXT_BASE - 0x1000 : - { +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) KEEP(*(.bootpg)) - } :text = 0xffff #endif - . = IMAGE_TEXT_BASE; - .text : { *(.text*) } _etext = .; @@ -75,7 +66,7 @@ SECTIONS #endif /* For nor and nand is needed the SPL with section .resetvec */ -#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC +#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ #ifndef BOOT_PAGE_OFFSET #define BOOT_PAGE_OFFSET 0x1000 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 8bbe319b3e..8fba712655 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -14,32 +14,22 @@ OUTPUT_ARCH(powerpc) ENTRY(_start) -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - SECTIONS { /* Read-only sections, merged into text segment: */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 : + .text : { +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - . = CONFIG_SYS_TEXT_BASE; #endif - .text : - { *(.text*) - } :text + } _etext = .; PROVIDE (etext = .); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text + } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -84,16 +74,16 @@ SECTIONS __init_end = .; _end = .; -#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC +#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) .bootpg RESET_VECTOR_ADDRESS - 0xffc : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) - } :text = 0xffff + } = 0xffff .resetvec RESET_VECTOR_ADDRESS : { KEEP(*(.resetvec)) - } :text = 0xffff + } = 0xffff . = RESET_VECTOR_ADDRESS + 0x4; @@ -115,7 +105,7 @@ SECTIONS *(.sbss*) *(.bss*) *(COMMON) - } :bss + } . = ALIGN(4); __bss_end = . ; diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 67f8b10001..871554a7f4 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -17,10 +17,6 @@ #include <phy.h> #include <hwconfig.h> -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) { diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 0d0cd2273c..ea215ab075 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -13,49 +13,6 @@ compatible = "fsl,p2020-immr", "simple-bus"; bus-frequency = <0x0>; - usb@22000 { - compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; - reg = <0x22000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <28 0x2 0 0>; - phy_type = "ulpi"; - }; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic"; - device_type = "open-pic"; - big-endian; - single-cpu-affinity; - last-interrupt-source = <255>; - }; - - esdhc: sdhc@2e000 { - compatible = "fsl,p2020-esdhc", "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <72 0x2 0 0>; - /* Filled in by U-Boot */ - clock-frequency = <0>; - }; - - espi0: spi@7000 { - compatible = "fsl,mpc8536-espi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7000 0x1000>; - interrupts = < 0x3b 0x02 0x00 0x00 >; - fsl,espi-num-chipselects = <4>; - }; - -/include/ "pq3-i2c-0.dtsi" -/include/ "pq3-i2c-1.dtsi" -/include/ "pq3-duart-0.dtsi" -/include/ "pq3-gpio-0.dtsi" - ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; @@ -74,6 +31,22 @@ interrupts = <18 2 0 0>; }; +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" +/include/ "pq3-duart-0.dtsi" + + espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + interrupts = < 0x3b 0x02 0x00 0x00 >; + fsl,espi-num-chipselects = <4>; + }; + +/include/ "pq3-dma-1.dtsi" +/include/ "pq3-gpio-0.dtsi" + L2: l2-cache-controller@20000 { compatible = "fsl,p2020-l2-cache-controller"; reg = <0x20000 0x1000>; @@ -83,7 +56,15 @@ }; /include/ "pq3-dma-0.dtsi" -/include/ "pq3-dma-1.dtsi" + + usb@22000 { + compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; + reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <28 0x2 0 0>; + phy_type = "ulpi"; + }; /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" @@ -95,6 +76,14 @@ /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" + esdhc: sdhc@2e000 { + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2 0 0>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; + /include/ "pq3-sec3.1-0.dtsi" /include/ "pq3-mpic.dtsi" /include/ "pq3-mpic-timer-B.dtsi" diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 059ffe1fd4..79fe567b58 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -14,8 +14,6 @@ #define HWCONFIG_BUFFER_SIZE 256 #endif -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #ifndef CONFIG_MAX_MEM_MAPPED #if defined(CONFIG_E500) || \ defined(CONFIG_MPC86xx) || \ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 47bfcc7244..a43e6e5e53 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -18,8 +18,6 @@ /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SEC_MON_BE #if defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 @@ -31,35 +29,27 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_ESDHC_HC_BLK_ADDR /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -68,11 +58,9 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -84,7 +72,6 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -92,9 +79,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -118,7 +102,6 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -132,7 +115,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" @@ -151,7 +133,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" @@ -163,16 +144,13 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 @@ -180,7 +158,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_T4240) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -204,7 +181,6 @@ #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 @@ -219,33 +195,21 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SFP_VER_3_0 -#define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ -#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ -#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_MAPLE -#define CONFIG_SYS_CPRI #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FM1_CLK 0 -#define CONFIG_SYS_CPRI_CLK 3 -#define CONFIG_SYS_ULB_CLK 4 -#define CONFIG_SYS_ETVPE_CLK 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_SFP_VER_3_0 #ifdef CONFIG_ARCH_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 @@ -255,7 +219,6 @@ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -278,7 +241,6 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -295,7 +257,6 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T1024) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -309,7 +270,6 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 @@ -323,7 +283,6 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T2080) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -333,7 +292,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_PCI_VER_3_X #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 4 @@ -343,7 +301,6 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK 0 @@ -354,10 +311,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE -#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_C29X) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3a1d858ec6..3e707600f2 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,28 +10,17 @@ #ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 -#elif defined(CONFIG_TARGET_BSC9132QDS) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 -#elif defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 -#if defined(CONFIG_TARGET_B4860QDS) || \ - defined(CONFIG_TARGET_B4420QDS) || \ - defined(CONFIG_TARGET_T4240QDS) || \ - defined(CONFIG_TARGET_T2080QDS) || \ +#if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ defined(CONFIG_TARGET_T1042RDB) || \ defined(CONFIG_TARGET_T1042D4RDB) || \ defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_CPC_REINIT_F -#endif -#define CONFIG_KEY_REVOCATION #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 #endif @@ -47,10 +36,6 @@ #endif #endif -#if defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_KEY_REVOCATION -#endif - #if defined(CONFIG_ARCH_P3041) || \ defined(CONFIG_ARCH_P4080) || \ defined(CONFIG_ARCH_P5040) || \ @@ -80,55 +65,9 @@ #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 #define CONFIG_SPL_JR0_LIODN_S 454 #define CONFIG_SPL_JR0_LIODN_NS 458 -/* - * Define the key hash for U-Boot here if public/private key pair used to - * sign U-boot are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_SPL_UBOOT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - * else leave it defined as NULL - */ - -#define CONFIG_SPL_UBOOT_KEY_HASH NULL #endif /* ifdef CONFIG_SPL_BUILD */ -#define CONFIG_FSL_SEC_MON - #ifndef CONFIG_SPL_BUILD -/* - * fsl_setenv_chain_of_trust() must be called from - * board_late_init() - */ - -/* If Boot Script is not on NOR and is required to be copied on RAM */ -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_HDR_ADDR_RAM 0x00010000 -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 -#define CONFIG_BS_HDR_SIZE 0x00002000 -#define CONFIG_BS_ADDR_RAM 0x00012000 -#define CONFIG_BS_ADDR_DEVICE 0x00802000 -#define CONFIG_BS_SIZE 0x00001000 - -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#else - -/* The bootscript header address is different for B4860 because the NOR - * mapping is different on B4 due to reduced NOR size. - */ -#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 -#elif defined(CONFIG_FSL_CORENET) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 -#elif defined(CONFIG_TARGET_BSC9132QDS) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 -#elif defined(CONFIG_TARGET_C29XPCIE) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 -#else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 -#endif - -#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ - #include <config_fsl_chain_trust.h> #endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index d2443dc90d..6d1ddbcd27 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -666,19 +666,6 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#ifndef CONFIG_ARCH_MPC834X -#ifdef CONFIG_HAS_FSL_MPH_USB -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 -#else -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ -#endif -#else -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 -#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 -#endif - #elif defined(CONFIG_ARCH_MPC8313) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ @@ -944,15 +931,6 @@ struct ccsr_gpio { #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) -#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET -#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000 -#endif -#define CONFIG_SYS_MPC83xx_USB1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) -#if defined(CONFIG_ARCH_MPC834X) -#define CONFIG_SYS_MPC83xx_USB2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) -#endif #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff --git a/arch/riscv/include/asm/config.h b/arch/riscv/include/asm/config.h index d911007537..c55c85d4e6 100644 --- a/arch/riscv/include/asm/config.h +++ b/arch/riscv/include/asm/config.h @@ -7,6 +7,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7cbfd6c972..7e86c6a0cd 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -945,6 +945,7 @@ config ACPI_GPE config SPL_ACPI_GPE bool "Support ACPI general-purpose events in SPL" + depends on SPL help Enable a driver for ACPI GPEs to allow peripherals to send interrupts via ACPI to the OS. In U-Boot this is only used when U-Boot itself @@ -956,6 +957,7 @@ config SPL_ACPI_GPE config TPL_ACPI_GPE bool "Support ACPI general-purpose events in TPL" + depends on TPL help Enable a driver for ACPI GPEs to allow peripherals to send interrupts via ACPI to the OS. In U-Boot this is only used when U-Boot itself diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h index 221eb93d58..bad0026648 100644 --- a/arch/x86/include/asm/config.h +++ b/arch/x86/include/asm/config.h @@ -6,6 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #endif diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile index fbbdefaf2c..c22c50ac4e 100644 --- a/arch/xtensa/dts/Makefile +++ b/arch/xtensa/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb +dtb-$(CONFIG_XTENSA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb include $(srctree)/scripts/Makefile.dts diff --git a/board/advantech/imx8mp_rsb3720a1/Kconfig b/board/advantech/imx8mp_rsb3720a1/Kconfig index 4486ed6d33..95cac7c4f0 100644 --- a/board/advantech/imx8mp_rsb3720a1/Kconfig +++ b/board/advantech/imx8mp_rsb3720a1/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mp_rsb3720" -source "board/freescale/common/Kconfig" - endif diff --git a/board/advantech/imx8qm_rom7720_a1/Kconfig b/board/advantech/imx8qm_rom7720_a1/Kconfig index 8bf3a7d348..c846537f74 100644 --- a/board/advantech/imx8qm_rom7720_a1/Kconfig +++ b/board/advantech/imx8qm_rom7720_a1/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/advantech/imx8qm_rom7720_a1/imximage.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/armadeus/opos6uldev/opos6uldev.env b/board/armadeus/opos6uldev/opos6uldev.env new file mode 100644 index 0000000000..585f28ca85 --- /dev/null +++ b/board/armadeus/opos6uldev/opos6uldev.env @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Copyright (C) 2017 Armadeus Systems + */ + +/* Environment is stored in the eMMC boot partition */ + +env_version=100 +consoledev=ttymxc0 +board_name=opos6ul +fdt_addr=0x88000000 +fdt_high=0xffffffff +fdt_name=opos6uldev +initrd_high=0xffffffff +ip_dyn=yes +stdin=serial +stdout=serial +stderr=serial +mmcdev=0 +mmcpart=2 +mmcroot=/dev/mmcblk0p2 ro +mmcrootfstype=ext4 rootwait +kernelimg=opos6ul-linux.bin +splashpos=0,0 +splashimage=CONFIG_SYS_LOAD_ADDR +videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0 +check_env=if test -n ${flash_env_version}; + then env default env_version; + else env set flash_env_version ${env_version}; env save; + fi; + if itest ${flash_env_version} != ${env_version}; then + echo "*** Warning - Environment version + change suggests: run flash_reset_env; reset"; + env default flash_reset_env; + else exit; fi; +flash_reset_env=env default -f -a && saveenv && + echo Environment variables erased! +download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl +flash_uboot_spl= + if mmc dev 0 1; then + setexpr sz ${filesize} / 0x200; + setexpr sz ${sz} + 1; + if mmc write ${loadaddr} 0x2 ${sz}; then + echo Flashing of U-boot SPL succeed; + else echo Flashing of U-boot SPL failed; + fi; + fi; +download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img +flash_uboot_img= + if mmc dev 0 1; then + setexpr sz ${filesize} / 0x200; + setexpr sz ${sz} + 1; + if mmc write ${loadaddr} 0x8a ${sz}; then + echo Flashing of U-boot image succeed; + else echo Flashing of U-boot image failed; + fi; + fi; +update_uboot=run download_uboot_spl flash_uboot_spl + download_uboot_img flash_uboot_img +download_kernel=tftpboot ${loadaddr} ${kernelimg} +flash_kernel= + if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then + echo kernel update succeed; + else echo kernel update failed; + fi; +update_kernel=run download_kernel flash_kernel +download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb +flash_dtb= + if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then + echo dtb update succeed; + else echo dtb update in failed; + fi; +update_dtb=run download_dtb flash_dtb +download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4 +flash_rootfs= + if mmc dev 0 0; then + setexpr nbblocks ${filesize} / 0x200; + setexpr nbblocks ${nbblocks} + 1; + if mmc write ${loadaddr} 0x40800 ${nbblocks}; then + echo Flashing of rootfs image succeed; + else echo Flashing of rootfs image failed; + fi; + fi; +update_rootfs=run download_rootfs flash_rootfs +flash_failsafe= + if mmc dev 0 0; then + setexpr nbblocks ${filesize} / 0x200; + setexpr nbblocks ${nbblocks} + 1; + if mmc write ${loadaddr} 0x800 ${nbblocks}; then + echo Flashing of rootfs image in failsafe partition succeed; + else echo Flashing of rootfs image in failsafe partition failed; + fi; + fi; +update_failsafe=run download_rootfs flash_failsafe +download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4 +flash_userdata= + if mmc dev 0 0; then + setexpr nbblocks ${filesize} / 0x200; + setexpr nbblocks ${nbblocks} + 1; + if mmc write ${loadaddr} 0 ${nbblocks}; then + echo Flashing of user_data image succeed; + else echo Flashing of user_data image failed; + fi; + fi; +update_userdata=run download_userdata flash_userdata; mmc rescan +erase_userdata= + if mmc dev 0 0; then + echo Erasing eMMC User Data partition, no way out...; + mw ${loadaddr} 0 0x200000; + mmc write ${loadaddr} 0 0x1000; + mmc write ${loadaddr} 0x800 0x1000; + mmc write ${loadaddr} 0x40800 0x1000; + mmc write ${loadaddr} 0x440800 0x1000; + fi; + mmc rescan +update_all=run update_rootfs update_uboot +initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs} +addipargs=setenv bootargs ${bootargs} + ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off +addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} + rootfstype=${mmcrootfstype} +emmcboot=run initargs; run addmmcargs; + load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && + load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && + bootz ${loadaddr} - ${fdt_addr}; +emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot; +addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw + nfsroot=${serverip}:${rootpath} +nfsboot=run initargs; run addnfsargs addipargs; + nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && + nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && + bootz ${loadaddr} - ${fdt_addr}; diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index ef82f06607..50a3830b85 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -168,7 +168,8 @@ Altera_CYC2_Passive_Serial_fns altera_fns = { altera_post_fn }; -Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = { +#define FPGA_COUNT 1 +Altera_desc altera_fpga[FPGA_COUNT] = { {Altera_CYC2, passive_serial, 85903, @@ -182,7 +183,7 @@ int astro5373l_altera_load(void) { int i; - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + for (i = 0; i < FPGA_COUNT; i++) { /* * I did not yet manage to get relocation work properly, * so set stuff here instead of static initialisation: @@ -372,7 +373,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = { xilinx_fastwr_config_fn }; -xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc xilinx_fpga[FPGA_COUNT] = { {xilinx_spartan3, slave_serial, XILINX_XC3S4000_SIZE, @@ -388,7 +389,7 @@ int astro5373l_xilinx_load(void) fpga_init(); - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + for (i = 0; i < FPGA_COUNT; i++) { /* * I did not yet manage to get relocation work properly, * so set stuff here instead of static initialisation: diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 38f97bce20..a9ea9b558a 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -74,9 +74,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 0318eeaa94..8a7a960c26 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -234,9 +234,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 3218e14e86..c3e1734dda 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -192,9 +192,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index fcca8923e3..347197a606 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -258,9 +258,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index a3fc55bbc3..018fed9cc2 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -176,9 +176,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index f427ee658b..af59620d0c 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -169,9 +169,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index e0abe4aeb0..8192824c59 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -105,9 +105,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 00de277812..d8f32c93b5 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -39,9 +39,6 @@ void board_debug_uart_init(void) int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 32e5a2bf23..7035fab878 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -101,9 +101,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index b69f1c8cfa..65d0a7532e 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -65,10 +65,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif - return 0; } #endif diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 67ada27072..c38585c6fe 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -58,10 +58,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif - return 0; } #endif diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index da697a7b0f..0207770028 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -48,9 +48,6 @@ void board_debug_uart_init(void) int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index cca5bd1d8a..16e9183f54 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -108,9 +108,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 4bbb05c2fb..9e0f9c3b7e 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -64,10 +64,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif - return 0; } #endif diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index c25bf42e0a..a778f2694d 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -87,9 +87,6 @@ int board_late_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index b6f8dcd91d..132e7fad1e 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -140,9 +140,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 2088b48b7e..9fb7e6f308 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -102,9 +102,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 46ec1eb324..ba38533343 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -100,9 +100,6 @@ void board_debug_uart_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif return 0; } #endif diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index ae18ed05e0..7d83e76f9a 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -48,9 +48,6 @@ void board_debug_uart_init(void) int board_early_init_f(void) { -#if (IS_ENABLED(CONFIG_DEBUG_UART)) - debug_uart_init(); -#endif return 0; } diff --git a/board/beacon/imx8mm/Kconfig b/board/beacon/imx8mm/Kconfig index 63f064e8cb..e5d8aa3ec9 100644 --- a/board/beacon/imx8mm/Kconfig +++ b/board/beacon/imx8mm/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/beacon/imx8mm/imximage-8mm-lpddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/beacon/imx8mn/Kconfig b/board/beacon/imx8mn/Kconfig index fb301397b1..e11286c5c3 100644 --- a/board/beacon/imx8mn/Kconfig +++ b/board/beacon/imx8mn/Kconfig @@ -18,6 +18,4 @@ config IMX8MN_BEACON_2GB_LPDDR config IMX_CONFIG default "board/beacon/imx8mn/imximage-8mn-lpddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/bsh/imx8mn_smm_s2/Kconfig b/board/bsh/imx8mn_smm_s2/Kconfig index f43d058f21..041a9c78a6 100644 --- a/board/bsh/imx8mn_smm_s2/Kconfig +++ b/board/bsh/imx8mn_smm_s2/Kconfig @@ -22,8 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BSH_SMM_S2_DDR3L_256 -source "board/freescale/common/Kconfig" - endif if TARGET_IMX8MN_BSH_SMM_S2PRO @@ -44,6 +42,4 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BSH_SMM_S2_DDR3L_512 -source "board/freescale/common/Kconfig" - endif diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig index d4a238de99..a1f2139219 100644 --- a/board/congatec/common/Kconfig +++ b/board/congatec/common/Kconfig @@ -1,44 +1,3 @@ -if !ARCH_IMX8M && !ARCH_IMX8 - -config CHAIN_OF_TRUST - depends on !FIT_SIGNATURE && SECURE_BOOT - imply CMD_BLOB - imply CMD_HASH if ARM - select FSL_CAAM - select SPL_BOARD_INIT if (ARM && SPL) - select SHA_HW_ACCEL - select SHA_PROG_HW_ACCEL - select ENV_IS_NOWHERE - select CMD_EXT4 if ARM - select CMD_EXT4_WRITE if ARM - bool - default y - -config CMD_ESBC_VALIDATE - bool "Enable the 'esbc_validate' and 'esbc_halt' commands" - default y if CHAIN_OF_TRUST - help - This option enables two commands used for secure booting: - - esbc_validate - validate signature using RSA verification - esbc_halt - put the core in spin loop (Secure Boot Only) - -endif - -config VOL_MONITOR_LTC3882_READ - depends on VID - bool "Enable the LTC3882 voltage monitor read" - help - This option enables LTC3882 voltage monitor read - functionality. It is used by common VID driver. - -config VOL_MONITOR_LTC3882_SET - depends on VID - bool "Enable the LTC3882 voltage monitor set" - help - This option enables LTC3882 voltage monitor set - functionality. It is used by common VID driver. - config USB_TCPC bool "USB Typec port controller simple driver" help diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 348fcf3bb0..99edaa3b42 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR; +/* Virtual address range for PCI region maps */ +#define SYS_PCI_MAP_START 0x80000000 +#define SYS_PCI_MAP_END 0xe0000000 + static void *get_fdt_virt(void) { if (gd->flags & GD_FLG_RELOC) @@ -101,7 +105,7 @@ static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr) map_addr += size - 1; map_addr &= ~(size - 1); - if (map_addr + size >= CONFIG_SYS_PCI_MAP_END) + if (map_addr + size >= SYS_PCI_MAP_END) return -1; /* Map virtual memory for range */ @@ -137,7 +141,7 @@ int misc_init_r(void) pci_get_regions(dev, &io, &mem, &pre); /* Start MMIO and PIO range maps above RAM */ - map_addr = CONFIG_SYS_PCI_MAP_START; + map_addr = SYS_PCI_MAP_START; /* Map MMIO range */ ret = pci_map_region(mem->phys_start, mem->size, &map_addr); diff --git a/board/engicam/imx8mm/Kconfig b/board/engicam/imx8mm/Kconfig index 5495b3bf99..3b3b93bb2f 100644 --- a/board/engicam/imx8mm/Kconfig +++ b/board/engicam/imx8mm/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig deleted file mode 100644 index b0e6e43f4f..0000000000 --- a/board/freescale/common/Kconfig +++ /dev/null @@ -1,110 +0,0 @@ -config CHAIN_OF_TRUST - depends on !FIT_SIGNATURE && NXP_ESBC - imply CMD_BLOB - imply CMD_HASH if ARM - select FSL_CAAM - select ARCH_MISC_INIT - select SPL_BOARD_INIT if (ARM && SPL) - select SPL_HASH if (ARM && SPL) - select SHA_HW_ACCEL - select SHA_PROG_HW_ACCEL - select ENV_IS_NOWHERE - select CMD_EXT4 if ARM - select CMD_EXT4_WRITE if ARM - bool - default y - -config CMD_ESBC_VALIDATE - bool "Enable the 'esbc_validate' and 'esbc_halt' commands" - default y if CHAIN_OF_TRUST - help - This option enables two commands used for secure booting: - - esbc_validate - validate signature using RSA verification - esbc_halt - put the core in spin loop (Secure Boot Only) - -config DEEP_SLEEP - bool "Enable SoC deep sleep feature" - default y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A - help - Indicates this SoC supports deep sleep feature. If deep sleep is - supported, core will start to execute uboot when wakes up. - -config FSL_USE_PCA9547_MUX - bool "Enable PCA9547 I2C Mux on Freescale boards" - help - This option enables the PCA9547 I2C mux on Freescale boards. - -config VID - bool "Enable Freescale VID" - depends on I2C || DM_I2C - help - This option enables setting core voltage based on individual - values saved in SoC fuses. - -config SPL_VID - bool "Enable Freescale VID in SPL" - depends on I2C || DM_I2C - help - This option enables setting core voltage based on individual - values saved in SoC fuses, in SPL. - -if VID || SPL_VID - -config VID_FLS_ENV - string "Environment variable for overriding VDD" - help - This option allows for specifying the environment variable - to check to override VDD information. - -config VOL_MONITOR_INA220 - bool "Enable the INA220 voltage monitor read" - help - This option enables INA220 voltage monitor read - functionality. It is used by the common VID driver. - -config VOL_MONITOR_IR36021_READ - bool "Enable the IR36021 voltage monitor read" - help - This option enables IR36021 voltage monitor read - functionality. It is used by the common VID driver. - -config VOL_MONITOR_IR36021_SET - bool "Enable the IR36021 voltage monitor set" - help - This option enables IR36021 voltage monitor set - functionality. It is used by the common VID driver. - -config VOL_MONITOR_LTC3882_READ - bool "Enable the LTC3882 voltage monitor read" - help - This option enables LTC3882 voltage monitor read - functionality. It is used by the common VID driver. - -config VOL_MONITOR_LTC3882_SET - bool "Enable the LTC3882 voltage monitor set" - help - This option enables LTC3882 voltage monitor set - functionality. It is used by the common VID driver. - -config VOL_MONITOR_ISL68233_READ - bool "Enable the ISL68233 voltage monitor read" - help - This option enables ISL68233 voltage monitor read - functionality. It is used by the common VID driver. - -config VOL_MONITOR_ISL68233_SET - bool "Enable the ISL68233 voltage monitor set" - help - This option enables ISL68233 voltage monitor set - functionality. It is used by the common VID driver. - -endif - -config FSL_QIXIS - bool "Enable QIXIS support" - -config QIXIS_I2C_ACCESS - bool "Access to QIXIS is over i2c" - depends on FSL_QIXIS - default y diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 7ffb315bc9..d31fb82181 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -12,6 +12,7 @@ #include <fsl_sfp.h> #include <log.h> #include <dm/root.h> +#include <asm/fsl_secure_boot.h> #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) #include <spl.h> @@ -76,14 +77,14 @@ int fsl_setenv_chain_of_trust(void) /* If Boot mode is Secure, set the environment variables * bootdelay = 0 (To disable Boot Prompt) - * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) + * bootcmd = CHAIN_BOOT_CMD (Validate and execute Boot script) */ env_set("bootdelay", "-2"); #ifdef CONFIG_ARM env_set("secureboot", "y"); #else - env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD); + env_set("bootcmd", CHAIN_BOOT_CMD); #endif return 0; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 34875d0b8f..f1a0b0cfc3 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -871,7 +871,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, int ret, i, hash_cmd = 0; u32 srk_hash[8]; - if (arg_hash_str != NULL) { + if (strlen(arg_hash_str) != 0) { const char *cp = arg_hash_str; int i = 0; diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 0860bd2312..af76327e4d 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -166,4 +166,25 @@ defined(CONFIG_TARGET_LX2160ARDB) #define QIXIS_ESDHC_NO_ADAPTER 0x7 #endif +/* + * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. + */ +static inline u8 qixis_esdhc_detect_quirk(void) +{ + /* + * SDHC1 Card ID: + * Specifies the type of card installed in the SDHC1 adapter slot. + * 000= (reserved) + * 001= eMMC V4.5 adapter is installed. + * 010= SD/MMC 3.3V adapter is installed. + * 011= eMMC V4.4 adapter is installed. + * 100= eMMC V5.0 adapter is installed. + * 101= MMC card/Legacy (3.3V) adapter is installed. + * 110= SDCard V2/V3 adapter installed. + * 111= no adapter is installed. + */ + return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) != + QIXIS_ESDHC_NO_ADAPTER); +} + #endif diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig index e92b0d099d..dbcd1afcba 100644 --- a/board/freescale/corenet_ds/Kconfig +++ b/board/freescale/corenet_ds/Kconfig @@ -9,8 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P3041DS" -source "board/freescale/common/Kconfig" - endif if TARGET_P4080DS @@ -24,8 +22,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P4080DS" -source "board/freescale/common/Kconfig" - endif if TARGET_P5040DS @@ -39,6 +35,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P5040DS" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig index 0adf87bd42..a148a9b998 100644 --- a/board/freescale/imx8mn_evk/Kconfig +++ b/board/freescale/imx8mn_evk/Kconfig @@ -15,6 +15,4 @@ config IMX8MN_LOW_DRIVE_MODE config IMX_CONFIG default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8mp_evk/Kconfig b/board/freescale/imx8mp_evk/Kconfig index 42625fd588..cafa6329a4 100644 --- a/board/freescale/imx8mp_evk/Kconfig +++ b/board/freescale/imx8mp_evk/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig index aed6ab25ce..5f2413f8db 100644 --- a/board/freescale/imx8qm_mek/Kconfig +++ b/board/freescale/imx8qm_mek/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/freescale/imx8qm_mek/imximage.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig index b9aab3789e..6533b4d953 100644 --- a/board/freescale/imx8qxp_mek/Kconfig +++ b/board/freescale/imx8qxp_mek/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/freescale/imx8qxp_mek/imximage.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig index 1e461ee1da..4637b969be 100644 --- a/board/freescale/imx8ulp_evk/Kconfig +++ b/board/freescale/imx8ulp_evk/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8ulp_evk" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig index 4ac69d7117..75de782afc 100644 --- a/board/freescale/ls1012afrdm/Kconfig +++ b/board/freescale/ls1012afrdm/Kconfig @@ -89,7 +89,3 @@ config SYS_LS_PFE_ESBC_LENGTH hex "length of PFE Firmware HDR" default 0xc00 endif - -if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY -source "board/freescale/common/Kconfig" -endif diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index 59b1a87665..991ba6044d 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -77,7 +77,4 @@ config PFE_SGMII_2500_PHY2_ADDR endif - -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index c4acea3ae2..aa15f5a027 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -63,8 +63,6 @@ config PFE_EMAC2_PHY_ADDR endif -source "board/freescale/common/Kconfig" - endif if TARGET_LS1012A2G5RDB @@ -119,6 +117,4 @@ config PFE_EMAC2_PHY_ADDR endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig index c6b16063a4..4a12c1687f 100644 --- a/board/freescale/ls1021aiot/Kconfig +++ b/board/freescale/ls1021aiot/Kconfig @@ -12,6 +12,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1021aiot" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig index 60b8472990..119b955041 100644 --- a/board/freescale/ls1021aqds/Kconfig +++ b/board/freescale/ls1021aqds/Kconfig @@ -12,6 +12,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1021aqds" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1021atsn/Kconfig b/board/freescale/ls1021atsn/Kconfig index d999fa4690..aa42a06c66 100644 --- a/board/freescale/ls1021atsn/Kconfig +++ b/board/freescale/ls1021atsn/Kconfig @@ -13,6 +13,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1021atsn" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig index a4641cbca0..bc50b8d966 100644 --- a/board/freescale/ls1021atwr/Kconfig +++ b/board/freescale/ls1021atwr/Kconfig @@ -12,6 +12,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1021atwr" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig index 40939816ad..5c27f0f726 100644 --- a/board/freescale/ls1028a/Kconfig +++ b/board/freescale/ls1028a/Kconfig @@ -32,8 +32,6 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif if TARGET_LS1028ARDB @@ -58,6 +56,4 @@ config SYS_TEXT_BASE default 0x82000000 if TFABOOT default 0x20100000 -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig index 182900efb7..4be445e8c8 100644 --- a/board/freescale/ls1043aqds/Kconfig +++ b/board/freescale/ls1043aqds/Kconfig @@ -28,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig index d66c7804b1..56502f9f9c 100644 --- a/board/freescale/ls1043ardb/Kconfig +++ b/board/freescale/ls1043ardb/Kconfig @@ -27,6 +27,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig index 6a4c3e92f7..68329d78ca 100644 --- a/board/freescale/ls1046afrwy/Kconfig +++ b/board/freescale/ls1046afrwy/Kconfig @@ -13,5 +13,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1046afrwy" -source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig index 1616dcc683..adf325f4ef 100644 --- a/board/freescale/ls1046aqds/Kconfig +++ b/board/freescale/ls1046aqds/Kconfig @@ -28,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig index 4c31e0e885..1fb391c991 100644 --- a/board/freescale/ls1046ardb/Kconfig +++ b/board/freescale/ls1046ardb/Kconfig @@ -27,5 +27,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig index 8bb828e3fd..f1a4523606 100644 --- a/board/freescale/ls1088a/Kconfig +++ b/board/freescale/ls1088a/Kconfig @@ -26,7 +26,6 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" endif if TARGET_LS1088ARDB @@ -57,5 +56,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig index 6b2b64581d..1036f33c61 100644 --- a/board/freescale/ls2080aqds/Kconfig +++ b/board/freescale/ls2080aqds/Kconfig @@ -29,6 +29,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig index 678d582573..c8b0b94596 100644 --- a/board/freescale/ls2080ardb/Kconfig +++ b/board/freescale/ls2080ardb/Kconfig @@ -12,8 +12,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls2080ardb" -source "board/freescale/common/Kconfig" - if FSL_LS_PPA config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" @@ -30,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR endif endif -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig index 7556f7dd21..0e4b4158a7 100644 --- a/board/freescale/lx2160a/Kconfig +++ b/board/freescale/lx2160a/Kconfig @@ -12,7 +12,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "lx2160ardb" -source "board/freescale/common/Kconfig" endif if TARGET_LX2160AQDS @@ -29,7 +28,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "lx2160aqds" -source "board/freescale/common/Kconfig" endif if TARGET_LX2162AQDS @@ -46,5 +44,4 @@ config SYS_SOC config SYS_CONFIG_NAME default "lx2162aqds" -source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 49d96d3fa2..a078643708 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -356,27 +356,6 @@ int checkboard(void) } #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -/* - * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. - */ -u8 qixis_esdhc_detect_quirk(void) -{ - /* - * SDHC1 Card ID: - * Specifies the type of card installed in the SDHC1 adapter slot. - * 000= (reserved) - * 001= eMMC V4.5 adapter is installed. - * 010= SD/MMC 3.3V adapter is installed. - * 011= eMMC V4.4 adapter is installed. - * 100= eMMC V5.0 adapter is installed. - * 101= MMC card/Legacy (3.3V) adapter is installed. - * 110= SDCard V2/V3 adapter installed. - * 111= no adapter is installed. - */ - return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) != - QIXIS_ESDHC_NO_ADAPTER); -} - static void esdhc_adapter_card_ident(void) { u8 card_id, val; diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 2a4703579d..85f5f0c034 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -93,11 +93,6 @@ int testdram(void) #ifdef CONFIG_IDE #include <ata.h> -int ide_preinit(void) -{ - return (0); -} - void ide_set_reset(int idereset) { atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig index 87f3374bf4..bd9153bc0d 100644 --- a/board/freescale/mpc8548cds/Kconfig +++ b/board/freescale/mpc8548cds/Kconfig @@ -1,5 +1,8 @@ if TARGET_MPC8548CDS +config PCI1 + def_bool y + config SYS_BOARD default "mpc8548cds" diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig index 3adac4af1e..159bcc4f54 100644 --- a/board/freescale/p1010rdb/Kconfig +++ b/board/freescale/p1010rdb/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P1010RDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 5f4d713ca5..6bdfb356ee 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -9,7 +9,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 947bbc9a5a..56bc355d21 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -186,7 +186,11 @@ int checkboard(void) int bus_num = CONFIG_SYS_SPD_BUS_NUM; /* FIXME: This should just use the model from the device tree or similar */ - printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", BOARD_NAME, +#ifdef BOARD_NAME + printf("Board: %s ", BOARD_NAME); +#endif + + printf("CPLD: V%d.%d PCBA: V%d.0\n", in_8(&cpld_data->cpld_rev_major) & 0x0F, in_8(&cpld_data->cpld_rev_minor) & 0x0F, in_8(&cpld_data->pcba_rev) & 0x0F); @@ -224,8 +228,11 @@ int checkboard(void) val = (in & io_config) | (out & (~io_config)); puts("rom_loc: "); - if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { + if (0) { +#ifdef __SW_BOOT_SD + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { puts("sd"); +#endif #ifdef __SW_BOOT_SD2 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) { puts("sd"); diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 6ded38ac68..38843a96cb 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -65,9 +65,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_64K, 1), #endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig index 7e187dde72..78e11214a5 100644 --- a/board/freescale/p2041rdb/Kconfig +++ b/board/freescale/p2041rdb/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "P2041RDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 5bd2b99506..2a84e9bdf5 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -229,7 +229,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +#if defined(CONFIG_HAS_FSL_DR_USB) fsl_fdt_fixup_dr_usb(blob, bd); #endif diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig index 6deeb248a3..d538386d43 100644 --- a/board/freescale/t102xrdb/Kconfig +++ b/board/freescale/t102xrdb/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "T102xRDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig index e6e46fa126..e33d317365 100644 --- a/board/freescale/t104xrdb/Kconfig +++ b/board/freescale/t104xrdb/Kconfig @@ -11,6 +11,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "T104xRDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig index 58a31b6527..c419a59dbb 100644 --- a/board/freescale/t208xqds/Kconfig +++ b/board/freescale/t208xqds/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config SRIO_PCIE_BOOT_SLAVE bool "Boot as a SRIO PCIe slave device" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig index d4c061a5ea..35d884e6cc 100644 --- a/board/freescale/t208xrdb/Kconfig +++ b/board/freescale/t208xrdb/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config T2080RDB_REV_D bool "Support for T2080RDB revisions D and up" -source "board/freescale/common/Kconfig" - endif diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig index 542e574fed..d93e4532ac 100644 --- a/board/freescale/t4rdb/Kconfig +++ b/board/freescale/t4rdb/Kconfig @@ -9,6 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "T4240RDB" -source "board/freescale/common/Kconfig" - endif diff --git a/board/friendlyarm/Kconfig b/board/friendlyarm/Kconfig index f8f9cfd879..fa04727a6a 100644 --- a/board/friendlyarm/Kconfig +++ b/board/friendlyarm/Kconfig @@ -11,6 +11,7 @@ config S5P4418_ONEWIRE config PWM_NX bool "PWM" + select PWM_S5P help This enables LCD-Backlight control via PWM. endchoice diff --git a/board/gateworks/gw_ventana/gw_ventana.env b/board/gateworks/gw_ventana/gw_ventana.env new file mode 100644 index 0000000000..9a316c74f2 --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.env @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Gateworks Corporation + */ + +splashpos=m,m +splashimage=CONFIG_SYS_LOAD_ADDR +usb_pgood_delay=2000 +console=ttymxc1 +bootdevs=usb mmc sata flash +hwconfig=_UNKNOWN_ + +disk=0 +part=1 + +fdt_high=0xffffffff +fdt_addr=0x18000000 +initrd_high=0xffffffff +fixfdt=fdt addr ${fdt_addr} +bootdir=boot +loadfdt= + if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then + echo Loaded DTB from ${bootdir}/${fdt_file}; + run fixfdt; + elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then + echo Loaded DTB from ${bootdir}/${fdt_file1}; + run fixfdt; + elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then + echo Loaded DTB from ${bootdir}/${fdt_file2}; + run fixfdt; + fi + +fs=ext4 +script=6x_bootscript-ventana +loadscript= + if ${fsload} ${loadaddr} ${bootdir}/${script}; then + source ${loadaddr}; + fi + +uimage=uImage +mmc_root=mmcblk0p1 +mmc_boot= + setenv fsload "${fs}load mmc ${disk}:${part}"; + mmc dev ${disk} && mmc rescan && + setenv dtype mmc; run loadscript; + if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then + setenv bootargs console=${console},${baudrate} + root=/dev/${mmc_root} rootfstype=${fs} + rootwait rw ${video} ${extra}; + if run loadfdt; then + bootm ${loadaddr} - ${fdt_addr}; + else + bootm; + fi; + fi + +sata_boot= + setenv fsload "${fs}load sata ${disk}:${part}"; + sata init && + setenv dtype sata; run loadscript; + if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then + setenv bootargs console=${console},${baudrate} + root=/dev/sda1 rootfstype=${fs} + rootwait rw ${video} ${extra}; + if run loadfdt; then + bootm ${loadaddr} - ${fdt_addr}; + else + bootm; + fi; + fi + +usb_boot= + setenv fsload "${fs}load usb ${disk}:${part}"; + usb start && usb dev ${disk} && + setenv dtype usb; run loadscript; + if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then + setenv bootargs console=${console},${baudrate} + root=/dev/sda1 rootfstype=${fs} + rootwait rw ${video} ${extra}; + if run loadfdt; then + bootm ${loadaddr} - ${fdt_addr}; + else + bootm; + fi; + fi + +#ifdef CONFIG_SPI_FLASH +image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin +image_uboot=ventana/u-boot_spi.imx + +spi_koffset=0x90000 +spi_klen=0x200000 + +spi_updateuboot=echo Updating uboot from + ${serverip}:${image_uboot}...; + tftpboot ${loadaddr} ${image_uboot} && + sf probe && sf erase 0 80000 && + sf write ${loadaddr} 400 ${filesize} +spi_update=echo Updating OS from ${serverip}:${image_os} + to ${spi_koffset} ...; + tftp ${loadaddr} ${image_os} && + sf probe && + sf update ${loadaddr} ${spi_koffset} ${filesize} + +flash_boot= + if sf probe && + sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then + setenv bootargs console=${console},${baudrate} + root=/dev/mtdblock3 + rootfstype=squashfs,jffs2 + ${video} ${extra}; + bootm; + fi +#else +image_rootfs=openwrt-imx6-ventana-rootfs.ubi +nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; + tftp ${loadaddr} ${image_rootfs} && + nand erase.part rootfs && + nand write ${loadaddr} rootfs ${filesize} + +flash_boot= + setenv fsload 'ubifsload'; + ubi part rootfs; + if ubi check boot; then + ubifsmount ubi0:boot; + setenv root ubi0:rootfs ubi.mtd=2 + rootfstype=squashfs,ubifs; + setenv bootdir; + elif ubi check rootfs; then + ubifsmount ubi0:rootfs; + setenv root ubi0:rootfs ubi.mtd=2 + rootfstype=ubifs; + fi; + setenv dtype nand; run loadscript; + if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then + setenv bootargs console=${console},${baudrate} + root=${root} ${video} ${extra}; + if run loadfdt; then + ubifsumount; + bootm ${loadaddr} - ${fdt_addr}; + else + ubifsumount; bootm; + fi; + fi +#endif diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index ecc8c786b6..8a0b175856 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -102,8 +102,10 @@ int misc_init_r(void) int last_stage_init(void) { #if defined(CONFIG_TARGET_KMCOGE5NE) - struct bfticu_iomap *base = - (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; + /* + * BFTIC3 on the local bus CS4 + */ + struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000; u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; if (dip_switch != 0) { diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.env b/board/qualcomm/dragonboard410c/dragonboard410c.env new file mode 100644 index 0000000000..9d9a575a0c --- /dev/null +++ b/board/qualcomm/dragonboard410c/dragonboard410c.env @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* Does what recovery does */ +#define REFLASH(file, partnum) \ +part start mmc 0 partnum start && \ +part size mmc 0 partnum size && \ +tftp $loadaddr file && \ +mmc write $loadaddr $start $size && + +reflash= +mmc dev 0 && +usb start && +dhcp && +tftp $loadaddr dragonboard/rescue/gpt_both0.bin && +mmc write $loadaddr 0 43 && +mmc rescan && +REFLASH(dragonboard/rescue/NON-HLOS.bin, 1) +REFLASH(dragonboard/rescue/sbl1.mbn, 2) +REFLASH(dragonboard/rescue/rpm.mbn, 3) +REFLASH(dragonboard/rescue/tz.mbn, 4) +REFLASH(dragonboard/rescue/hyp.mbn, 5) +REFLASH(dragonboard/rescue/sec.dat, 6) +REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7) +REFLASH(dragonboard/u-boot.img, 8) +usb stop && +echo Reflash completed + +loadaddr=0x81000000 +initrd_high=0xffffffffffffffff +linux_image=Image +kernel_addr_r=0x81000000 +fdtfile=qcom/apq8016-sbc.dtb +fdt_addr_r=0x83000000 +ramdisk_addr_r=0x84000000 +scriptaddr=0x90000000 +pxefile_addr_r=0x90100000 diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index b43242fd3f..5320c1f2e0 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -112,10 +112,10 @@ int checkboard(void) } #endif -#ifdef CONFIG_S5P_PA_SYSRAM +#ifdef CONFIG_SMP_PEN_ADDR void smp_set_core_boot_addr(unsigned long addr, int corenr) { - writel(addr, CONFIG_S5P_PA_SYSRAM); + writel(addr, CONFIG_SMP_PEN_ADDR); /* make sure this write is really executed */ __asm__ volatile ("dsb\n"); diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index d06687620c..24bf355ef6 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -403,16 +403,6 @@ int exynos_early_init_f(void) return 0; } -void exynos_reset_lcd(void) -{ - gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); - gpio_direction_output(EXYNOS4_GPIO_Y45, 1); - udelay(10000); - gpio_direction_output(EXYNOS4_GPIO_Y45, 0); - udelay(10000); - gpio_direction_output(EXYNOS4_GPIO_Y45, 1); -} - int lcd_power(void) { #if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */ @@ -460,16 +450,3 @@ int mipi_power(void) #endif return 0; } - -#ifdef CONFIG_LCD -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif -#ifdef CONFIG_S6E8AX0 - s6e8ax0_init(); - env_set("lcdinfo", "lcd=s6e8ax0"); -#endif -} -#endif diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index a03dc87385..da7f0dc022 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -302,39 +302,4 @@ int mipi_power(void) return 0; } -void exynos_lcd_power_on(void) -{ -#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */ - struct pmic *p = pmic_get("MAX77686_PMIC"); - - /* LCD_2.2V_EN: GPC0[1] */ - gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en"); - gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP); - gpio_direction_output(EXYNOS4X12_GPIO_C01, 1); - - /* LDO25 VCC_3.1V_LCD */ - pmic_probe(p); - max77686_set_ldo_voltage(p, 25, 3100000); - max77686_set_ldo_mode(p, 25, OPMODE_LPM); -#endif -} - -void exynos_reset_lcd(void) -{ - /* reset lcd */ - gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset"); - gpio_direction_output(EXYNOS4X12_GPIO_F21, 0); - udelay(10); - gpio_set_value(EXYNOS4X12_GPIO_F21, 1); -} - -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif -#ifdef CONFIG_S6E8AX0 - s6e8ax0_init(); -#endif -} #endif /* LCD */ diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 3764b5478b..1dde2f799b 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -267,98 +267,6 @@ static int init_pmic_lcd(void) return 0; } -void exynos_cfg_lcd_gpio(void) -{ - unsigned int i, f3_end = 4; - - for (i = 0; i < 8; i++) { - /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ - gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2)); - gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2)); - gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2)); - /* pull-up/down disable */ - gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE); - gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE); - gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE); - - /* drive strength to max (24bit) */ - gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X); - gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); - gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X); - gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW); - gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X); - gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); - } - - for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) { - /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ - gpio_cfg_pin(i, S5P_GPIO_FUNC(2)); - /* pull-up/down disable */ - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - /* drive strength to max (24bit) */ - gpio_set_drv(i, S5P_GPIO_DRV_4X); - gpio_set_rate(i, S5P_GPIO_DRV_SLOW); - } - - /* gpio pad configuration for LCD reset. */ - gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); - gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT); -} - -int mipi_power(void) -{ - return 0; -} - -void exynos_reset_lcd(void) -{ - gpio_set_value(EXYNOS4_GPIO_Y45, 1); - udelay(10000); - gpio_set_value(EXYNOS4_GPIO_Y45, 0); - udelay(10000); - gpio_set_value(EXYNOS4_GPIO_Y45, 1); - udelay(100); -} - -void exynos_lcd_power_on(void) -{ - struct udevice *dev; - int ret; - u8 reg; - - ret = pmic_get("max8998-pmic", &dev); - if (ret) { - puts("Failed to get MAX8998!\n"); - return; - } - - reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3); - reg |= MAX8998_LDO17; - ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg); - if (ret) { - puts("MAX8998 LDO setting error\n"); - return; - } - - reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2); - reg |= MAX8998_LDO7; - ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg); - if (ret) { - puts("MAX8998 LDO setting error\n"); - return; - } -} - -void exynos_cfg_ldo(void) -{ - ld9040_cfg_ldo(); -} - -void exynos_enable_ldo(unsigned int onoff) -{ - ld9040_enable_ldo(onoff); -} - int exynos_init(void) { gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; @@ -390,18 +298,3 @@ int exynos_init(void) return 0; } - -#ifdef CONFIG_LCD -void exynos_lcd_misc_init(vidinfo_t *vid) -{ -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif - - /* for LD9040. */ - vid->pclk_name = 1; /* MPLL */ - vid->sclk_div = 1; - - env_set("lcdinfo", "lcd=ld9040"); -} -#endif diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig new file mode 100644 index 0000000000..131439fcfe --- /dev/null +++ b/board/siemens/common/Kconfig @@ -0,0 +1,2 @@ +config FACTORYSET + bool diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 3430a1ed01..27aad4eaae 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -59,7 +59,8 @@ int checkboard (void) f = get_board_sys_clk(); } else { src = "PCI_CLK"; - f = CONFIG_PCI_CLK_FREQ; + /* PCI is clocked by the external source at 33 MHz */ + f = 33000000; } printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); #else diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig index 4abcdb3aaf..49d02744a9 100644 --- a/board/sysam/stmark2/Kconfig +++ b/board/sysam/stmark2/Kconfig @@ -3,6 +3,9 @@ if TARGET_STMARK2 config CF_SBF def_bool y +config EXTRA_CLOCK + def_bool y + config SYS_INPUT_CLKSRC hex default 30000000 diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 4dd5e64299..d65ee1d696 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -9,6 +9,8 @@ #include <asm/io.h> #include <spl.h> +#include <dm/uclass.h> +#include <k3-ddrss.h> #include <fdt_support.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -23,17 +25,61 @@ int board_init(void) int dram_init(void) { - gd->ram_size = 0x80000000; - - return 0; + return fdtdec_setup_mem_size_base(); } int dram_init_banksize(void) { - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; - gd->ram_size = 0x80000000; + return fdtdec_setup_memory_banksize(); +} - return 0; +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_K3_AM64_DDRSS) +static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret; + + dram_init_banksize(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannot get RAM device for ddr size fixup: %d\n", ret); + + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret); +} +#else +static void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, + CONFIG_NR_DRAM_BANKS); + if (ret) + printf("Error fixing up memory node! %d\n", ret); +} +#endif + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ +#if defined(CONFIG_K3_AM64_DDRSS) + fixup_ddr_driver_for_ecc(spl_image); +#else + fixup_memory_node(spl_image); +#endif } +#endif diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig index d4ec759d7f..8036947e34 100644 --- a/board/ti/am64x/Kconfig +++ b/board/ti/am64x/Kconfig @@ -54,9 +54,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "am64x_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index 47b41cd6af..16a7476d9c 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -53,9 +53,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "am65x_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index de92eb0981..ed34991377 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -86,7 +86,7 @@ __weak void gpi2c_init(void) static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, u32 header, u32 size, uint8_t *ep) { - u32 hdr_read; + u32 hdr_read = 0xdeadbeef; int rc; #if CONFIG_IS_ENABLED(DM_I2C) @@ -103,21 +103,25 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, /* * Read the header first then only read the other contents. */ - rc = i2c_set_chip_offset_len(dev, 2); + rc = i2c_set_chip_offset_len(dev, 1); if (rc) return rc; - rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); - if (rc) - return rc; + /* + * Skip checking result here since this could be a valid i2c read fail + * on some boards that use 2 byte addressing. + * We must allow for fall through to check the data if 2 byte + * addressing works + */ + (void)dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); /* Corrupted data??? */ if (hdr_read != header) { /* * read the eeprom header using i2c again, but use only a - * 1 byte address (some legacy boards need this..) + * 2 byte address (some newer boards need this..) */ - rc = i2c_set_chip_offset_len(dev, 1); + rc = i2c_set_chip_offset_len(dev, 2); if (rc) return rc; @@ -142,19 +146,23 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, /* * Read the header first then only read the other contents. */ - byte = 2; + byte = 1; - rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); - if (rc) - return rc; + /* + * Skip checking result here since this could be a valid i2c read fail + * on some boards that use 2 byte addressing. + * We must allow for fall through to check the data if 2 byte + * addressing works + */ + (void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); /* Corrupted data??? */ if (hdr_read != header) { /* * read the eeprom header using i2c again, but use only a - * 1 byte address (some legacy boards need this..) + * 2 byte address (some newer boards need this..) */ - byte = 1; + byte = 2; rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); if (rc) @@ -434,6 +442,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, struct ti_am6_eeprom_record_board_id board_id; struct ti_am6_eeprom_record record; int rc; + int consecutive_bad_records = 0; /* Initialize with a known bad marker for i2c fails.. */ memset(ep, 0, sizeof(*ep)); @@ -470,7 +479,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, */ eeprom_addr = sizeof(board_id); - while (true) { + while (consecutive_bad_records < 10) { rc = dm_i2c_read(dev, eeprom_addr, (uint8_t *)&record.header, sizeof(record.header)); if (rc) @@ -506,6 +515,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, pr_err("%s: EEPROM parsing error!\n", __func__); return rc; } + consecutive_bad_records = 0; } else { /* * We may get here in case of larger records which @@ -513,6 +523,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, */ pr_err("%s: Ignoring record id %u\n", __func__, record.header.id); + consecutive_bad_records++; } eeprom_addr += record.header.len; diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index c28752a658..d19d30d59e 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -75,9 +75,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "j721e_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif @@ -108,9 +105,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "j721e_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 105461e1db..5d090048ce 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -382,19 +382,25 @@ void configure_serdes_torrent(void) ret = uclass_get_device_by_driver(UCLASS_PHY, DM_DRIVER_GET(torrent_phy_provider), &dev); - if (ret) + if (ret) { printf("Torrent init failed:%d\n", ret); + return; + } serdes.dev = dev; serdes.id = 0; ret = generic_phy_init(&serdes); - if (ret) - printf("phy_init failed!!\n"); + if (ret) { + printf("phy_init failed!!: %d\n", ret); + return; + } ret = generic_phy_power_on(&serdes); - if (ret) - printf("phy_power_on failed !!\n"); + if (ret) { + printf("phy_power_on failed!!: %d\n", ret); + return; + } } void configure_serdes_sierra(void) @@ -410,21 +416,27 @@ void configure_serdes_sierra(void) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(sierra_phy_provider), &dev); - if (ret) + if (ret) { printf("Sierra init failed:%d\n", ret); + return; + } count = device_get_child_count(dev); for (i = 0; i < count; i++) { ret = device_get_child(dev, i, &link_dev); - if (ret) - printf("probe of sierra child node %d failed\n", i); + if (ret) { + printf("probe of sierra child node %d failed: %d\n", i, ret); + return; + } if (link_dev->driver->id == UCLASS_PHY) { link.dev = link_dev; link.id = link_count++; ret = generic_phy_power_on(&link); - if (ret) - printf("phy_power_on failed !!\n"); + if (ret) { + printf("phy_power_on failed!!: %d\n", ret); + return; + } } } } diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig index 2e115f1417..6141798333 100644 --- a/board/ti/j721s2/Kconfig +++ b/board/ti/j721s2/Kconfig @@ -55,9 +55,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "j721s2_evm" -config SPL_LDSCRIPT - default "arch/arm/mach-omap2/u-boot-spl.lds" - source "board/ti/common/Kconfig" endif diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 6c8cf4592d..9305709a3c 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -159,6 +159,42 @@ const char * const toradex_display_adapters[] = { [159] = "Verdin DSI to LVDS Adapter", }; +const u32 toradex_ouis[] = { + [0] = 0x00142dUL, + [1] = 0x8c06cbUL, +}; + +static u32 get_serial_from_mac(struct toradex_eth_addr *eth_addr) +{ + int i; + u32 oui = ntohl(eth_addr->oui) >> 8; + u32 nic = ntohl(eth_addr->nic) >> 8; + + for (i = 0; i < ARRAY_SIZE(toradex_ouis); i++) { + if (toradex_ouis[i] == oui) + break; + } + + return (u32)((i << 24) + nic); +} + +void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr) +{ + u8 oui_index = tdx_serial >> 24; + u32 nic = tdx_serial & GENMASK(23, 0); + u32 oui; + + if (oui_index >= ARRAY_SIZE(toradex_ouis)) { + puts("Can't find OUI for this serial#\n"); + oui_index = 0; + } + + oui = toradex_ouis[oui_index]; + + eth_addr->oui = htonl(oui << 8); + eth_addr->nic = htonl(nic << 8); +} + #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC static int tdx_cfg_block_mmc_storage(u8 *config_block, int write) { @@ -331,8 +367,7 @@ int read_tdx_cfg_block(void) memcpy(&tdx_eth_addr, config_block + offset, 6); - /* NIC part of MAC address is serial number */ - tdx_serial = ntohl(tdx_eth_addr.nic) >> 8; + tdx_serial = get_serial_from_mac(&tdx_eth_addr); break; case TAG_HW: memcpy(&tdx_hw_tag, config_block + offset, 8); @@ -354,6 +389,18 @@ out: return ret; } +static int parse_assembly_string(char *string_to_parse, u16 *assembly) +{ + if (string_to_parse[3] >= 'A' && string_to_parse[3] <= 'Z') + *assembly = string_to_parse[3] - 'A'; + else if (string_to_parse[3] == '#') + *assembly = dectoul(&string_to_parse[4], NULL); + else + return -EINVAL; + + return 0; +} + static int get_cfgblock_interactive(void) { char message[CONFIG_SYS_CBSIZE]; @@ -362,6 +409,7 @@ static int get_cfgblock_interactive(void) char wb = 'n'; char mem8g = 'n'; int len = 0; + int ret = 0; /* Unknown module by default */ tdx_hw_tag.prodid = 0; @@ -545,13 +593,18 @@ static int get_cfgblock_interactive(void) } while (len < 4) { - sprintf(message, "Enter the module version (e.g. V1.1B): V"); + sprintf(message, "Enter the module version (e.g. V1.1B or V1.1#26): V"); len = cli_readline(message); } tdx_hw_tag.ver_major = console_buffer[0] - '0'; tdx_hw_tag.ver_minor = console_buffer[2] - '0'; - tdx_hw_tag.ver_assembly = console_buffer[3] - 'A'; + + ret = parse_assembly_string(console_buffer, &tdx_hw_tag.ver_assembly); + if (ret) { + printf("Parsing module version failed\n"); + return ret; + } while (len < 8) { sprintf(message, "Enter module serial number: "); @@ -754,6 +807,7 @@ static int get_cfgblock_carrier_interactive(void) { char message[CONFIG_SYS_CBSIZE]; int len; + int ret = 0; printf("Supported carrier boards:\n"); printf("CARRIER BOARD NAME\t\t [ID]\n"); @@ -767,13 +821,18 @@ static int get_cfgblock_carrier_interactive(void) tdx_car_hw_tag.prodid = dectoul(console_buffer, NULL); do { - sprintf(message, "Enter carrier board version (e.g. V1.1B): V"); + sprintf(message, "Enter carrier board version (e.g. V1.1B or V1.1#26): V"); len = cli_readline(message); } while (len < 4); tdx_car_hw_tag.ver_major = console_buffer[0] - '0'; tdx_car_hw_tag.ver_minor = console_buffer[2] - '0'; - tdx_car_hw_tag.ver_assembly = console_buffer[3] - 'A'; + + ret = parse_assembly_string(console_buffer, &tdx_car_hw_tag.ver_assembly); + if (ret) { + printf("Parsing module version failed\n"); + return ret; + } while (len < 8) { sprintf(message, "Enter carrier board serial number: "); @@ -950,8 +1009,7 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc, } /* Convert serial number to MAC address (the storage format) */ - tdx_eth_addr.oui = htonl(0x00142dUL << 8); - tdx_eth_addr.nic = htonl(tdx_serial << 8); + get_mac_from_serial(tdx_serial, &tdx_eth_addr); /* Valid Tag */ write_tag(config_block, &offset, TAG_VALID, NULL, 0); diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 43e662e41d..1790698486 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -114,4 +114,6 @@ int read_tdx_cfg_block_carrier(void); int try_migrate_tdx_cfg_block_carrier(void); +void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr); + #endif /* _TDX_CFG_BLOCK_H */ diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index 9db4553e0f..3798bf9537 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -20,15 +20,17 @@ #include <asm/setup.h> #include "tdx-common.h" -#define TORADEX_OUI 0x00142dUL +#define SERIAL_STR_LEN 8 +#define MODULE_VER_STR_LEN 4 // V1.1 +#define MODULE_REV_STR_LEN 3 // [A-Z] or #[26-99] #ifdef CONFIG_TDX_CFG_BLOCK -static char tdx_serial_str[9]; -static char tdx_board_rev_str[6]; +static char tdx_serial_str[SERIAL_STR_LEN + 1]; +static char tdx_board_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1]; #ifdef CONFIG_TDX_CFG_BLOCK_EXTRA -static char tdx_car_serial_str[9]; -static char tdx_car_rev_str[6]; +static char tdx_car_serial_str[SERIAL_STR_LEN + 1]; +static char tdx_car_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1]; static char *tdx_carrier_board_name; #endif @@ -79,21 +81,37 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif /* CONFIG_SERIAL_TAG */ +static const char *get_board_assembly(u16 ver_assembly) +{ + static char ver_name[MODULE_REV_STR_LEN + 1]; + + if (ver_assembly < 26) { + ver_name[0] = (char)ver_assembly + 'A'; + ver_name[1] = '\0'; + } else { + snprintf(ver_name, sizeof(ver_name), + "#%u", ver_assembly); + } + + return ver_name; +} + int show_board_info(void) { unsigned char ethaddr[6]; if (read_tdx_cfg_block()) { printf("MISSING TORADEX CONFIG BLOCK\n"); - tdx_eth_addr.oui = htonl(TORADEX_OUI << 8); - tdx_eth_addr.nic = htonl(tdx_serial << 8); + get_mac_from_serial(tdx_serial, &tdx_eth_addr); checkboard(); } else { - sprintf(tdx_serial_str, "%08u", tdx_serial); - sprintf(tdx_board_rev_str, "V%1d.%1d%c", - tdx_hw_tag.ver_major, - tdx_hw_tag.ver_minor, - (char)tdx_hw_tag.ver_assembly + 'A'); + snprintf(tdx_serial_str, sizeof(tdx_serial_str), + "%08u", tdx_serial); + snprintf(tdx_board_rev_str, sizeof(tdx_board_rev_str), + "V%1d.%1d%s", + tdx_hw_tag.ver_major, + tdx_hw_tag.ver_minor, + get_board_assembly(tdx_hw_tag.ver_assembly)); env_set("serial#", tdx_serial_str); @@ -109,12 +127,13 @@ int show_board_info(void) tdx_carrier_board_name = (char *) toradex_carrier_boards[tdx_car_hw_tag.prodid]; - sprintf(tdx_car_serial_str, "%08u", tdx_car_serial); - sprintf(tdx_car_rev_str, "V%1d.%1d%c", - tdx_car_hw_tag.ver_major, - tdx_car_hw_tag.ver_minor, - (char)tdx_car_hw_tag.ver_assembly + - 'A'); + snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str), + "%08u", tdx_car_serial); + snprintf(tdx_car_rev_str, sizeof(tdx_car_rev_str), + "V%1d.%1d%s", + tdx_car_hw_tag.ver_major, + tdx_car_hw_tag.ver_minor, + get_board_assembly(tdx_car_hw_tag.ver_assembly)); env_set("carrier_serial#", tdx_car_serial_str); printf("Carrier: Toradex %s %s, Serial# %s\n", @@ -170,7 +189,7 @@ int ft_common_board_setup(void *blob, struct bd_info *bd) if (tdx_hw_tag.ver_major) { char prod_id[5]; - sprintf(prod_id, "%04u", tdx_hw_tag.prodid); + snprintf(prod_id, sizeof(prod_id), "%04u", tdx_hw_tag.prodid); fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5); fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str, diff --git a/board/variscite/imx8mn_var_som/Kconfig b/board/variscite/imx8mn_var_som/Kconfig index cfe6fc8c2c..9a4003aa11 100644 --- a/board/variscite/imx8mn_var_som/Kconfig +++ b/board/variscite/imx8mn_var_som/Kconfig @@ -12,6 +12,4 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg" -source "board/freescale/common/Kconfig" - endif diff --git a/boot/Kconfig b/boot/Kconfig index 08451c65a5..17438b566d 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -555,8 +555,12 @@ config CHROMEOS_VBOOT distinguishing between booting Chrome OS in a basic way (developer mode) and a full boot. +config SYS_RAMBOOT + bool + config RAMBOOT_PBL bool "Freescale PBL(pre-boot loader) image format support" + select SYS_RAMBOOT if PPC help Some SoCs use PBL to load RCW and/or pre-initialization instructions. For more details refer to doc/README.pblimage @@ -575,6 +579,19 @@ config SPIFLASH endchoice +config FSL_FIXED_MMC_LOCATION + bool "PBL MMC is at a fixed location" + depends on SDCARD && !RAMBOOT_PBL + +config ESDHC_HC_BLK_ADDR + def_bool y + depends on FSL_FIXED_MMC_LOCATION && (ARCH_BSC9131 || ARCH_BSC9132 || ARCH_P1010) + help + In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and + code length of these soc specify the memory address in block address + format. Block length is fixed to 512 bytes as per the SD High + Capacity specification. + config SYS_FSL_PBL_PBI string "PBI(pre-boot instructions) commands for the PBL image" depends on RAMBOOT_PBL @@ -589,6 +606,14 @@ config SYS_FSL_PBL_RCW Enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details. +config SYS_BOOT_RAMDISK_HIGH + depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ + depends on !(NIOS2 || SANDBOX || SH || XTENSA) + def_bool y + help + Enable initrd_high functionality. If defined then the initrd_high + feature is enabled and the boot* ramdisk subcommand is enabled. + endmenu # Boot images menu "Boot timing" @@ -613,7 +638,7 @@ config BOOTSTAGE config SPL_BOOTSTAGE bool "Boot timing and reported in SPL" - depends on BOOTSTAGE + depends on BOOTSTAGE && SPL help Enable recording of boot time in SPL. To make this visible to U-Boot proper, enable BOOTSTAGE_STASH as well. This will stash the timing @@ -622,7 +647,7 @@ config SPL_BOOTSTAGE config TPL_BOOTSTAGE bool "Boot timing and reported in TPL" - depends on BOOTSTAGE + depends on BOOTSTAGE && TPL help Enable recording of boot time in SPL. To make this visible to U-Boot proper, enable BOOTSTAGE_STASH as well. This will stash the timing diff --git a/boot/bootm.c b/boot/bootm.c index dfa65f125e..86dbfbcfed 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -33,11 +33,6 @@ #include <bootm.h> #include <image.h> -#ifndef CONFIG_SYS_BOOTM_LEN -/* use 8MByte as default max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN 0x800000 -#endif - #define MAX_CMDLINE_SIZE SZ_4K #define IH_INITRD_ARCH IH_ARCH_DEFAULT @@ -369,10 +364,12 @@ static int bootm_find_other(struct cmd_tbl *cmdtp, int flag, int argc, * * @comp_type: Compression type being used (IH_COMP_...) * @uncomp_size: Number of bytes uncompressed + * @buf_size: Number of bytes the decompresion buffer was * @ret: errno error code received from compression library * Return: Appropriate BOOTM_ERR_ error code */ -static int handle_decomp_error(int comp_type, size_t uncomp_size, int ret) +static int handle_decomp_error(int comp_type, size_t uncomp_size, + size_t buf_size, int ret) { const char *name = genimg_get_comp_name(comp_type); @@ -380,7 +377,7 @@ static int handle_decomp_error(int comp_type, size_t uncomp_size, int ret) if (ret == -ENOSYS) return BOOTM_ERR_UNIMPLEMENTED; - if (uncomp_size >= CONFIG_SYS_BOOTM_LEN) + if (uncomp_size >= buf_size) printf("Image too large: increase CONFIG_SYS_BOOTM_LEN\n"); else printf("%s: uncompress error %d\n", name, ret); @@ -420,7 +417,8 @@ static int bootm_load_os(bootm_headers_t *images, int boot_progress) load_buf, image_buf, image_len, CONFIG_SYS_BOOTM_LEN, &load_end); if (err) { - err = handle_decomp_error(os.comp, load_end - load, err); + err = handle_decomp_error(os.comp, load_end - load, + CONFIG_SYS_BOOTM_LEN, err); bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); return err; } @@ -1006,7 +1004,7 @@ static int bootm_host_load_image(const void *fit, int req_image_type, ulong data, len; bootm_headers_t images; int noffset; - ulong load_end; + ulong load_end, buf_size; uint8_t image_type; uint8_t imape_comp; void *load_buf; @@ -1032,14 +1030,14 @@ static int bootm_host_load_image(const void *fit, int req_image_type, } /* Allow the image to expand by a factor of 4, should be safe */ - load_buf = malloc((1 << 20) + len * 4); + buf_size = (1 << 20) + len * 4; + load_buf = malloc(buf_size); ret = image_decomp(imape_comp, 0, data, image_type, load_buf, - (void *)data, len, CONFIG_SYS_BOOTM_LEN, - &load_end); + (void *)data, len, buf_size, &load_end); free(load_buf); if (ret) { - ret = handle_decomp_error(imape_comp, load_end - 0, ret); + ret = handle_decomp_error(imape_comp, load_end - 0, buf_size, ret); if (ret != BOOTM_ERR_UNIMPLEMENTED) return ret; } diff --git a/cmd/Kconfig b/cmd/Kconfig index dea3729d13..d5f842136c 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -335,6 +335,16 @@ config BOOTM_VXWORKS help Support booting VxWorks images via the bootm command. +config SYS_BOOTM_LEN + hex "Maximum size of a decompresed OS image" + depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ + default 0x4000000 if PPC || ARM64 + default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7 + default 0x800000 + help + This is the maximum size of the buffer that is used to decompress the OS + image in to, if passing a compressed image to bootm/booti/bootz. + config CMD_BOOTEFI bool "bootefi" depends on EFI_LOADER @@ -1298,6 +1308,10 @@ config CMD_ONENAND and erasing blocks. It allso provides a way to show and change bad blocks, and test the device. +config USE_ONENAND_BOARD_INIT + bool "Call onenand_board_init() in the onenand command" + depends on CMD_ONENAND + config CMD_OSD bool "osd" help @@ -1737,6 +1751,15 @@ config NFS_TIMEOUT "ERROR: Cannot umount" in nfs command, try longer timeout such as 10000. +config SYS_DISABLE_AUTOLOAD + bool "Disable automatically loading files over the network" + depends on CMD_BOOTP || CMD_DHCP || CMD_NFS || CMD_RARP + help + Typically, commands such as "dhcp" will attempt to automatically + load a file from the network, once the initial network configuration + is complete. Enable this option to disable this behavior and instead + require files to be loaded over the network by subsequent commands. + config CMD_MII bool "mii" imply CMD_MDIO diff --git a/common/Kconfig b/common/Kconfig index 84db2e43f1..e7914ca750 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -83,14 +83,17 @@ config LOGLEVEL config SPL_LOGLEVEL int + depends on SPL default LOGLEVEL config TPL_LOGLEVEL int + depends on TPL default LOGLEVEL config VPL_LOGLEVEL int "loglevel for VPL" + depends on VPL default LOGLEVEL help All Messages with a loglevel smaller than the console loglevel will @@ -271,15 +274,6 @@ config LOG if LOG -config VPL_LOG - bool "Enable logging support in VPL" - depends on LOG - help - This enables support for logging of status and debug messages. These - can be displayed on the console, recorded in a memory buffer, or - discarded if not needed. Logging supports various categories and - levels of severity. - config LOG_MAX_LEVEL int "Maximum log level to record" default 6 @@ -365,7 +359,7 @@ config LOG_SYSLOG config SPL_LOG bool "Enable logging support in SPL" - depends on LOG + depends on LOG && SPL help This enables support for logging of status and debug messages. These can be displayed on the console, recorded in a memory buffer, or @@ -408,7 +402,7 @@ endif config TPL_LOG bool "Enable logging support in TPL" - depends on LOG + depends on LOG && TPL help This enables support for logging of status and debug messages. These can be displayed on the console, recorded in a memory buffer, or @@ -451,7 +445,7 @@ endif config VPL_LOG bool "Enable logging support in VPL" - depends on LOG + depends on LOG && VPL help This enables support for logging of status and debug messages. These can be displayed on the console, recorded in a memory buffer, or diff --git a/common/Makefile b/common/Makefile index 75c24e3249..2ed8672c3a 100644 --- a/common/Makefile +++ b/common/Makefile @@ -23,10 +23,9 @@ obj-$(CONFIG_MII) += miiphyutil.o obj-$(CONFIG_CMD_MII) += miiphyutil.o obj-$(CONFIG_PHYLIB) += miiphyutil.o -ifdef CONFIG_USB -obj-y += usb.o usb_hub.o +obj-$(CONFIG_USB_HOST) += usb.o usb_hub.o +obj-$(CONFIG_USB_GADGET) += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o -endif # others obj-$(CONFIG_CONSOLE_MUX) += iomux.o @@ -57,13 +56,9 @@ endif obj-$(CONFIG_SPL_NET) += miiphyutil.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o -ifdef CONFIG_SPL_USB_HOST -obj-y += usb.o -obj-y += usb_hub.o +obj-$(CONFIG_SPL_USB_HOST) += usb.o usb_hub.o obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o -else -obj-$(CONFIG_USB_MUSB_HOST) += usb.o -endif +obj-$(CONFIG_SPL_MUSB_NEW) += usb.o endif # CONFIG_SPL_BUILD #others diff --git a/common/board_f.c b/common/board_f.c index a5666ca77c..5c86faeb21 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -400,13 +400,9 @@ static int reserve_video(void) ((unsigned long)gd->relocaddr - addr) >> 10, addr); gd->relocaddr = addr; #elif defined(CONFIG_LCD) -# ifdef CONFIG_FB_ADDR - gd->fb_base = CONFIG_FB_ADDR; -# else /* reserve memory for LCD display (always full pages) */ gd->relocaddr = lcd_setmem(gd->relocaddr); gd->fb_base = gd->relocaddr; -# endif /* CONFIG_FB_ADDR */ #endif return 0; diff --git a/common/init/board_init.c b/common/init/board_init.c index eab5ee1395..6a55026177 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -78,9 +78,11 @@ __weak void board_init_f_init_stack_protection(void) ulong board_init_f_alloc_reserve(ulong top) { /* Reserve early malloc arena */ +#ifndef CONFIG_MALLOC_F_ADDR #if CONFIG_VAL(SYS_MALLOC_F_LEN) top -= CONFIG_VAL(SYS_MALLOC_F_LEN); #endif +#endif /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */ top = rounddown(top-sizeof(struct global_data), 16); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 152569ee43..931619c366 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -82,6 +82,7 @@ config SPL_MAX_SIZE default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616 default 0x7000 if RCAR_GEN3 default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0 + default 0x10000 if ASPEED_AST2600 default 0x0 help Maximum size of the SPL image (text, data, rodata, and linker lists @@ -234,6 +235,18 @@ config SPL_HANDOFF config SPL_LDSCRIPT string "Linker script for the SPL stage" + default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if ARCH_SUNXI && !MACH_SUNIV && !ARM64 + default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK + default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 + default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if ARCH_AT91 && CPU_ARM926EJS + default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if ARCH_AT91 && CPU_V7A + default "arch/arm/mach-omap2/u-boot-spl.lds" if ARCH_MX6 || ARCH_OMAP2PLUS || (ARCH_K3 && !ARM64) + default "arch/arm/mach-zynq/u-boot-spl.lds" if ARCH_ZYNQ + default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 + default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds" if ARCH_DAVINCI default "arch/\$(ARCH)/cpu/u-boot-spl.lds" help The SPL stage will usually require a different linker-script @@ -1318,6 +1331,13 @@ config SPL_USB_STORAGE config options. This enables loading from USB using a configured device. +config SYS_USB_FAT_BOOT_PARTITION + int "Partition on USB to use to load U-Boot from" + depends on SPL_USB_STORAGE + default 1 + help + Partition on the USB storage device to load U-Boot from + config SPL_USB_GADGET bool "Suppport USB Gadget drivers" help diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index cf3f7ef4c0..3eef2f8d68 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -71,6 +71,16 @@ unsigned int __weak spl_spi_get_uboot_offs(struct spi_flash *flash) return CONFIG_SYS_SPI_U_BOOT_OFFS; } +u32 __weak spl_spi_boot_bus(void) +{ + return CONFIG_SF_DEFAULT_BUS; +} + +u32 __weak spl_spi_boot_cs(void) +{ + return CONFIG_SF_DEFAULT_CS; +} + /* * The main entry for SPI booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image @@ -83,15 +93,15 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, unsigned int payload_offs; struct spi_flash *flash; struct image_header *header; + unsigned int sf_bus = spl_spi_boot_bus(); + unsigned int sf_cs = spl_spi_boot_cs(); /* * Load U-Boot image from SPI flash into RAM * In DM mode: defaults speed and mode will be * taken from DT when available */ - - flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, - CONFIG_SF_DEFAULT_CS, + flash = spi_flash_probe(sf_bus, sf_cs, CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); if (!flash) { diff --git a/common/usb.c b/common/usb.c index aad13fd9c5..6fcf1e8428 100644 --- a/common/usb.c +++ b/common/usb.c @@ -49,10 +49,6 @@ char usb_started; /* flag for the started/stopped USB status */ static struct usb_device usb_dev[USB_MAX_DEVICE]; static int dev_index; -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - /*************************************************************************** * Init USB Device */ diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 026668b0bd..26a921279b 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index e0db1e6738..b5802818ec 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index a78cbfb139..de4f6311f2 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index da3532ccc4..ebb3a02b82 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index 0563a5188e..c8802435b4 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 4993cf7d2d..f449641245 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index 0db97ae841..67b47f51f1 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index 91d29e4446..e02d67da5e 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index 893f2e627d..317a1e695d 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 7d9c688171..be5be9ae2f 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 6cc2d5b647..053ba13765 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 19b644613a..36f9bf8b32 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index 794d6668d2..315c52f344 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 1027c5e3bf..49eb018695 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 560248dc5b..62668df01e 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PBSIZE=1024 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index 42cb24e88e..1a16155584 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index d4692f8184..3627e4dd3a 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index dbafdd5bd8..41ed46a7b5 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index ff6a4e8b37..44a3901e22 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 4ab888f59e..858fc5bbfd 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 2a79962784..c7fd5a07a7 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index 5eeed2d2f3..a14bf427ad 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index b3e6277a7e..3ed703a7a7 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 3420934caf..fe6ffca43c 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 901a15d506..28d51eaa9d 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y @@ -42,6 +43,7 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y +CONFIG_SYS_UNIFY_CACHE=y CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 0bce9d8f42..c59359b820 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set @@ -41,6 +42,7 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y +CONFIG_SYS_UNIFY_CACHE=y CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index efc7733b44..ae4add504b 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -43,6 +44,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y +CONFIG_SYS_UNIFY_CACHE=y CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 920a86fa9a..aead0f45bd 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="-> " CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y @@ -43,6 +44,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_DM_ETH=y CONFIG_MCFFEC=y +CONFIG_SYS_UNIFY_CACHE=y CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 236be1628c..6adba431ef 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_PROMPT="S3K> " CONFIG_SYS_PBSIZE=278 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_LOADB is not set diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index f2dd5d3f8c..6fa89aad36 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -10,6 +10,8 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_PCIE1=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 55acf63ae1..82776497a5 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -10,6 +10,8 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_PCIE1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 4bd0b1a27b..c21ed57dc3 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -10,7 +10,9 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y CONFIG_TARGET_MPC8548CDS_LEGACY=y +CONFIG_PCIE1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index c88cfd6aa3..1584778dc7 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -8,6 +8,7 @@ CONFIG_AHCI=y CONFIG_SPL_STACK=0x8000 CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 429baf3faf..eb3e798800 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index a426729700..2e6d5dd460 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index e7cf38ac7d..ba976f8f5f 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 494edf0625..720e9e5df4 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index cec563e0f9..7a50cd7f90 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xD0001000 +CONFIG_TPL_TEXT_BASE=0xD0000000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,12 +14,17 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xD0001000 +CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -35,7 +40,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000 CONFIG_SPL_RELOC_STACK=0xd003fff0 CONFIG_TPL_GD_ADDR=0xd002c000 -CONFIG_TPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_TPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_TPL_RELOC_STACK=0xd0030000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 @@ -66,16 +71,20 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index f4209305c1..5030afd098 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -8,11 +8,16 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -41,10 +46,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 8dd667ff48..dd04cff4a4 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -1,23 +1,29 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -30,7 +36,7 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 @@ -62,10 +68,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 16bb174e98..46613cce3b 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -15,6 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -33,7 +38,7 @@ CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 @@ -65,10 +70,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 15c7e993b9..49acfd2d38 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xD0001000 +CONFIG_TPL_TEXT_BASE=0xD0000000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,11 +14,16 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xD0001000 +CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -34,7 +39,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000 CONFIG_SPL_RELOC_STACK=0xd003fff0 CONFIG_TPL_GD_ADDR=0xd002c000 -CONFIG_TPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_TPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_TPL_RELOC_STACK=0xd0030000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 @@ -65,16 +70,20 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index bea23e2d90..89fccd6fc3 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -8,10 +8,15 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -40,10 +45,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index e0d967f8cc..a2786616c8 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -1,22 +1,28 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -29,7 +35,7 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 @@ -61,10 +67,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 92587aa03b..17daecd2ec 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -15,6 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -32,7 +37,7 @@ CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 @@ -64,10 +69,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 8e0c4ed358..6b73bf4341 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xD0001000 +CONFIG_TPL_TEXT_BASE=0xD0000000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,12 +14,17 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xD0001000 +CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -36,7 +41,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000 CONFIG_SPL_RELOC_STACK=0xd003fff0 CONFIG_TPL_GD_ADDR=0xd002c000 -CONFIG_TPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_TPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_TPL_RELOC_STACK=0xd0030000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 @@ -67,16 +72,20 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 3d5e6dd4ea..7a5e057a2c 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -8,11 +8,16 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -42,10 +47,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 0b99fb33ed..ef85d48719 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -1,23 +1,29 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -31,7 +37,7 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 @@ -63,10 +69,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 8a6c44d489..bda32ccbf3 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -15,6 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -34,7 +39,7 @@ CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 @@ -66,10 +71,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 6b249dc7ee..50667e56f6 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xD0001000 +CONFIG_TPL_TEXT_BASE=0xD0000000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,11 +14,16 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xD0001000 +CONFIG_TPL_SYS_MONITOR_BASE=0xD0000000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -35,7 +40,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000 CONFIG_SPL_RELOC_STACK=0xd003fff0 CONFIG_TPL_GD_ADDR=0xd002c000 -CONFIG_TPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_TPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_TPL_RELOC_STACK=0xd0030000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xd0034000 @@ -66,16 +71,20 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_TPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index ec11f8b53d..c13369efe7 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -8,10 +8,15 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -41,10 +46,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_COMMON_INIT_DDR=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 7b9aec1882..691d6e33da 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -1,22 +1,28 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr" @@ -30,7 +36,7 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 @@ -62,10 +68,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 13c836d106..a630e961ee 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -15,6 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -33,7 +38,7 @@ CONFIG_SPL_SPI_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 @@ -65,10 +70,13 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SPL_COMMON_INIT_DDR=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 18d9da8535..8288e858ed 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,13 +14,18 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -36,7 +41,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000 CONFIG_SPL_RELOC_STACK=0xf8fbfff0 CONFIG_TPL_GD_ADDR=0xf8fac000 -CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 CONFIG_TPL_RELOC_STACK=0xf8fb0000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 @@ -66,14 +71,18 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 @@ -134,5 +143,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index b88ca9404d..b581cb109b 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -1,25 +1,31 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -63,8 +69,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -116,5 +125,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 10fecbbbf1..e8543c6461 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -15,13 +15,18 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -66,8 +71,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -119,5 +127,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index d9f402dbaf..2b9fcb034c 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -9,12 +9,17 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -43,8 +48,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -97,5 +105,6 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 25d5a5b25c..fdb163f49c 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,12 +14,17 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -35,7 +40,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000 CONFIG_SPL_RELOC_STACK=0xf8fbfff0 CONFIG_TPL_GD_ADDR=0xf8fac000 -CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 CONFIG_TPL_RELOC_STACK=0xf8fb0000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 @@ -65,14 +70,18 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 @@ -133,4 +142,5 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index ca71a90904..7489ad3459 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -1,24 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -62,8 +68,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -115,4 +124,5 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 71994c4b7d..728592f6c3 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -15,12 +15,17 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -65,8 +70,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -118,4 +126,5 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 854def1077..ada7e2d59a 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -9,11 +9,16 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -42,8 +47,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 @@ -96,4 +104,5 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 1c5bb4d5e0..0839286337 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,12 +14,17 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -35,7 +40,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000 CONFIG_SPL_RELOC_STACK=0xf8fbfff0 CONFIG_TPL_GD_ADDR=0xf8fac000 -CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 CONFIG_TPL_RELOC_STACK=0xf8fb0000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 @@ -68,14 +73,18 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x60000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8796 diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 3b86e8ff43..ddd9e335e6 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -1,24 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -65,8 +71,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index b8a46f379f..88365bff62 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -15,12 +15,17 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -68,8 +73,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index a998a6f961..ef31e0970a 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -9,11 +9,16 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -45,8 +50,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=2 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEC001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index bb12b477d3..99f1d26446 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,13 +14,18 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -36,7 +41,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xf8ffe000 CONFIG_SPL_RELOC_STACK=0xf8fffff0 CONFIG_TPL_GD_ADDR=0xf8fac000 -CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 CONFIG_TPL_RELOC_STACK=0xf8fb0000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 @@ -70,14 +75,18 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb) CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 7a60b990fc..856a78fdd1 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -1,25 +1,31 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -67,8 +73,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 9ae632b7cb..b03c17c7e7 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -15,13 +15,18 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -70,8 +75,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 9b3b77f729..c1a5ef9d30 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -9,12 +9,17 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -47,8 +52,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index b341a2aed6..2558596b16 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_SPL_SERIAL=y -CONFIG_TPL_TEXT_BASE=0xF8F81000 +CONFIG_TPL_TEXT_BASE=0xF8F80000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL=y @@ -14,12 +14,17 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_TPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -35,7 +40,7 @@ CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_RELOC_TEXT_BASE=0xf8ffe000 CONFIG_SPL_RELOC_STACK=0xf8fffff0 CONFIG_TPL_GD_ADDR=0xf8fac000 -CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000 +CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000 CONFIG_TPL_RELOC_STACK=0xf8fb0000 CONFIG_TPL_RELOC_MALLOC=y CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000 @@ -69,14 +74,18 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb), CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0xc000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFF800C21 CONFIG_SYS_OR0_PRELIM=0xFFFF8396 diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 1727584636..29cc14700a 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -1,24 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -66,8 +72,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 35a726ec60..3ee43f8da6 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" -CONFIG_SPL_TEXT_BASE=0xf8f81000 +CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -15,12 +15,17 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SPL_SYS_MONITOR_BASE=0xF8F81000 +CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000 CONFIG_SPIFLASH=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y @@ -69,8 +74,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 5f8ba378e7..7af0244078 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -9,11 +9,16 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_FSL_FIXED_MMC_LOCATION=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr" @@ -46,8 +51,11 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_CHIP_SELECTS_PER_CTRL=1 +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xEF001001 CONFIG_SYS_OR0_PRELIM=0xFC000FF7 diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 9389d99256..4c453a7cd9 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -7,6 +7,12 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -46,6 +52,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -91,6 +98,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 31d5814d55..b5f920b013 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -7,6 +7,12 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -46,6 +52,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -86,6 +93,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 7e913c8136..ecf63e59c6 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -8,6 +8,12 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -48,6 +54,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -88,6 +95,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 23165b83f7..e609dfcbf2 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -8,6 +8,12 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -43,6 +49,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -83,6 +90,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 7c5b6d288b..59fdc33ad4 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -7,6 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -44,8 +51,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -94,6 +103,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 41ec73a6be..17aa980518 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -7,6 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -44,8 +51,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -89,6 +98,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index bdbf2e959e..2be600a584 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -8,6 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -46,8 +53,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -91,6 +100,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 953cbd4b0b..f22719558f 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -8,6 +8,13 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -41,8 +48,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -86,6 +95,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index e603f81287..2aba222894 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -7,6 +7,12 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -44,7 +50,9 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -87,6 +95,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 90b4688ea2..9bfb0a88f1 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -8,6 +8,12 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -46,7 +52,9 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -89,6 +97,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 85acd7e427..1d5f00d1c8 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -8,6 +8,12 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -41,7 +47,9 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_LBA48=y CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -84,6 +92,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 6e0bdb2e13..741adc5162 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -7,6 +7,12 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -45,8 +51,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -95,6 +103,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index e040fab7cb..c10c94849e 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -7,6 +7,12 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -44,8 +50,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -89,6 +97,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 1e1a2f8036..111ca1d487 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -8,6 +8,12 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -46,8 +52,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -91,6 +99,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index ec897c3323..fd94afa762 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -8,6 +8,12 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -41,8 +47,10 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_SYS_SPD_BUS_NUM=1 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y @@ -86,6 +94,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 2eb985823e..d44f062558 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -12,6 +12,14 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -122,6 +130,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 9daf7fd5ef..fdff32c2d2 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -13,6 +13,13 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -117,6 +124,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index ee9292a4fb..fdfbdd2ec0 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,6 +15,13 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -120,6 +127,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 0f7e062380..9f1599fb63 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -8,6 +8,12 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -93,6 +99,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 91a83007ce..aca69b3216 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -11,6 +11,15 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -120,6 +129,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 32fed7a33a..fcf530d44f 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -12,6 +12,14 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -115,6 +123,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 638ed7147a..3e0239edf3 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x30001000 +CONFIG_SYS_TEXT_BASE=0x30000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -14,6 +14,14 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -118,6 +126,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index f05e66e0d3..3063157a7f 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -7,6 +7,13 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -91,6 +98,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index b71659a660..0a83ed19b1 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -1,11 +1,25 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x140000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -13,11 +27,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -72,6 +81,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -125,6 +135,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 1b8ef0cb36..2f12b4e609 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -1,11 +1,25 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -13,12 +27,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -72,6 +80,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -120,6 +129,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index d9822bab3f..2fc4e16cfe 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -1,8 +1,19 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DEFAULT_DEVICE_TREE="t2080qds" +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_NXP_ESBC=y +CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000 +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -10,9 +21,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_SYS_MALLOC_F is not set CONFIG_MP=y CONFIG_FIT=y @@ -47,6 +55,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 @@ -94,9 +103,9 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index bcef31a665..7adf3af6b8 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -7,13 +7,6 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -21,6 +14,21 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -75,6 +83,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -123,6 +132,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 6158be76fe..2228c64d10 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -2,6 +2,18 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" +CONFIG_ENV_ADDR=0xFFE20000 +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SRIO_PCIE_BOOT_SLAVE=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -9,11 +21,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_SRIO_PCIE_BOOT_SLAVE=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -45,6 +52,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -87,6 +95,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index fd658454c4..fbfbab84a1 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -3,6 +3,17 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" +CONFIG_ENV_ADDR=0xEFF20000 +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080QDS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" @@ -10,10 +21,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T2080QDS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -48,6 +55,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y @@ -96,6 +104,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 9e8e3ea8b5..b84d653d49 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -1,20 +1,29 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -74,6 +83,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -128,6 +138,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index b6a0b857a7..21f76bd4b0 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -1,21 +1,29 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -74,6 +82,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -123,6 +132,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index b0f0d165cd..bcc60b7ade 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -7,10 +7,6 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -18,6 +14,18 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -77,6 +85,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -126,6 +135,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 66d043309b..8df5b3db29 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -3,14 +3,21 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -50,6 +57,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -98,6 +106,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index feba8e54b5..a8e020ae68 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -1,21 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -75,6 +84,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -130,6 +140,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 0495786bc5..3baf69a088 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -1,22 +1,30 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -75,6 +83,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -125,6 +134,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index bb7c711d55..9d8feac9ec 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 @@ -7,10 +7,6 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y @@ -18,7 +14,19 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -78,6 +86,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -128,6 +137,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index 56b174fad7..e4eaa75d30 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -3,15 +3,22 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y CONFIG_T2080RDB_REV_D=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y @@ -51,6 +58,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133330000 @@ -100,6 +108,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index fb35c83f1b..a2062b4b3d 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -1,21 +1,29 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -66,6 +74,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 @@ -110,6 +119,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 4f19024a6b..c3216474c3 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -3,14 +3,21 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" -CONFIG_VID=y -CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" -CONFIG_VOL_MONITOR_IR36021_READ=y -CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_PCIE4=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" +CONFIG_VOL_MONITOR_IR36021_READ=y +CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -42,6 +49,7 @@ CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" CONFIG_DM=y +CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 @@ -86,6 +94,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_EHCI_FSL=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 09608dd1cc..c9d22534d5 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/a3y17lte_defconfig b/configs/a3y17lte_defconfig index 67eb7aff1f..9c0427236b 100644 --- a/configs/a3y17lte_defconfig +++ b/configs/a3y17lte_defconfig @@ -20,6 +20,7 @@ CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/a5y17lte_defconfig b/configs/a5y17lte_defconfig index 44915ea534..ea0773e7a2 100644 --- a/configs/a5y17lte_defconfig +++ b/configs/a5y17lte_defconfig @@ -20,6 +20,7 @@ CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig index 7d8e7649f2..afa0c24b68 100644 --- a/configs/a64-olinuxino-emmc_defconfig +++ b/configs/a64-olinuxino-emmc_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 06f51a8f8d..ccb5abc984 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/a7y17lte_defconfig b/configs/a7y17lte_defconfig index 58486f6a57..952c72b760 100644 --- a/configs/a7y17lte_defconfig +++ b/configs/a7y17lte_defconfig @@ -20,6 +20,7 @@ CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index fcfc7b3fe2..b7ea28b178 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index cfd857c183..fd89ea14e9 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 36345fbfdc..2a0c1abf6e 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 01883850f9..e85921bcb3 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 477329fa67..cab5a387e5 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index eba12a8f0d..a5cc757182 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 6ade12b740..dbe5db278f 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 2be91815a8..c9dc1d10f8 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 0ec4409175..bbb987c5ed 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index b5ba2ccda5..9fe5ac4a16 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -36,6 +36,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set @@ -54,6 +55,7 @@ CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index c7dbd3c570..b5801094e8 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00080000 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -63,6 +64,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y CONFIG_CLK_TI_CTRL=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 00e80a89de..1f28d50a1b 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set @@ -53,6 +54,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y CONFIG_DFU_TFTP=y @@ -76,7 +78,6 @@ CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 -# CONFIG_SPL_NAND_AM33XX_BCH is not set CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 0dc4bb25be..56da3720d9 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -48,6 +48,7 @@ CONFIG_SPL_POWER=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y @@ -59,6 +60,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index ef0a09877c..bb03e487f8 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y # CONFIG_SPL_YMODEM_SUPPORT is not set CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y @@ -51,6 +52,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y CONFIG_DFU_MMC=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index d7ea5a31cd..ac451026b0 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y @@ -52,6 +53,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y CONFIG_DFU_MMC=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 77593e3e3d..070674651f 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 97a361ce4d..595e7301cf 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -47,6 +47,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index 2c6fc5496e..d5cd182acb 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -51,6 +51,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index a154a34255..e9e89f627e 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -50,6 +50,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 1338190e9f..f2385e3d70 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y @@ -68,6 +69,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 80ad268fe1..18be57a2fe 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -54,8 +54,6 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y -CONFIG_SPL_POWER_LEGACY=y -CONFIG_SPL_POWER_I2C=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index d82c66572c..249e6702dd 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -45,6 +45,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y CONFIG_CMD_SPL=y @@ -107,6 +108,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 3320917730..aa0b466d95 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -97,6 +98,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 014a3830df..1c37b63540 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -106,6 +107,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PALMAS_POWER=y CONFIG_SCSI_AHCI_PLAT=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 7ebf366521..2c0bd4d2e1 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_MMC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 2e340cd6f4..deafb92fc1 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_R5_EVM=y CONFIG_DM_GPIO=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 49bfc006dd..0f547526fe 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -63,6 +63,7 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 2d8add2fbd..5232b97970 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -64,6 +64,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 05a6a9219e..7507128c11 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -56,6 +56,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 37e04483db..e7e2226473 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -56,6 +56,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig index fc0c5432db..6e63f0e880 100644 --- a/configs/am65x_hs_evm_r5_defconfig +++ b/configs/am65x_hs_evm_r5_defconfig @@ -60,6 +60,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index 0e173c28c1..72f97cee4d 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 2d9c0ae18e..39ee46dbec 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_APALIS_TK1=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -58,6 +59,7 @@ CONFIG_SYS_I2C_TEGRA=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y CONFIG_E1000=y +CONFIG_E1000_NO_NVM=y CONFIG_PCI=y CONFIG_PCI_TEGRA=y CONFIG_DM_PMIC=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 89e9971ea3..f9721796db 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -79,6 +79,7 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DM_I2C=y @@ -104,6 +105,7 @@ CONFIG_DM_SCSI=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_GADGET=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 2a8d3c6e0a..f5d958646f 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -50,6 +50,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_E1000=y +CONFIG_E1000_NO_NVM=y CONFIG_PCI=y CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index c4fd803456..4ba09334d4 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -8,6 +8,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_NET is not set CONFIG_APPLE_SPI_KEYB=y # CONFIG_MMC is not set diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 7a3e690ed6..26bcb00ff5 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -51,6 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red),-(ubi-nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 6bc78b7732..682903082c 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -51,6 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red),-(ubi-nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index 9947d1d4c6..62b467ea30 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -65,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 8e54f1b133..a5ccce1eae 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -65,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 1badceeb2c..d3706d158b 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -63,3 +63,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index 8b2f27a406..d479d76c79 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -65,4 +65,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index e5350cfd6f..96c44e9a16 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -65,4 +65,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index 3557c4e57a..16de519511 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -63,4 +63,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index aa69b0f97a..e73ff8861b 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -68,4 +68,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index aa69b0f97a..e73ff8861b 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -68,4 +68,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index f88ea5cc3d..184431640e 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -66,4 +66,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index b93eeaa214..7b97581392 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -68,4 +68,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index eb2e13ccc0..2c354f3b5b 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -69,4 +69,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_ATMEL_LCD_BGR555=y diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index 818e630ea2..ee4de9b67d 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -62,3 +62,6 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index 118d778d4c..4a47ad1286 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -62,3 +62,6 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index bf667606a2..0e3d0b1314 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -60,3 +60,6 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index d175575f79..add019c10a 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -66,3 +66,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index 2ea5bbd034..72a21c3da9 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -65,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 304ee157bb..03b029cee8 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -65,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index a93ae955a5..1ae1b28fee 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -65,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index 4c51e7a335..77ad4b9fda 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -63,3 +63,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 18ec990fe3..5ffa294482 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -48,9 +48,7 @@ CONFIG_AT91_GPIO=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 6e36b60ce0..da37fb507a 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -55,9 +55,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index a32eb130f1..9d581734f9 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -54,9 +54,7 @@ CONFIG_AT91_GPIO=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index 9947d1d4c6..62b467ea30 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -65,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index 8e54f1b133..a5ccce1eae 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -65,3 +65,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 1badceeb2c..d3706d158b 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -63,3 +63,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9260" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 450b2830e5..0574ee95e4 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -6,8 +6,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_ZYNQ_MAC_IN_EEPROM=y @@ -44,6 +42,7 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SYS_SPL_ARGS_ADDR=0x8000000 CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2073 +CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index b61151129f..a5f60bd8d0 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -7,7 +7,6 @@ CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 CONFIG_SYS_MALLOC_LEN=0x460000 CONFIG_TARGET_TAURUS=y @@ -17,6 +16,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index efad458720..c744b38cc4 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -21,6 +21,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=278 +CONFIG_SYS_BOOTM_LEN=0x8000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 6440765576..29affdc5e9 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -21,6 +21,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=278 +CONFIG_SYS_BOOTM_LEN=0x8000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y @@ -62,5 +63,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 955a60ddc3..290e9c17e2 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 08f7683233..e6b8f0f8a3 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL_STACK=0x8000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index 0fb1bda1c6..a68742e9d6 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 5d1d10a091..36aa80a09b 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 80602fbbff..d1a467dfe7 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -55,6 +55,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y CONFIG_SPI=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 2804220210..c44e6ba4ff 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="U-Boot>" CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=536 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index 0382034a47..bab2c76efb 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_PROMPT="U-Boot>" CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=536 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig index af9e0c742c..c61fbe1848 100644 --- a/configs/bcm947622_defconfig +++ b/configs/bcm947622_defconfig @@ -16,6 +16,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index 3bc4ca3ef6..424eca7946 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -25,6 +25,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=24 CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/bcm968360bg_ram_defconfig b/configs/bcm968360bg_ram_defconfig index d327dc68b1..7f9093c6f6 100644 --- a/configs/bcm968360bg_ram_defconfig +++ b/configs/bcm968360bg_ram_defconfig @@ -23,6 +23,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=24 CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig index ef5ae44345..a8c7ffa748 100644 --- a/configs/bcm968580xref_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -23,6 +23,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=24 CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 9446f8454c..9181b9e477 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -29,6 +29,7 @@ CONFIG_SYS_PROMPT="u-boot> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1049 # CONFIG_SYS_XTRACE is not set +CONFIG_SYS_BOOTM_LEN=0x1800000 CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_MMC=y diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index 6453a72a7d..2c440e44f5 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -10,6 +10,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x118000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index f8ab914358..b0d2105db6 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -13,7 +13,6 @@ CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xe0001000 -CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y @@ -41,6 +40,7 @@ CONFIG_SYS_PROMPT="antminer> " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2075 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x3c00000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_DM is not set # CONFIG_CMD_FLASH is not set @@ -56,6 +56,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_PXE=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 838090e303..0f8955dbbf 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index 691e47c550..2be57d2d1e 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -21,6 +21,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index 3c4aac93d8..524564355f 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -8,12 +8,12 @@ CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_TARGET_BOSTON=y -CONFIG_SYS_LITTLE_ENDIAN=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -22,6 +22,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index 30c5356c01..7bb4e692d6 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index f1253e6a51..8ae2f235b1 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -8,13 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_TARGET_BOSTON=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32_R6=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -23,6 +23,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index a7c67805ab..4a41e6b5cc 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index 326c757057..0670ffabbb 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -8,13 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_TARGET_BOSTON=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64_R2=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -23,6 +23,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index d31b92dc3c..bf7f709524 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -22,6 +22,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index 72b3649d4a..e1d46d3060 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -8,13 +8,13 @@ CONFIG_DEFAULT_DEVICE_TREE="img,boston" CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_TARGET_BOSTON=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64_R6=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -23,6 +23,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_PROMPT="boston # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_ELF is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 488167e27f..f088e0bdc0 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -61,6 +62,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index dce6bebd81..7f961ae473 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -61,6 +62,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 41dd24fedd..5d6dfbd5c4 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -70,6 +71,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index db87b579ee..e2c36e13ad 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y # CONFIG_SPL_SYS_THUMB_BUILD is not set CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_MX6=y -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_LEN=0xa00000 CONFIG_SYS_MALLOC_F_LEN=0x1000 @@ -10,6 +9,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x20000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -57,6 +57,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index 3134d3b4b6..0a906ca955 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set @@ -72,6 +73,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index c39389451f..c38393410f 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -63,6 +63,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_MAY_FAIL=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index 0daff7d150..8dc928a927 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -18,6 +18,7 @@ CONFIG_BOOTARGS="console=ttyOWL5,115200n8" CONFIG_SYS_PROMPT="U-Boot => " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1051 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_CACHE=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index f55848ab2c..35f8d9c781 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y +CONFIG_TEGRA_GPU=y CONFIG_ARMV7_PSCI_0_1=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 17219969f6..5dea71980b 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -49,6 +49,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_CLK=y CONFIG_CMD_DM=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 1d4256e37b..9c3d26a36e 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -45,6 +45,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y CONFIG_SPI=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 849d751f08..0556906142 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MISC=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 862b37d0fb..dad3b36b99 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_CRC32 is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 84fe5be19d..938bc28a1d 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -102,6 +102,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 693f119b79..60c50e75be 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -87,6 +87,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index a0f15f6e7b..35d546e631 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_CRC32 is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 669d6f570b..6f88002f96 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -103,6 +103,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index f735f84d54..b645cba907 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -70,6 +70,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 1bcf9ce61b..fa3641e42f 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -60,6 +60,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 513e5f85e9..60fc528a8c 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_CRC32 is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 8ee114d0a0..56a0d6c8a8 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -62,6 +62,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 13aa3e2e63..1e1091fa7e 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -80,6 +80,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 7fc505ee4e..e6f03faa87 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_CRC32 is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index c909d316a3..870843ada5 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -53,6 +53,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_RTL8169=y diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig index 983642dac5..07848a5933 100644 --- a/configs/ci20_mmc_defconfig +++ b/configs/ci20_mmc_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1c CONFIG_SPL_MMC_TINY=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DM=y CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 075d8678c8..bf670dbae6 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index bec36beb85..1ee0c66375 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -50,6 +50,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_MIN_ENTRIES=128 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index a45c02061e..baafe3c58c 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -26,6 +26,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -47,6 +48,8 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 16e619b38a..9bf78788e4 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y @@ -75,6 +76,7 @@ CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y # CONFIG_DWC_AHSATA_AHCI is not set +CONFIG_LBA48=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index 0c2e8a35ef..f1b4b622cb 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -46,6 +46,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand" diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 30afd5e7d0..c0dc70312a 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -62,6 +62,7 @@ CONFIG_CMD_NAND=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 750b03b74d..a4225d862b 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -55,6 +55,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 44e2ff0940..0bdd088b1e 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -102,6 +102,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_GADGET=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index f56064d34d..15dae6b3db 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index d92756fb16..9dbe6280dd 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -62,6 +62,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig index 170b766089..36eab571ea 100644 --- a/configs/comtrend_ar5315u_ram_defconfig +++ b/configs/comtrend_ar5315u_ram_defconfig @@ -72,3 +72,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 599fda481a..68969c0413 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -73,3 +73,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index b1ad57b5a5..cb2caf4543 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -67,4 +67,6 @@ CONFIG_BCM6345_SERIAL=y CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y CONFIG_WDT_BCM6345=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index d07895de9b..138d3c84ba 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -72,3 +72,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index ca370e66a3..b7174ff5ee 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -69,3 +69,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index c41b83121e..8b6957da16 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -62,6 +62,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 84ba5cadfe..286abe2f82 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -58,6 +58,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 3bd099e723..a42fc3974a 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -58,6 +58,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set CONFIG_SOUND=y CONFIG_SOUND_I8254=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 792d35eec5..fcd48148f1 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -52,6 +52,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set CONFIG_SOUND=y CONFIG_SOUND_I8254=y diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig index 49a651aba2..ba5cf0308f 100644 --- a/configs/corstone1000_defconfig +++ b/configs/corstone1000_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=512 # CONFIG_CMD_CONSOLE is not set CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_XIMG is not set CONFIG_CMD_LOADM=y # CONFIG_CMD_LOADS is not set diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig index 3edc532e31..1471deb0a9 100644 --- a/configs/cortina_presidio-asic-base_defconfig +++ b/configs/cortina_presidio-asic-base_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_PROMPT="G3#" CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0xc00000 CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/cortina_presidio-asic-emmc_defconfig b/configs/cortina_presidio-asic-emmc_defconfig index becb1beb1f..456f26ced3 100644 --- a/configs/cortina_presidio-asic-emmc_defconfig +++ b/configs/cortina_presidio-asic-emmc_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_PROMPT="G3#" CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0xc00000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_WDT=y diff --git a/configs/cortina_presidio-asic-pnand_defconfig b/configs/cortina_presidio-asic-pnand_defconfig index 842ec9fa92..be3e6a9bd1 100644 --- a/configs/cortina_presidio-asic-pnand_defconfig +++ b/configs/cortina_presidio-asic-pnand_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_PROMPT="G3#" CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0xc00000 CONFIG_CMD_MTD=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 09a6e4bc00..7ee0cb746e 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -48,6 +48,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index addaf3b7f7..fdd0d2badb 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -53,6 +53,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y CONFIG_SOUND=y diff --git a/configs/crs305-1g-4s-bit_defconfig b/configs/crs305-1g-4s-bit_defconfig index 01e784efa8..1b46ab4bf9 100644 --- a/configs/crs305-1g-4s-bit_defconfig +++ b/configs/crs305-1g-4s-bit_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig index 98e10d509d..a7a3ffe481 100644 --- a/configs/crs305-1g-4s_defconfig +++ b/configs/crs305-1g-4s_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs326-24g-2s-bit_defconfig b/configs/crs326-24g-2s-bit_defconfig index dd04bd18a1..70f71de6ae 100644 --- a/configs/crs326-24g-2s-bit_defconfig +++ b/configs/crs326-24g-2s-bit_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs326-24g-2s_defconfig b/configs/crs326-24g-2s_defconfig index 8f7b839460..5991b62923 100644 --- a/configs/crs326-24g-2s_defconfig +++ b/configs/crs326-24g-2s_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs328-4c-20s-4s-bit_defconfig b/configs/crs328-4c-20s-4s-bit_defconfig index 68a47fc7c2..434e9fb90f 100644 --- a/configs/crs328-4c-20s-4s-bit_defconfig +++ b/configs/crs328-4c-20s-4s-bit_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/crs328-4c-20s-4s_defconfig b/configs/crs328-4c-20s-4s_defconfig index fbf8101363..8e08cceaac 100644 --- a/configs/crs328-4c-20s-4s_defconfig +++ b/configs/crs328-4c-20s-4s_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=96 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig index 223a775387..7437d4b4b9 100644 --- a/configs/cubieboard7_defconfig +++ b/configs/cubieboard7_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTARGS="console=ttyOWL3,115200n8" CONFIG_SYS_PROMPT="U-Boot => " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1051 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_MMC=y CONFIG_MMC_OWL=y CONFIG_PHY_REALTEK=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 4eb74f759f..bbafd57727 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -54,6 +55,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index de2d709a7a..d734829858 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -110,6 +110,7 @@ CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_DA8XX=y CONFIG_USB_MUSB_PIO_ONLY=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 88ef772d9d..8f6b8b9702 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -88,6 +88,7 @@ CONFIG_DAVINCI_SPI=y CONFIG_USB=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_DA8XX=y CONFIG_USB_MUSB_PIO_ONLY=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 052ef30703..95b41ef32b 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -113,6 +113,7 @@ CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_DA8XX=y CONFIG_USB_MUSB_PIO_ONLY=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 4fe0d3ec24..49c616852b 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -61,6 +61,7 @@ CONFIG_NET_RETRY_COUNT=50 CONFIG_SPL_OF_TRANSLATE=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig index 309545be53..ae1179a116 100644 --- a/configs/deneb_defconfig +++ b/configs/deneb_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2073 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 5290ac5e82..eae073d76e 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y @@ -85,4 +86,7 @@ CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="lpc32xx-ohci" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 +CONFIG_USB_OHCI_LPC32XX=y CONFIG_OF_LIBFDT=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index a5e9f614df..ac30794478 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -69,11 +69,9 @@ CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_OF_TRANSLATE=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_TWL4030_LED=y CONFIG_MMC_OMAP_HS=y -CONFIG_DM_I2C=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index 177764ef80..35e2c1a326 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -56,6 +56,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_NUVOTON_NCT6102D=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index a659e996b5..051816f719 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -67,7 +67,9 @@ CONFIG_ETHPRIME="FEC" CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 585f44d85d..242cc36fce 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -50,6 +51,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 3cb09ea4f7..6f99cdd44b 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index aae84dc6ad..bd3ce11b79 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -130,6 +130,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 51ffd2779c..63b8f2b6fe 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -124,6 +124,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 34dcdede92..cd4b8bbce0 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -113,6 +113,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y +CONFIG_PALMAS_POWER=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index f7bb01f3bf..c137fc72e0 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -79,6 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 80be9b853c..d6b55636ba 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index aeea352e25..529d756947 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -48,6 +48,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set diff --git a/configs/durian_defconfig b/configs/durian_defconfig index eccf55f895..27c8e260d9 100644 --- a/configs/durian_defconfig +++ b/configs/durian_defconfig @@ -22,6 +22,7 @@ CONFIG_LAST_STAGE_INIT=y CONFIG_SYS_PROMPT="durian#" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 +CONFIG_SYS_BOOTM_LEN=0x3c00000 # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set CONFIG_CMD_PCI=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index b8906b1bb0..6b7cdbe4b1 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -1,12 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_ORION5X=y -CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_SPL_TEXT_BASE=0xffff0000 @@ -56,6 +56,7 @@ CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x4000 +CONFIG_LBA48=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 42fb89d5b3..83f532d6e5 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -49,6 +49,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set # CONFIG_GZIP is not set CONFIG_EFI=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index eef51e8efc..28aaff69e9 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -49,6 +49,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set # CONFIG_GZIP is not set CONFIG_EFI=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 2f595be1c2..263fe3b7c8 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -55,6 +55,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_PRODUCT_NUM=0x110a diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig index d9272eae16..73121f2f4e 100644 --- a/configs/emlid_neutis_n5_devboard_defconfig +++ b/configs/emlid_neutis_n5_devboard_defconfig @@ -10,4 +10,5 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig index 9128fa086a..34e5b4e743 100644 --- a/configs/espresso7420_defconfig +++ b/configs/espresso7420_defconfig @@ -20,6 +20,7 @@ CONFIG_CONSOLE_MUX=y # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="ESPRESSO7420 # " CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 294a67a7fa..f0b10f0292 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -80,6 +80,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x200000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index da8c0bd9cb..796b71793a 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x27000000 CONFIG_SYS_MALLOC_LEN=0x121000 CONFIG_TARGET_ETHERNUT5=y CONFIG_AT91_EFLASH=y +CONFIG_EFLASH_PROTSECTORS=1 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x21000 CONFIG_ENV_OFFSET=0x3DE000 @@ -37,6 +38,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_RARP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 9d2c4f81c5..e7d93ec48b 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -20,6 +20,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -35,6 +36,7 @@ CONFIG_CLK=y CONFIG_ASPEED_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y CONFIG_PHY_REALTEK=y diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index a91a53da4f..d07d3c41fe 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_POSITION_INDEPENDENT=y CONFIG_SPL_SYS_THUMB_BUILD=y -CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds" CONFIG_ARCH_ASPEED=y CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_SYS_MALLOC_LEN=0x2000000 @@ -11,6 +11,7 @@ CONFIG_TARGET_EVB_AST2600=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds" CONFIG_ENV_SIZE=0x10000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb" @@ -20,6 +21,8 @@ CONFIG_SPL_SIZE_LIMIT=0x10000 CONFIG_SPL=y # CONFIG_ARMV7_NONSEC is not set CONFIG_SYS_LOAD_ADDR=0x83000000 +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_SPL_FIT_SIGNATURE=y @@ -40,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000 CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_CRC32=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_RAM_SUPPORT=y @@ -47,6 +51,14 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -54,6 +66,11 @@ CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_DOS_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -64,12 +81,10 @@ CONFIG_REGMAP=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_DM_HASH=y -CONFIG_HASH_ASPEED=y -CONFIG_ASPEED_ACRY=y CONFIG_ASPEED_GPIO=y CONFIG_DM_I2C=y -CONFIG_MISC=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y CONFIG_PHY_REALTEK=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index e0fb3f62b4..6526933274 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -18,6 +18,7 @@ CONFIG_FIT=y CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -51,6 +52,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index f44dec09c2..ebf13c31c5 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_OPTEE_IMAGE=y CONFIG_TPL_MAX_SIZE=0x100000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 6587c19c36..a2b88169c6 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_OPTEE_IMAGE=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 4d6d235cb1..c81437300c 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -99,6 +99,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index dbca68fcf3..65b76c6b36 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -49,6 +49,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_PRODUCT_NUM=0x110a diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index c2b3a0e315..b3198bfa38 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 104532bd05..5ae13d5a1e 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -49,6 +49,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index c48541a9ec..a81aa00f2d 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -133,6 +133,7 @@ CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=1024 CONFIG_CMD_CPU=y +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_BINOP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index ff14bd625a..c282990aa4 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -123,6 +123,7 @@ CONFIG_POWEROFF_GPIO=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index c9e4ee8f93..c332878126 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -74,6 +74,8 @@ CONFIG_CMD_E1000=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig index 7e9a7ea7c0..016282080b 100644 --- a/configs/giedi_defconfig +++ b/configs/giedi_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2073 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index cdd71b36dd..1ef4d6c881 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 02c59c3f31..c5cbce52a9 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 0effee6d30..0516176e6d 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_PROMPT="Ventana > " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=539 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set @@ -96,6 +97,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -113,6 +115,7 @@ CONFIG_E1000=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 28e08788b6..63c87f17a5 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_PROMPT="Ventana > " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=539 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set @@ -96,6 +97,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -117,6 +119,7 @@ CONFIG_E1000=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index f46440bf56..9d6819f19d 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_PROMPT="Ventana > " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=539 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL_NAND_OFS=0x1100000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_UNZIP=y @@ -99,6 +100,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -123,6 +125,7 @@ CONFIG_E1000=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 2a1db65d1b..4642eb1ccb 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -51,6 +51,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_MIN_ENTRIES=128 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 8a7d0fd8a9..4fc7356010 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -31,6 +31,7 @@ CONFIG_MISC_INIT_R=y # CONFIG_CMD_SETEXPR is not set CONFIG_ENV_IS_IN_NVRAM=y CONFIG_SCSI_AHCI=y +CONFIG_SYS_64BIT_LBA=y CONFIG_BOOTCOUNT_LIMIT=y # CONFIG_MMC is not set CONFIG_CALXEDA_XGMAC=y diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig index 85844f7ec8..8e673545a9 100644 --- a/configs/hsdk_4xd_defconfig +++ b/configs/hsdk_4xd_defconfig @@ -23,6 +23,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="hsdk-4xd# " CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2075 +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_ENV_FLAGS=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y @@ -68,6 +69,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_PANIC_HANG=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index a714d28134..3bd6f9314c 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -22,6 +22,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="hsdk# " CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2071 +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_ENV_FLAGS=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y @@ -67,6 +68,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_PANIC_HANG=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 1c43ae262d..2b5a587141 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -69,3 +69,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 3d4bd5145f..6ed3d68cd9 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y @@ -53,6 +54,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x2000 CONFIG_SYS_ATA_IDE1_OFFSET=0x4000 +CONFIG_LBA48=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 644d0abd3a..7adf76d777 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index b8070e7351..74dfc66804 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -142,6 +142,7 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_IMLS=y CONFIG_CMD_ENV_FLAGS=y CONFIG_CMD_I2C=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 00f0a670c2..17c97ac27f 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_ONENAND=y +CONFIG_USE_ONENAND_BOARD_INIT=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 8669217471..067498d80e 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -63,6 +63,7 @@ CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 8005591209..2a209bcfe4 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index dae7ddc20e..0708498813 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 69ebc6fa32..7040d782ef 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index a3c142feb2..0488ec223f 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index bf2b648634..1a0672879e 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 399b388460..da59e4c7ad 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -71,6 +71,7 @@ CONFIG_SYS_PBSIZE=2074 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 190209d632..49b36e0c8f 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -49,6 +49,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CRC32_VERIFY=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index cadef45028..bd17788768 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 357109e32e..738d308f45 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 68c2940456..5013dc5895 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -48,6 +48,7 @@ CONFIG_SYS_PROMPT="> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_FUSE=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index 4bc5512105..74d033eb40 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -48,6 +48,7 @@ CONFIG_SYS_PROMPT="> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_FUSE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index e16c1f60e6..e53e00845e 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 70d3d83e9a..7c1e48dccc 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y @@ -59,9 +60,6 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 889bcf7dc5..927b449e03 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -48,6 +48,7 @@ CONFIG_SYS_PROMPT="> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_FUSE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 4a0bf39398..935de02316 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CRC32_VERIFY=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 3a41767c15..f3b6907069 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -71,6 +71,7 @@ CONFIG_SYS_PBSIZE=2081 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 2b2a025c2b..dcee933a1b 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 97925196a8..9f067fc633 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index df35dcbb76..2271f2a14e 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index cef5f26d0b..7fdde41b6d 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CRC32_VERIFY=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index cd1ee4d9e7..6f59f29dac 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_I2C=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 2c566e068f..dc3992b0b4 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_POWER=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 5c36178026..f250425e26 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 908e50dab1..7b1e8dee16 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -54,6 +55,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index a0f9f20f2f..9ac6ef1678 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -66,6 +66,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 21ec66d7e4..5e25ed620f 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -67,6 +67,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig index 02a6665223..add8da0205 100644 --- a/configs/j721e_hs_evm_r5_defconfig +++ b/configs/j721e_hs_evm_r5_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index fb6e69197d..98d69a18b9 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -73,6 +73,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index b0c7ea3b99..515fa23b24 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_JETSON_TK1=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index e9618e3e20..9a0171e4a8 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -65,6 +65,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 252a02b579..27f119931f 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -64,6 +64,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 731fbfcab2..de2b625120 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -65,6 +65,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index 1d8ae5876b..054038fdd0 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg" CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_TARGET_KM_KIRKWOOD=y +# CONFIG_KIRKWOOD_PCIE_INIT is not set CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" @@ -31,6 +32,7 @@ CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index d2f2ff4e23..ac2deeb27c 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_TARGET_KM_KIRKWOOD=y +# CONFIG_KIRKWOOD_PCIE_INIT is not set CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" @@ -31,6 +32,7 @@ CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index 4d116c3a7a..80746791fe 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 17e899a919..ee900f5d9c 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -10,6 +10,11 @@ CONFIG_ENV_ADDR=0xebf20000 CONFIG_MPC85xx=y CONFIG_TARGET_KMCENT2=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_BOOK3E_HV=y +CONFIG_SYS_FSL_CPC=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_PCIE1=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_IVM_BUS=2 CONFIG_MP=y @@ -52,6 +57,7 @@ CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="fm1-mac5" CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 924f9ac463..34ab31565c 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -171,6 +171,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -200,6 +201,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 9654b8d806..5766f49d77 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_256M8_1.cfg" CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_TARGET_KM_KIRKWOOD=y +# CONFIG_KIRKWOOD_PCIE_INIT is not set CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -34,6 +35,7 @@ CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index dfa2500a29..98f23dbbf1 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -141,6 +141,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -169,6 +170,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index 8cbde0e178..a309acae7d 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 7775b604f5..6a6f20890a 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -154,6 +154,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 221335da8e..d251eba0d0 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -134,6 +134,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -160,6 +161,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmsuse2_defconfig b/configs/kmsuse2_defconfig index 8e27f9f6af..de44deb1ad 100644 --- a/configs/kmsuse2_defconfig +++ b/configs/kmsuse2_defconfig @@ -36,6 +36,7 @@ CONFIG_SYS_PBSIZE=532 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index f1791a0fc0..7c0ebefa69 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -133,6 +133,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -161,6 +162,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 6670c317a1..5bb3d9c116 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -154,6 +154,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index efa7a06886..f9cebf9e9c 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -92,6 +92,7 @@ CONFIG_FSL_QSPI=y CONFIG_MXC_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index 27a89f9b1b..49671e8fb4 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -48,6 +48,7 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index aaabb14f91..aaca8966c8 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -50,6 +50,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index 524138aa2e..13ff758212 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_it_h5_defconfig b/configs/libretech_all_h3_it_h5_defconfig index 1b08333586..75280ee1e3 100644 --- a/configs/libretech_all_h3_it_h5_defconfig +++ b/configs/libretech_all_h3_it_h5_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_XMC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig index e0734f9673..f42747e946 100644 --- a/configs/libretech_all_h5_cc_h5_defconfig +++ b/configs/libretech_all_h5_cc_h5_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_XMC=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 0ab5c868af..da72b39a49 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 4a65705a8e..8219d70e42 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -14,6 +14,7 @@ CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 8c70bf0951..c679b2b983 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -11,6 +11,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index c425a7aae8..b580a59df4 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 7c69d56d52..1f12a3b95a 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -5,11 +5,13 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_FSL_LS_PPA=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -47,6 +49,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index bb30e27e00..dfa525f31d 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -12,6 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_FSL_LS_PPA=y CONFIG_ENV_ADDR=0x401D0000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 21c989cff9..50855d5456 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -6,12 +6,14 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -45,6 +47,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 129855f984..2bdebe2da4 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 1adf0fe070..0f6c2ac37d 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -9,10 +9,12 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_FSL_QIXIS=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index a77e124b4b..fcc7914b56 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -6,13 +6,15 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_FSL_QIXIS=y CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -52,6 +54,7 @@ CONFIG_DM=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 5f361b6a35..98e48f2fba 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -10,11 +10,13 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_FSL_QIXIS=y CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 02d6e0f2e1..6147d4b0bc 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -5,12 +5,14 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -50,6 +52,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 0a6c43f04a..f9b0e6edac 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -13,6 +13,8 @@ CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_ENV_ADDR=0x40300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 6dc5674dbf..a603bd9acc 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -6,13 +6,15 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -48,6 +50,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 4224b48f9d..5a86992f09 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -14,6 +14,8 @@ CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 8b588f7d70..d731936d52 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -12,9 +12,12 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" -# CONFIG_DEEP_SLEEP is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_QSPI_BOOT=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index d34897a508..c71ab78186 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -14,12 +14,15 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -# CONFIG_DEEP_SLEEP is not set CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_RAMBOOT_PBL=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 915871338e..92fa4f000e 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -12,12 +12,15 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -35,6 +38,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 00d9d3eced..fcbaf9b685 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -12,12 +12,15 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -35,6 +38,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index cfa81baff6..19a21f4a04 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -16,14 +16,17 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -63,6 +66,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -95,6 +99,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index ad7e390b5c..727475f622 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -6,17 +6,20 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_SYS_MALLOC_LEN=0x1002000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_LOAD_ADDR=0x82000000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff # CONFIG_SYS_MALLOC_F is not set @@ -34,6 +37,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -62,6 +66,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y @@ -95,4 +100,3 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y -CONFIG_SPL_RSA=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 1434817e1c..82c6a1bdc3 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -12,12 +12,15 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -35,6 +38,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -65,6 +69,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 9bfbe2eff9..438a8ecf0a 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -12,12 +12,15 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -35,6 +38,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -65,6 +69,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 02d056f4e6..750a5a501e 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -13,10 +13,13 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -34,6 +37,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -62,6 +66,7 @@ CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 164e8b0176..cbb7c55944 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -16,15 +16,18 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -61,6 +64,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -93,6 +97,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 8a6357b0b2..71eff4582f 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -16,14 +16,17 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y @@ -60,6 +63,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y @@ -89,6 +93,7 @@ CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index cfa83b8c3b..4ee3072866 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -14,6 +14,9 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -26,6 +29,7 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 5e93f730b3..aad9978331 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -19,6 +19,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -52,6 +55,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x8000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 175f10f1f5..b86a60fd32 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -6,7 +6,6 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_SYS_MALLOC_LEN=0x1020000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -14,6 +13,10 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -32,6 +35,7 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 @@ -79,4 +83,3 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index e80b793a38..0410249b31 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -33,6 +36,7 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index a22d2a5921..82e3b39a52 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -15,6 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -33,6 +36,7 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index aadc61b66c..9343203eac 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -15,6 +15,9 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -34,6 +37,7 @@ CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index f16c156490..d247d114f3 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -21,6 +20,10 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -59,6 +62,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index c9a265d781..855657ca37 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -60,6 +63,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index e4f2b85823..a225f1a37b 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -21,6 +21,9 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -61,6 +64,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GREPENV=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 0d32be18e2..752dca28df 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -8,14 +8,14 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 00a5ead565..bb0e76df9b 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -12,12 +12,12 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 7e0860103f..7025f11447 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -11,12 +11,12 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 933084013b..31773689a7 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -8,14 +8,14 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index bc5987cc5d..c953706216 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -12,12 +12,12 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 5a40f002c8..364a34751f 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -19,9 +26,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 0acb8817ec..7b083b32fb 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -19,9 +26,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 1fe04fe769..7446f01272 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -15,6 +15,15 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -22,11 +31,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index af362b1347..6dd797c652 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -19,9 +26,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 6ba6b420c0..30cc15a12f 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -13,15 +13,19 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x40300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x40300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 21231cb416..53f19a376e 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -15,6 +15,16 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" @@ -22,12 +32,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 7991458727..447a51513f 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -15,18 +15,22 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" +CONFIG_VOL_MONITOR_INA220=y +CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 9035594139..1ebe893b43 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -6,22 +6,26 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -64,6 +68,7 @@ CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -102,5 +107,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 6bf7500686..d04d1d918b 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -14,16 +14,20 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x60500000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x60500000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 7f4729fe7d..787c8f96bd 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -13,6 +12,11 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FSL_LS_PPA=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 @@ -45,10 +49,12 @@ CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -85,6 +91,5 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 454f3dccbb..341fb0f926 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -14,6 +14,10 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FSL_LS_PPA=y CONFIG_ENV_ADDR=0x60300000 +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 @@ -49,6 +53,7 @@ CONFIG_DM=y CONFIG_FSL_CAAM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 401bc393b2..305734d748 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -7,7 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 @@ -15,6 +14,11 @@ CONFIG_FSL_LS_PPA=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 @@ -73,6 +77,7 @@ CONFIG_SPL_DM=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 3c5e5ce0ae..56cdef8221 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -19,6 +19,10 @@ CONFIG_FSL_LS_PPA=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 9d29c365c6..bf2805db9e 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -7,7 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_SPL_TEXT_BASE=0x10000000 @@ -16,6 +15,11 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 @@ -73,6 +77,7 @@ CONFIG_SPL_DM=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 # CONFIG_SPL_DM_MMC is not set CONFIG_FSL_ESDHC=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 0c348615fa..f1370b5104 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -20,6 +20,10 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 34f6952f43..12ccb78b92 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -6,7 +6,6 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -15,6 +14,11 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -44,10 +48,12 @@ CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_DM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -83,6 +89,5 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 5d36183195..db52294872 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -17,6 +17,10 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x60500000 +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -51,6 +55,7 @@ CONFIG_DM=y CONFIG_FSL_CAAM=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_SYS_DDR_RAW_TIMING=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 00444420b9..1be7002a18 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -6,14 +6,18 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" -CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -45,6 +49,7 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 95ecf2adfb..f41434c741 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -10,12 +10,16 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" -CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x40500000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 8b1713099d..fdeedca476 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -5,13 +5,19 @@ CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_SYS_MALLOC_LEN=0x120000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -19,8 +25,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -64,6 +68,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index bf9f4803a9..a66099c815 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -19,9 +26,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index c4672d0366..835159deef 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -12,6 +12,13 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x60300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -19,9 +26,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index d63e5a53e4..2a70d660ed 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -15,6 +15,15 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -22,11 +31,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index d62e5b611b..049cf1e56f 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -13,15 +13,19 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x40300000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x40300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 0fa3ea1c36..11554a831d 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -15,6 +15,16 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" @@ -22,12 +32,6 @@ CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index e55712fce1..68aae882a8 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -15,18 +15,22 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" +CONFIG_VOL_MONITOR_INA220=y +CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 58bc95d91c..7fd24122f0 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -6,22 +6,26 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -64,6 +68,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 881f1f1b63..52d3d302d9 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -14,16 +14,20 @@ CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x60500000 +CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv" CONFIG_VOL_MONITOR_INA220=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x60500000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 9cba997eb4..3314198446 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -21,6 +21,10 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 2a7c730aa0..2ea72cc2a8 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -15,6 +14,11 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 @@ -57,6 +61,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 6f9a2e8ea2..c6b537f3b8 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -17,6 +17,10 @@ CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_ENV_ADDR=0x40300000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 799d460f2b..57cebf5f8b 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -23,6 +23,10 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 4301d38eb7..6960aa9d3f 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -7,7 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -20,6 +19,11 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 @@ -80,6 +84,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 # CONFIG_SPL_DM_MMC is not set CONFIG_FSL_ESDHC=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 50efffa442..9ca4315c83 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -21,6 +21,10 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 62020ee6c8..e192ef48b1 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -6,7 +6,6 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_LEN=0x102000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -17,6 +16,11 @@ CONFIG_QSPI_AHB_INIT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y +CONFIG_NXP_ESBC=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -51,6 +55,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index c0685777ea..6e5f29a708 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -19,6 +19,10 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x40500000 CONFIG_AHCI=y +CONFIG_LAYERSCAPE_NS_ACCESS=y +CONFIG_PCIE1=y +CONFIG_PCIE2=y +CONFIG_PCIE3=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 1580ceb6b7..64d87ae9b4 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -8,16 +8,15 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x80300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x80300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -71,6 +70,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index b20a5d20f7..3af10a0e06 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -5,19 +5,18 @@ CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -65,6 +64,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index caf5d774f5..55a5389272 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -9,17 +9,16 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_ENV_ADDR=0x20300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ENV_ADDR=0x20300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -68,6 +67,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 663aacf876..d3b0684839 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -11,6 +11,12 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_SPL_VID=y @@ -18,12 +24,6 @@ CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -90,6 +90,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index f3e204875e..fa1f71d77c 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -11,6 +11,12 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_SPL_VID=y @@ -18,12 +24,6 @@ CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -86,6 +86,7 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index a135de388f..af5ecadec9 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -11,18 +11,17 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x20500000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -79,6 +78,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 8571eec461..b4cae480e1 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -5,19 +5,18 @@ CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 1cd59ec7e2..452ee839b8 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -9,17 +9,16 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_ENV_ADDR=0x20300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ENV_ADDR=0x20300000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 5b462a41c9..e36512e62d 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -7,10 +7,15 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_SPL_VID=y @@ -18,11 +23,6 @@ CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 455fce3ed7..2f81a1343c 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -11,6 +11,12 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_SPL_VID=y @@ -18,12 +24,6 @@ CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 7354d4132d..b5f556dc20 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -7,20 +7,19 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y @@ -101,6 +100,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index bb7e57691e..3af7828887 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -11,18 +11,17 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x20500000 -CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index abc958f5dd..91cb2df6ee 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -6,13 +6,13 @@ CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_AHCI=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set @@ -59,6 +59,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 9278a6e80f..8aef83af82 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -8,12 +8,12 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_FSL_LS_PPA=y CONFIG_ENV_ADDR=0x80300000 CONFIG_AHCI=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set @@ -62,6 +62,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index dab9a7fb85..1d841af6b0 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -12,12 +12,12 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y @@ -83,6 +83,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index afa2469b1b..302de32398 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -10,9 +10,9 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_QIXIS=y -CONFIG_AHCI=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y @@ -64,6 +64,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 3d6aa69d5f..e97284222d 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -12,14 +12,14 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_SPL_TEXT_BASE=0x1800a000 -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_AHCI=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y @@ -78,6 +78,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index cb2d56838a..4fab4fb3b1 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -6,8 +6,10 @@ CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -15,8 +17,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_AHCI=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 136a101179..c3327cd0b7 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -8,6 +8,9 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_ENV_ADDR=0x80300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -15,9 +18,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x80300000 -CONFIG_AHCI=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 9fcc5d6647..6c7b49b71c 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -12,6 +12,10 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x200000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_SPL_TEXT_BASE=0x1800a000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -19,10 +23,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 981217c147..fb7faa46d2 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -9,15 +9,15 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index c46e506213..dc0f6f886b 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -11,13 +11,13 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x580500000 CONFIG_AHCI=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_FSL_QIXIS=y +# CONFIG_QIXIS_I2C_ACCESS is not set # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y CONFIG_MP=y @@ -73,6 +73,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 0ec945fce8..b86f8164f0 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -6,17 +6,17 @@ CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 651bd04e0e..9e08552fb3 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -10,15 +10,15 @@ CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_ENV_ADDR=0x20300000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_ENV_ADDR=0x20300000 -CONFIG_AHCI=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 2f0ece68eb..8d970cce42 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -8,9 +8,13 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -18,10 +22,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -103,6 +103,5 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 37d3275278..d70d3cbf90 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -12,6 +12,11 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" +CONFIG_QSPI_AHB_INIT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ENV_ADDR=0x580500000 +CONFIG_AHCI=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv" @@ -19,11 +24,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x580500000 -CONFIG_AHCI=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 4fe9f6d3a6..0da058302c 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -44,6 +44,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index e57f93ebd1..d847255d5e 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -45,6 +45,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index abb095d98a..b2bc71afa8 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -8,21 +8,20 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSPI_AHB_EN_4BYTE=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y -CONFIG_OF_BOARD_FIXUP=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -69,6 +68,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y @@ -105,7 +105,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index e8ae5af0ad..32e47c326e 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -12,19 +12,18 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -76,6 +75,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_ESDHC_DETECT_QUIRK=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y @@ -112,6 +112,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index d7ebf896fb..a758a4dca2 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -8,22 +8,21 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_EMC2305=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_NXP_ESBC=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -96,7 +95,7 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index d3cfb1fea5..e6e794006c 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -12,13 +12,6 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_EMC2305=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -26,6 +19,12 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -107,6 +106,7 @@ CONFIG_OPTEE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index 5589c48bef..bbdcb895d8 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -12,13 +12,6 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_EMC2305=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -26,6 +19,12 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -107,5 +106,6 @@ CONFIG_OPTEE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_EFI_MM_COMM_TEE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index d0f92f8e2c..bb81e56fed 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -8,21 +8,20 @@ CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_NXP_ESBC=y CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_VID=y -CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_FSL_QIXIS=y -CONFIG_FSPI_AHB_EN_4BYTE=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y -CONFIG_OF_BOARD_FIXUP=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y @@ -109,6 +108,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_RSA=y -CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index df437a6beb..216ac80074 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -12,19 +12,18 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index c48c8a3ffb..b7a4238e92 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -12,19 +12,18 @@ CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_SPL_VID=y -CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" -CONFIG_VOL_MONITOR_LTC3882_READ=y -CONFIG_VOL_MONITOR_LTC3882_SET=y -CONFIG_FSL_QIXIS=y CONFIG_FSPI_AHB_EN_4BYTE=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y +CONFIG_FSL_USE_PCA9547_MUX=y +CONFIG_VID=y +CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" +CONFIG_VOL_MONITOR_LTC3882_READ=y +CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 2ccea8315c..2ce0ab9181 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -68,6 +68,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ub CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index cbea4fadff..e55b4a4914 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -17,6 +17,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="malta # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=281 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set @@ -38,5 +39,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y +CONFIG_PCI_GT64120=y +CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index b268e33a37..6c6492d3fe 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -9,8 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xffffffff81000000 CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000 CONFIG_TARGET_MALTA=y CONFIG_BUILD_TARGET="u-boot-swap.bin" -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_CPU_MIPS64_R2=y +CONFIG_SYS_LITTLE_ENDIAN=y # CONFIG_AUTOBOOT is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y @@ -19,6 +19,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="maltael # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=283 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set @@ -40,5 +41,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y +CONFIG_PCI_GT64120=y +CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 7b1b50547a..3aff68b018 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -16,6 +16,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="malta # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=281 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set @@ -37,5 +38,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y +CONFIG_PCI_GT64120=y +CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 540864b573..e268fb6374 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -18,6 +18,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="maltael # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=283 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set @@ -39,5 +40,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y +CONFIG_PCI_GT64120=y +CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 5828d84fb1..ad61859b89 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_SYS_MAXARGS=15 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 462c8b7f29..cf093532b1 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -16,6 +16,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 87eb82a79a..2e9edc6c4e 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -61,6 +61,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y CONFIG_SPI=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 7000b89311..34465f99a5 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 04e15c6148..b2e1a8e826 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -13,10 +13,10 @@ CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y CONFIG_SOC_JR2=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fc00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -30,6 +30,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=279 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index b144dd4354..8eebe7b314 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -14,11 +14,11 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y CONFIG_SOC_LUTON=y CONFIG_DDRTYPE_MT47H128M8HQ=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_MIPS_BOOT_FDT=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x87c00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -32,6 +32,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=281 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index e088f3ca04..6ba9311626 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -12,10 +12,10 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fc00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -29,6 +29,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index a56c5ebdec..1b9096682f 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -11,9 +11,9 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y CONFIG_SOC_SERVAL=y CONFIG_DDRTYPE_H5TQ1G63BFA=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x87c00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -27,6 +27,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig index cf1c4db1d3..ca358e666a 100644 --- a/configs/mscc_servalt_defconfig +++ b/configs/mscc_servalt_defconfig @@ -10,9 +10,9 @@ CONFIG_ENV_OFFSET_REDUND=0x140000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ARCH_MSCC=y CONFIG_SOC_SERVALT=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fc00000 +CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -26,6 +26,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=283 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig index 9e409b60b2..8c64bb740a 100644 --- a/configs/mt7620_mt7530_rfb_defconfig +++ b/configs/mt7620_mt7530_rfb_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_BSS_START_ADDR=0x80010000 CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig index f3f5e3a887..2aa6eb7e26 100644 --- a/configs/mt7620_rfb_defconfig +++ b/configs/mt7620_rfb_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_BSS_START_ADDR=0x80010000 CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index 06e85c2f57..c8ac1997ca 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_SYS_MAXARGS=8 CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index 4320fe5bb6..4e8905b68f 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_SYS_MAXARGS=8 CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig index 7690213ab8..14fc8b05e3 100644 --- a/configs/mt7628_rfb_defconfig +++ b/configs/mt7628_rfb_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_BSS_START_ADDR=0x80010000 CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SYS_BOOTM_LEN=0x1000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index f5e3c26d66..a74c3edbf8 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -37,6 +37,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_SYS_MAXARGS=8 CONFIG_SYS_PBSIZE=1049 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig index 86e8b75e61..bcffaefb9b 100644 --- a/configs/mvebu_crb_cn9130_defconfig +++ b/configs/mvebu_crb_cn9130_defconfig @@ -26,6 +26,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Marvell>> " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=1051 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y @@ -47,6 +48,8 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 7b7382216b..437d438f8f 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -47,6 +47,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y # CONFIG_MVEBU_GPIO is not set diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index 0b4afbe59e..2eee745ed6 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -25,6 +25,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -43,6 +44,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig index 9f6196095b..99d46c1a2a 100644 --- a/configs/mvebu_db_cn9130_defconfig +++ b/configs/mvebu_db_cn9130_defconfig @@ -28,6 +28,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Marvell>> " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=1051 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y @@ -48,6 +49,8 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 8368e4c028..dd1f912150 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -58,6 +58,8 @@ CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_PCI=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y CONFIG_DM_I2C=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index be4bbe87ca..8164beb141 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -26,6 +26,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -47,6 +48,8 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig index c05beef8f9..25ae690fe6 100644 --- a/configs/mvebu_puzzle-m801-88f8040_defconfig +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -30,6 +30,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -50,6 +51,8 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index 6b3235ca6e..136c1d6069 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -43,6 +43,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),5 CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index edfa8b6928..1f15287369 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -56,6 +56,7 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index a1bc95bb4a..021e8a6151 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 551057fcfa..fa2c280a8d 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -54,6 +54,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 900fbf7ca7..d9d429b4f9 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -103,6 +103,7 @@ CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 15dbaf848c..ea0c764674 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -97,6 +97,8 @@ CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index c41b2d9264..1985ff96de 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -60,6 +60,8 @@ CONFIG_DM_ETH=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 10f6b4f099..784a5d97f0 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -93,6 +93,7 @@ CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig index 5b3b332f10..2b55fbd3b2 100644 --- a/configs/mx7ulp_com_defconfig +++ b/configs/mx7ulp_com_defconfig @@ -20,6 +20,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 6a22040c03..95cd22a59d 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MAXARGS=256 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index ea03eb3771..45cdd74f09 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -19,6 +19,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=256 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 41793ca7e4..15c2e1698c 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -102,6 +102,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index 8f3c242a7a..226ccaa12f 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -7,6 +7,7 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index 66df94b33b..6fedf056ff 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 60f2631842..3f834b756d 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig index 06c564ec8c..a0cf8ff044 100644 --- a/configs/nanopi_r1s_h5_defconfig +++ b/configs/nanopi_r1s_h5_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index ca482ce745..cc971f9b19 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -37,6 +38,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xa0000@0x0(uboot),0x010000@0xa0000(env),0x500000@0xc0000(uimage),0x1a40000@0x5c0000(rootfs)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y @@ -52,6 +55,7 @@ CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_LBA48=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 32308a04f6..248ce90519 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -55,6 +56,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig index bbfa9e13fa..73de5ed15b 100644 --- a/configs/netgear_dgnd3700v2_ram_defconfig +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -68,3 +68,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 2a1c3ac2d3..eea86eb0b7 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -55,6 +56,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 3c847316f6..cb06fe2ae3 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -55,6 +56,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 8239d45a84..3a46146910 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_SATA=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -54,6 +55,8 @@ CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 CONFIG_BLK=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 673e0a42a3..d39b6a479e 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y @@ -55,6 +56,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 2bf3e3a961..ec75ead6e2 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -62,6 +62,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index e169350f55..1b999ecc9c 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -62,6 +62,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 77d7afa6df..d4ab93850c 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -63,6 +63,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y @@ -74,6 +75,8 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 8b525eb5ff..2b39ae74b3 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y @@ -52,6 +53,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/nsim_700_defconfig b/configs/nsim_700_defconfig index bcf954aa63..60809400d2 100644 --- a/configs/nsim_700_defconfig +++ b/configs/nsim_700_defconfig @@ -18,6 +18,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_SYS_PROMPT="nsim# " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=279 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/nsim_700be_defconfig b/configs/nsim_700be_defconfig index 5a09db2f9b..e021cc94cc 100644 --- a/configs/nsim_700be_defconfig +++ b/configs/nsim_700be_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_SYS_PROMPT="nsim# " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=279 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/nsim_hs38_defconfig b/configs/nsim_hs38_defconfig index ad8acec4e0..3c3d1812a7 100644 --- a/configs/nsim_hs38_defconfig +++ b/configs/nsim_hs38_defconfig @@ -20,6 +20,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="nsim# " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=279 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_DM=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/nsim_hs38be_defconfig b/configs/nsim_hs38be_defconfig index 8a63e58263..9e1a14845d 100644 --- a/configs/nsim_hs38be_defconfig +++ b/configs/nsim_hs38be_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_SYS_PROMPT="nsim# " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=279 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 489ff63595..a48920cc99 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0x70006000 CONFIG_DEBUG_UART_CLOCK=408000000 CONFIG_TEGRA124=y CONFIG_TARGET_NYAN_BIG=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x82408000 CONFIG_DEBUG_UART=y CONFIG_FIT=y diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index 21468c426b..1cd8e9f2b6 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index dc2e215c05..0a18b94295 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -20,6 +20,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig index 5330915230..95e98c1161 100644 --- a/configs/octeon_nic23_defconfig +++ b/configs/octeon_nic23_defconfig @@ -27,6 +27,7 @@ CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -45,6 +46,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_TFTP_TSIZE=y CONFIG_SATA=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y # CONFIG_INPUT is not set CONFIG_MISC=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index fc7bc6d50e..d4f9f565ae 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -37,6 +37,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y @@ -59,6 +60,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CDP=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index e0d4fe76a0..aeb9f8a8b6 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -37,6 +37,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y @@ -60,6 +61,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CDP=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index 72e7c6ff53..6fe96f4755 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -37,6 +37,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y @@ -82,6 +83,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_TSIZE=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index fbdf1cb846..5ba4fc1cad 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -35,6 +35,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y @@ -79,6 +80,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_TSIZE=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 7acdca9339..929a52140d 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ARCH_EXYNOS5=y +# CONFIG_EXYNOS_TMU is not set CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x310000 diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index d442aca788..9f4543c1ba 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_LEN=0x5004000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_ODROID=y +CONFIG_EXYNOS_ACE_SHA=y CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x140000 @@ -71,6 +72,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_LIB_HW_RAND=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index c76c10ac70..787c26eaa4 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -51,6 +51,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 2637ecf9c5..ab5dfad28f 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index f55d52736b..ce777cae88 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -50,6 +50,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 97cdc9491d..8c5bc19f10 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 73d742ea1d..912dd91259 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -54,6 +54,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_ETH=y +CONFIG_PALMAS_POWER=y CONFIG_SCSI=y CONFIG_SCSI_AHCI_PLAT=y CONFIG_CONS_INDEX=3 diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index b45f6d8564..28f4f95c95 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -105,6 +105,7 @@ CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_DA8XX=y CONFIG_USB_MUSB_PIO_ONLY=y diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig index aa4c307b4c..98d6818e1b 100644 --- a/configs/openpiton_riscv64_defconfig +++ b/configs/openpiton_riscv64_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -73,8 +74,6 @@ CONFIG_RAM=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_FS_SQUASHFS=y -CONFIG_SPL_TINY_MEMSET=y -CONFIG_TPL_TINY_MEMSET=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_MD5=y diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig index bf0e09b73c..8ae265f902 100644 --- a/configs/openpiton_riscv64_spl_defconfig +++ b/configs/openpiton_riscv64_spl_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -90,7 +91,6 @@ CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_FS_SQUASHFS=y CONFIG_SPL_TINY_MEMSET=y -CONFIG_TPL_TINY_MEMSET=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_MD5=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 967246a9db..ba5d3a6bfc 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x2000 CONFIG_SYS_ATA_IDE1_OFFSET=0x4000 +CONFIG_LBA48=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index f1dbed87d6..0ee6ce3a65 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x2000 CONFIG_SYS_ATA_IDE1_OFFSET=0x4000 +CONFIG_LBA48=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 49668150fb..f7e8a3ee4e 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0x100 CONFIG_SYS_ATA_ALT_OFFSET=0x100 CONFIG_SYS_ATA_IDE0_OFFSET=0x2000 CONFIG_SYS_ATA_IDE1_OFFSET=0x4000 +CONFIG_LBA48=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 1c1daf86a3..b76e272e25 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -55,6 +55,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig index 824f017dae..dbca66d142 100644 --- a/configs/orangepi_3_defconfig +++ b/configs/orangepi_3_defconfig @@ -10,6 +10,7 @@ CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x118000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_PHY_SUN50I_USB3=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index cfce6cb0d4..14c8806281 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -9,5 +9,6 @@ CONFIG_MMC0_CD_PIN="PF6" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x118000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 63d3addbdd..a4336332fc 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -9,5 +9,6 @@ CONFIG_MMC0_CD_PIN="PF6" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x118000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 7b12bf00ff..d0cad2a746 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SPI_SUNXI=y CONFIG_SPL_STACK=0x54000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 8c4cb57ef0..690a5f195b 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 830cbbaaeb..7a9ca8e88a 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index 62117548e2..cad7a7bb06 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_MAX_SIZE=0xbfa0 CONFIG_SPL_STACK=0x58000 CONFIG_SPL_I2C=y CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index 79040125dc..02f70ccf0c 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index 008384e460..15520955f5 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 0a36472d33..9a429a8704 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -54,5 +54,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index d93b355d47..3852f7ba07 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000" CONFIG_TEGRA210=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y @@ -15,6 +16,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2089 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 74125c15a8..bf5872203b 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180" CONFIG_TEGRA210=y CONFIG_TARGET_P2371_2180=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y @@ -18,6 +19,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2089 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index b4e14add1d..5f57b1c019 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571" CONFIG_TEGRA210=y CONFIG_TARGET_P2571=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y @@ -16,6 +17,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2571) # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2084 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index 7b2fd5795a..ed23937fed 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2093 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 41621970f0..15e07a1294 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2093 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index fbe4aea1bd..36a001b83b 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" CONFIG_TEGRA210=y CONFIG_TARGET_P3450_0000=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y @@ -19,6 +20,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2089 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 75999d177d..41f1dc22c8 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 27be607566..d6662e18ab 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -84,6 +84,9 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y +CONFIG_VIDEO_EXYNOS=y +CONFIG_EXYNOS_DP=y +CONFIG_EXYNOS_FB=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_LCD=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index 296b4ceb19..07740571c7 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -83,6 +83,9 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y +CONFIG_VIDEO_EXYNOS=y +CONFIG_EXYNOS_DP=y +CONFIG_EXYNOS_FB=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_LCD=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index c5d6574083..bc58a631be 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_CLK_FREQ=66666666 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60060000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 @@ -44,6 +46,7 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -68,6 +71,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index c2b079df37..5d70160bd3 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60220000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 @@ -42,6 +44,7 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -66,6 +69,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 56e922a241..a604d3248f 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_CLK_FREQ=66666666 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60060000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 @@ -44,6 +46,7 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -68,6 +71,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 9d25094a9a..dfd6d627e1 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -17,6 +17,8 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60220000 CONFIG_AHCI=y +# CONFIG_DEEP_SLEEP is not set +CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 @@ -42,6 +44,7 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMINFO=y @@ -66,6 +69,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_VERSION_VARIABLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index d791e9dcf8..519a705a40 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index 18373600a4..cb9c6b8fec 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -72,6 +72,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index e27b5626a3..3adba803dd 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -87,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index f8754092ff..0a2f10d0f1 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -75,6 +75,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 275a3a0d1f..cbfe346820 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -87,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index aeda455743..e8f6c434b6 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -78,6 +78,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 13a7fcf175..a9d21eb02c 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -84,6 +84,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 3181964cdd..6a2f87a8bb 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -87,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 8e27f72314..6d4bebd6dc 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x8000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index e27b5626a3..3adba803dd 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -87,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index bb085678c7..a184393abd 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -75,6 +75,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 1a052a4022..79aa398e1e 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -87,6 +87,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index c6b4f7bf14..3f9ea1e329 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 7dbe061790..62608f93bd 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -8,6 +8,7 @@ CONFIG_PINE64_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 2cddcf5830..2f511c8051 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x118000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 121182c55d..af473f9136 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -90,6 +90,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index bf070aab8b..982f68143b 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -10,6 +10,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig index d882c0cc88..905b47d29e 100644 --- a/configs/pinephone_defconfig +++ b/configs/pinephone_defconfig @@ -12,6 +12,7 @@ CONFIG_PINEPHONE_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig index f90cb0d1f8..e20d20a2fd 100644 --- a/configs/pinetab_defconfig +++ b/configs/pinetab_defconfig @@ -10,3 +10,4 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index c22076250b..6922380b00 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -61,6 +61,9 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9261" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_LCD=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 1406e7f1aa..2b4a844d80 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -65,6 +65,9 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_SLOT_NAME="at91sam9263" +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_LCD=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index b7f9c12efc..e1a2517eb6 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -35,6 +35,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 6f928edf41..c62c88f1b5 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -64,6 +64,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_KIRKWOOD_GPIO=y # CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MVEBU_MMC=y diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig index 13b1d7b628..515624fd42 100644 --- a/configs/pomelo_defconfig +++ b/configs/pomelo_defconfig @@ -18,6 +18,7 @@ CONFIG_LAST_STAGE_INIT=y CONFIG_SYS_PROMPT="pomelo#" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 5b5039e290..7b024437c2 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 55444b69a7..034f7e6935 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -1,15 +1,17 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xf01000 +CONFIG_SYS_TEXT_BASE=0xf00000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500" CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_QEMU_PPCE500=y +CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_MONITOR_BASE=0x00F01000 +CONFIG_SYS_MONITOR_BASE=0x00F00000 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr" @@ -39,6 +41,7 @@ CONFIG_DM=y CONFIG_SIMPLE_BUS_CORRECT_RANGE=y CONFIG_BLK=y CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_LBA48=y CONFIG_CHIP_SELECTS_PER_CTRL=0 CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 1f169e1a34..9634d7f77f 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -13,6 +13,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 6f501a8798..1c5a0617aa 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -14,6 +14,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 2bc7b9fbd0..2421c9a371 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 95dc1b4769..d5eae95c80 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -14,6 +14,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 3eb3ea756e..2861d07f97 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -17,6 +17,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index e39accf940..1ecfa27ce2 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 66192734d5..b81e60658f 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -65,6 +65,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y CONFIG_SPL_DM_RTC=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index b9ab1805ab..c65b5868cd 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -46,6 +46,8 @@ CONFIG_SYS_ATA_DATA_OFFSET=0 CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y CONFIG_SPI=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index d14a7adc5d..5094547231 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -28,6 +28,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PCI_INIT_R=y CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index 5a38b07043..2beda3a2fe 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -52,6 +52,7 @@ CONFIG_PCNET=y CONFIG_RTL8139=y CONFIG_TULIP=y CONFIG_PCI=y +CONFIG_SH7751_PCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SERIAL_RX_BUFFER=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 9f27592088..373bca678d 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -79,6 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index ab25abc1a0..43b90c7879 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -108,6 +108,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 1d51a267b9..7d95e171f7 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -109,6 +109,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 7abb343ad6..87b050f5dc 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index c06ab641c3..dcececdc31 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_STACK=0xff718000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 640fe558d4..bc333a5e2a 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -106,6 +106,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y # CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 78e50dbfbc..bb5b214369 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -74,6 +74,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 4d2a5b32e3..ef28fe6a93 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -87,6 +87,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index a0104044a8..05335d2c2b 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_ONENAND=y +CONFIG_USE_ONENAND_BOARD_INIT=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y @@ -50,6 +51,7 @@ CONFIG_DM_I2C_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y +CONFIG_SAMSUNG_ONENAND=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX8998=y CONFIG_USB=y @@ -58,5 +60,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index af7fef58a6..cab0ac8e84 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -49,6 +49,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y +CONFIG_SAMSUNG_ONENAND=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX8998=y CONFIG_SOFT_SPI=y @@ -58,5 +59,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index 9c9166c16c..c50aa6b5c5 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y @@ -71,6 +72,13 @@ CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=8 CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y @@ -79,6 +87,9 @@ CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_AT91=y CONFIG_TIMER=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index f07725de36..d8d2383fed 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y @@ -72,6 +73,14 @@ CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=8 CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y @@ -80,6 +89,9 @@ CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_AT91=y CONFIG_TIMER=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 688fa00d23..86a49a1acf 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_PING=y @@ -83,6 +84,15 @@ CONFIG_SYS_I2C_AT91=y CONFIG_I2C_EEPROM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=2 +CONFIG_SF_DEFAULT_SPEED=66000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -91,6 +101,9 @@ CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_AT91=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index 0139ebefe2..2fd58b07bd 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -53,11 +53,9 @@ CONFIG_AT91_GPIO=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=4 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 8483260512..486e2190b2 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -104,6 +104,9 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_SPL_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y +CONFIG_USB_ATMEL_CLK_SEL_UPLL=y CONFIG_USB_STORAGE=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index f12c5d7917..184ff5ff72 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -107,6 +107,9 @@ CONFIG_ATMEL_PIT_TIMER=y CONFIG_SPL_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y +CONFIG_USB_ATMEL_CLK_SEL_UPLL=y CONFIG_USB_STORAGE=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index 20ca98821a..860362e158 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -28,6 +28,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMTEST=y diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index c9f62a8ebe..bc2852f091 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -28,6 +28,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_IMI is not set CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMTEST=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 46a9b16ad3..6553568e76 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -134,7 +134,6 @@ CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y -CONFIG_SPL_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_I8042_KEYB=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 86204c7908..572cf8edd8 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -178,7 +178,6 @@ CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y -CONFIG_SPL_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_I8042_KEYB=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 2c909ead4b..a71ce77c40 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -106,7 +106,6 @@ CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_I2C_MUX=y -CONFIG_SPL_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_I8042_KEYB=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 6f261882fa..df008b797f 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -71,3 +71,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index d014b2a814..fa1e7bd2c0 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -53,6 +53,8 @@ CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_DM=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_MVEBU_MMC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index 84bc49c0f2..99faabaa2f 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_CLK=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 02d4e54b07..c390af2689 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_PWM=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index 2e938b6486..b6b9f88c00 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -28,6 +28,8 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set CONFIG_CONSOLE_SCROLL_LINES=5 # CONFIG_GZIP is not set diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 57c5218d4b..84337e49e6 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -69,6 +69,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 @@ -91,6 +92,8 @@ CONFIG_MACB=y CONFIG_RMII=y CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 2c8bd1c8ee..ae5983e807 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=384 # CONFIG_CMD_FLASH is not set CONFIG_CMD_ONENAND=y +CONFIG_USE_ONENAND_BOARD_INIT=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y @@ -36,5 +37,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_ONENAND=y # CONFIG_MMC is not set CONFIG_MTD=y +CONFIG_SAMSUNG_ONENAND=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x98800300 diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 4377a58130..8d1b28dcf8 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -94,6 +94,9 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y +CONFIG_VIDEO_EXYNOS=y +CONFIG_EXYNOS_DP=y +CONFIG_EXYNOS_FB=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index e20789a6b4..bdfe764d9e 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -48,6 +48,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2082 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 7ae2b164a0..e2d869610c 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -42,6 +42,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2082 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index 539548bfcb..6f15b3e962 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -49,6 +49,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2082 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index c3b6368f61..958adfe25a 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -52,6 +52,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=500 CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 77d868a74a..37c8436318 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -47,6 +47,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_N5X # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2079 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 92d6045c6a..5f415b7ad4 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -39,6 +39,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_N5X # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2079 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index d3a9042ef2..a57d54a7f2 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -48,6 +48,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_N5X # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2079 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 72cf0d1bc8..83e24402a8 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -42,7 +42,9 @@ CONFIG_SPL_STACK=0x0 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 53d6b82972..def2ee8dbc 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index e4d8a2e049..6be4210c7d 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -1,10 +1,10 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y @@ -47,6 +47,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2085 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 6aff07d778..07e9f20a41 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -43,6 +43,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2085 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 0f4aa90514..d0c87416ef 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMDLINE_PS_SUPPORT=y CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index d902019d6c..60a38abc8e 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_ADDR=0xFFF40000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SOCRATES=y +CONFIG_ENABLE_36BIT_PHYS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -27,6 +28,7 @@ CONFIG_CMD_REGINFO=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y @@ -95,4 +97,6 @@ CONFIG_USB=y # CONFIG_USB_EHCI_HCD is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_PCI=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=15 +CONFIG_SYS_OHCI_SWAP_REG_ACCESS=y CONFIG_USB_STORAGE=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 3b96d64b3b..d912ac70bc 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -56,6 +56,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y CONFIG_SPI=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 576e86493a..55116f72d0 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index ad017564d9..366790b4ef 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -95,6 +95,9 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y +CONFIG_VIDEO_EXYNOS=y +CONFIG_EXYNOS_DP=y +CONFIG_EXYNOS_FB=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_LCD=y diff --git a/configs/stemmy_defconfig b/configs/stemmy_defconfig index 28a3129873..7fc0a39872 100644 --- a/configs/stemmy_defconfig +++ b/configs/stemmy_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_CONFIG=y CONFIG_CMD_LICENSE=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 198a0c7f9e..c9be056cf6 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTARGS="console=ttyAS1,115200 CONSOLE=/dev/ttyAS1 consoleblank=0 root=/ # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="stih410-b2260 => " CONFIG_SYS_PBSIZE=1058 +CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -58,6 +59,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig index 8ca8929f2a..64610658c7 100644 --- a/configs/stm32746g-eval_defconfig +++ b/configs/stm32746g-eval_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPI=y diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index 55e44f863c..753a4b80cb 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -69,6 +69,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 22274f99b1..e3f80ab8e2 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPI=y diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index c174984b93..927d28dd97 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -69,6 +69,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 9845eb0a10..b7e9ee92a7 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPI=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index a5dc89c802..bae28b4ec1 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index b5dcec78f5..f5b6262883 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -18,6 +18,7 @@ CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index 9441b8c3b1..c70329cd4a 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y @@ -43,6 +44,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index 9616285452..838fd89eb9 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y @@ -43,6 +44,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index 354a43cf55..d503c1a36f 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y @@ -43,6 +44,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index a601477d12..c2792aaad3 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_MEMINFO=y @@ -43,6 +44,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 8ae668ca23..416d92bf1b 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -64,6 +65,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 8c41f80ee1..3452403c61 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -23,6 +23,7 @@ CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -40,6 +41,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index fc23400264..4f478c1312 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -52,6 +52,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_TARGET="u-boot.itb" CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_EEPROM=y @@ -72,6 +73,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 95338c58c7..01fbb05123 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -50,6 +50,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_TARGET="u-boot.itb" CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXPORTENV is not set CONFIG_CMD_EEPROM=y @@ -70,6 +71,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index ebb51289c8..e14668042f 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -24,6 +24,7 @@ CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PBSIZE=1050 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -41,6 +42,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index d03d984871..2c143068b7 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -37,6 +37,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_PHY_RESET_DELAY=10000 CONFIG_ETH_DESIGNWARE=y +CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y CONFIG_CADENCE_QSPI=y CONFIG_HAS_CQSPI_REF_CLK=y diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 5e4accf4b1..9ddc80fe17 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -17,6 +17,7 @@ CONFIG_FIT=y CONFIG_BOOTSTAGE_STASH_SIZE=4096 CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=128 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_IMLS=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 31a550031d..51f629488b 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -9,8 +9,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 -CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_ZYNQ_MAC_IN_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA CONFIG_SYS_LOAD_ADDR=0x0 @@ -39,6 +37,7 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SYS_SPL_ARGS_ADDR=0x10000000 CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2071 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y diff --git a/configs/tanix_tx6_defconfig b/configs/tanix_tx6_defconfig index d1f12fba9b..84dbf106d4 100644 --- a/configs/tanix_tx6_defconfig +++ b/configs/tanix_tx6_defconfig @@ -10,3 +10,4 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_STACK=0x118000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index c0a4dcc271..3d61c7b57b 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -8,7 +8,6 @@ CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 CONFIG_SYS_MALLOC_LEN=0x460000 CONFIG_TARGET_TAURUS=y @@ -19,6 +18,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" @@ -110,6 +110,8 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_ATMEL_USART=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 +CONFIG_USB_ATMEL=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index 575bf2dae2..aebaa6ad14 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_SYS_PROMPT="[tb100]:~# " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 1519f7dbce..892d7c60d2 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -71,6 +71,8 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y @@ -81,6 +83,8 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y # CONFIG_PCI_PNP is not set +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_RTC=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index cd6d825715..6f202dc8a4 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -11,6 +11,7 @@ CONFIG_I2C0_ENABLE=y CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" CONFIG_SPL_STACK=0x54000 CONFIG_SYS_PBSIZE=1024 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index daaefba364..afb1957ddd 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -58,6 +58,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index a62ce3e0a5..113c0dae2e 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -57,6 +57,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index a54f34a6cf..95ff9d763f 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -55,6 +55,8 @@ CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_NUVOTON_NCT6102D=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index a3d6313f02..d47413c0a9 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -67,9 +67,11 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_SATA_MV=y CONFIG_SYS_SATA_MAX_DEVICE=1 +CONFIG_LBA48=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y CONFIG_FPGA_ALTERA=y +CONFIG_FPGA_STRATIX_V=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 0a6b0e88b3..6115e9e3ed 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -79,6 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 03b6201591..71fbf2122c 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_PROMPT="ThunderX_88XX> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_EDITENV is not set diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index ce12b79ac4..839b93284f 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 8dede27efc..886c6a933a 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index a11a17905c..faa0c4b10e 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -10,7 +10,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt" CONFIG_SYS_LOAD_ADDR=0x0 @@ -39,6 +38,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index f962f37d7e..97b3f237dc 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -10,7 +10,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt" CONFIG_SYS_LOAD_ADDR=0x0 @@ -39,6 +38,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index dc71856f72..4c76e8d180 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -10,7 +10,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus" CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" CONFIG_SYS_LOAD_ADDR=0x0 @@ -39,6 +38,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 00a663fcf2..b48ed9c424 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_LEN=0x5001000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_TRATS2=y +CONFIG_EXYNOS_ACE_SHA=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2" @@ -61,6 +62,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_LIB_HW_RAND=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index d5f0866606..3e0fdfe834 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_LEN=0x5001000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_TRATS=y +CONFIG_EXYNOS_ACE_SHA=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats" @@ -58,6 +59,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_LIB_HW_RAND=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 3c2a7a34d1..0d1c99c62c 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -134,6 +134,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -160,6 +161,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 8f273da2f1..3fe731fd18 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -156,6 +156,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 +CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 613a81b9b7..2b2dc16646 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -54,6 +54,8 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y CONFIG_DM_I2C=y @@ -100,4 +102,3 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_LZO=y -CONFIG_SPL_LZO=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index e5bacb1bb8..a1d2d7f2e4 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -44,6 +44,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 72306ab25e..5de9a68834 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_CMD_CONFIG=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_XIMG is not set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index a448d1cb4b..b6b5ca58c2 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_CMD_CONFIG=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_XIMG is not set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index db986cf13b..eccfb0dbb1 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -16,6 +16,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot" CONFIG_LOGLEVEL=6 CONFIG_CMD_CONFIG=y +CONFIG_SYS_BOOTM_LEN=0x2000000 # CONFIG_CMD_XIMG is not set CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_GPIO=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index f19dcbddcd..0f9cc8d82d 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -58,6 +58,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Variscite" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 25ee96a1dd..db455f4d97 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2" CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_VENICE2=y +CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index ba8883dced..792bcf1eb5 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -35,3 +35,4 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_PCI=y CONFIG_USB=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index f6ed47f734..288169c7ee 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_VYBRID_GPIO=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 3b9aa97909..8d87857ba0 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -84,6 +84,8 @@ CONFIG_DM_ETH=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PCI_SCAN_SHOW=y +CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y @@ -93,6 +95,7 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index cbaf970e6a..516e2cc32b 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x8800 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x8000 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 +CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_SPL=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 595176190a..8b0533ce58 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -59,6 +59,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig index fec124204b..31fb4fde40 100644 --- a/configs/xenguest_arm64_defconfig +++ b/configs/xenguest_arm64_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1051 # CONFIG_CMD_BDI is not set # CONFIG_CMD_BOOTD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_ELF is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_IMI is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index cb10394951..7f0bcb2eaa 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 -CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt" CONFIG_CMD_FRU=y CONFIG_DEFINE_TCM_OCM_MMAP=y @@ -24,6 +23,7 @@ CONFIG_CLOCKS=y CONFIG_SYS_PROMPT="Versal> " CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2073 +CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MEMTEST=y @@ -106,6 +106,8 @@ CONFIG_XILINX_UARTLITE=y CONFIG_SOC_XILINX_VERSAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index fb4e72be0d..b3834b4952 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2071 # CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig index 1ae6349030..1784792ce4 100644 --- a/configs/xilinx_zynqmp_r5_defconfig +++ b/configs/xilinx_zynqmp_r5_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="ZynqMP r5> " CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 +CONFIG_SYS_BOOTM_LEN=0x3c00000 # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_EMBED=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 855a1c9773..89622d18f8 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -55,6 +55,7 @@ CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2073 +CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 65b0896c7f..a7da4bcb83 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -11,18 +11,6 @@ Configuration options CONFIG_USB_OHCI_NEW: enable the new OHCI driver - CONFIG_SYS_USB_OHCI_BOARD_INIT: call the board dependant hooks: - - - extern int board_usb_init(void); - - extern int usb_board_stop(void); - - extern int usb_cpu_init_fail(void); - - CONFIG_SYS_USB_OHCI_CPU_INIT: call the cpu dependant hooks: - - - extern int usb_cpu_init(void); - - extern int usb_cpu_stop(void); - - extern int usb_cpu_init_fail(void); - CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers @@ -43,21 +31,3 @@ config option needs to be defined. - -PCI Controllers ----------------- - -You'll need to define - - CONFIG_PCI_OHCI - -If you have several USB PCI controllers, define - - CONFIG_PCI_OHCI_DEVNO: number of the OHCI device in PCI list - -If undefined, the first instance found in PCI space will be used. - -PCI Controllers need to do byte swapping on register accesses, so they -should to define: - - CONFIG_SYS_OHCI_SWAP_REG_ACCESS diff --git a/doc/develop/driver-model/serial-howto.rst b/doc/develop/driver-model/serial-howto.rst index 8af79a90f4..9da0e57eab 100644 --- a/doc/develop/driver-model/serial-howto.rst +++ b/doc/develop/driver-model/serial-howto.rst @@ -3,15 +3,6 @@ How to port a serial driver to driver model =========================================== -Almost all of the serial drivers have been converted as at January 2016. These -ones remain: - - * serial_bfin.c - * serial_pxa.c - -The deadline for this work was the end of January 2016. If no one steps -forward to convert these, at some point there may come a patch to remove them! - Here is a suggested approach for converting your serial driver over to driver model. Please feel free to update this file with your ideas and suggestions. diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index ce6907e690..7715c40365 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -113,12 +113,20 @@ config SATA_CEVA config FSL_SATA bool "Enable Freescale SATA controller driver support" + depends on PPC select AHCI select LIBATA + imply LBA48 help Enable this driver to support the SATA controller found in some Freescale PowerPC SoCs. +config FSL_SATA_V2 + bool "Enable support for V2 of the Freescale SATA controller" + depends on FSL_SATA + help + Enable support for V2 of this controller, rather than V1. + config SATA_MV bool "Enable Marvell SATA controller driver support" select AHCI diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index d9fd850c6f..1a2c3c2fe7 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -844,138 +844,6 @@ static ulong sata_write_common(struct ahci_uc_priv *uc_priv, return rc; } -#if !CONFIG_IS_ENABLED(AHCI) -static int ahci_init_one(int pdev) -{ - int rc; - struct ahci_uc_priv *uc_priv = NULL; - - uc_priv = malloc(sizeof(struct ahci_uc_priv)); - if (!uc_priv) - return -ENOMEM; - - memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); - uc_priv->dev = pdev; - - uc_priv->host_flags = ATA_FLAG_SATA - | ATA_FLAG_NO_LEGACY - | ATA_FLAG_MMIO - | ATA_FLAG_PIO_DMA - | ATA_FLAG_NO_ATAPI; - - uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; - - /* initialize adapter */ - rc = ahci_host_init(uc_priv); - if (rc) - goto err_out; - - ahci_print_info(uc_priv); - - /* Save the uc_private struct to block device struct */ - sata_dev_desc[pdev].priv = uc_priv; - - return 0; - -err_out: - if (uc_priv) - free(uc_priv); - return rc; -} - -int init_sata(int dev) -{ - struct ahci_uc_priv *uc_priv = NULL; - -#if defined(CONFIG_MX6) - if (!is_mx6dq() && !is_mx6dqp()) - return 1; -#endif - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { - printf("The sata index %d is out of ranges\n\r", dev); - return -1; - } - - ahci_init_one(dev); - - uc_priv = sata_dev_desc[dev].priv; - - return dwc_ahci_start_ports(uc_priv) ? 1 : 0; -} - -int reset_sata(int dev) -{ - struct ahci_uc_priv *uc_priv; - struct sata_host_regs *host_mmio; - - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { - printf("The sata index %d is out of ranges\n\r", dev); - return -1; - } - - uc_priv = sata_dev_desc[dev].priv; - if (NULL == uc_priv) - /* not initialized, so nothing to reset */ - return 0; - - host_mmio = uc_priv->mmio_base; - setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); - while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) - udelay(100); - - free(uc_priv); - memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc)); - - return 0; -} - -int sata_port_status(int dev, int port) -{ - struct sata_port_regs *port_mmio; - struct ahci_uc_priv *uc_priv = NULL; - - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) - return -EINVAL; - - if (sata_dev_desc[dev].priv == NULL) - return -ENODEV; - - uc_priv = sata_dev_desc[dev].priv; - port_mmio = uc_priv->port[port].port_mmio; - - return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; -} - -/* - * SATA interface between low level driver and command layer - */ -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - - return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, - buffer); -} - -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - - return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, - buffer); -} - -int scan_sata(int dev) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - struct blk_desc *pdev = &sata_dev_desc[dev]; - - return dwc_ahsata_scan_common(uc_priv, pdev); -} -#endif /* CONFIG_IS_ENABLED(AHCI) */ - -#if CONFIG_IS_ENABLED(AHCI) - int dwc_ahsata_port_status(struct udevice *dev, int port) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); @@ -1109,4 +977,3 @@ U_BOOT_DRIVER(dwc_ahsata_ahci) = { .probe = dwc_ahsata_probe, }; #endif -#endif diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c index d1bab93189..6db4247368 100644 --- a/drivers/ata/fsl_sata.c +++ b/drivers/ata/fsl_sata.c @@ -6,10 +6,13 @@ */ #include <common.h> +#include <ahci.h> #include <blk.h> #include <command.h> #include <console.h> #include <cpu_func.h> +#include <dm.h> +#include <dm/device-internal.h> #include <log.h> #include <asm/io.h> #include <asm/processor.h> @@ -21,33 +24,6 @@ #include <linux/delay.h> #include "fsl_sata.h" -#if CONFIG_IS_ENABLED(BLK) -#include <dm.h> -#include <ahci.h> -#include <blk.h> -#include <dm/device-internal.h> -#else -#ifndef CONFIG_SYS_SATA1_FLAGS - #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#endif -#ifndef CONFIG_SYS_SATA2_FLAGS - #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#endif - -static struct fsl_sata_info fsl_sata_info[] = { -#ifdef CONFIG_SATA1 - {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS}, -#else - {0, 0}, -#endif -#ifdef CONFIG_SATA2 - {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS}, -#else - {0, 0}, -#endif -}; -#endif - static inline void sdelay(unsigned long sec) { unsigned long i; @@ -86,11 +62,7 @@ static int ata_wait_register(unsigned __iomem *addr, u32 mask, return (i < timeout_msec) ? 0 : -1; } -#if !CONFIG_IS_ENABLED(BLK) -int init_sata(int dev) -#else static int init_sata(struct fsl_ata_priv *priv, int dev) -#endif { u32 length, align; cmd_hdr_tbl_t *cmd_hdr; @@ -129,15 +101,9 @@ static int init_sata(struct fsl_ata_priv *priv, int dev) snprintf(sata->name, 12, "SATA%d:", dev); /* Set the controller register base address to device struct */ -#if !CONFIG_IS_ENABLED(BLK) - sata_dev_desc[dev].priv = (void *)sata; - reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base); - sata->dma_flag = fsl_sata_info[dev].flags; -#else reg = (fsl_sata_reg_t *)(priv->base + priv->offset * dev); sata->dma_flag = priv->flag; priv->fsl_sata = sata; -#endif sata->reg_base = reg; /* Allocate the command header table, 4 bytes aligned */ @@ -738,17 +704,11 @@ static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt, /* * SATA interface between low level driver and command layer */ -#if !CONFIG_IS_ENABLED(BLK) -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer) { struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif u32 rc; if (sata->lba48) @@ -760,17 +720,11 @@ static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, return rc; } -#if !CONFIG_IS_ENABLED(BLK) -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) { struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif u32 rc; if (sata->lba48) { @@ -801,17 +755,11 @@ static void fsl_sata_identify(fsl_sata_t *sata, u16 *id) ata_swap_buf_le16(id, ATA_ID_WORDS); } -#if !CONFIG_IS_ENABLED(BLK) -int scan_sata(int dev) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static int scan_sata(struct udevice *dev) { struct blk_desc *desc = dev_get_uclass_plat(dev); struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif unsigned char serial[ATA_ID_SERNO_LEN + 1]; unsigned char firmware[ATA_ID_FW_REV_LEN + 1]; @@ -853,15 +801,6 @@ static int scan_sata(struct udevice *dev) debug("Device supports LBA28\n\r"); #endif -#if !CONFIG_IS_ENABLED(BLK) - memcpy(sata_dev_desc[dev].product, serial, sizeof(serial)); - memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware)); - memcpy(sata_dev_desc[dev].vendor, product, sizeof(product)); - sata_dev_desc[dev].lba = (u32)n_sectors; -#ifdef CONFIG_LBA48 - sata_dev_desc[dev].lba48 = sata->lba48; -#endif -#else memcpy(desc->product, serial, sizeof(serial)); memcpy(desc->revision, firmware, sizeof(firmware)); memcpy(desc->vendor, product, sizeof(product)); @@ -869,7 +808,6 @@ static int scan_sata(struct udevice *dev) #ifdef CONFIG_LBA48 desc->lba48 = sata->lba48; #endif -#endif /* Get the NCQ queue depth from device */ sata->queue_depth = ata_id_queue_depth(id); @@ -890,7 +828,6 @@ static int scan_sata(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(BLK) static const struct blk_ops sata_fsl_blk_ops = { .read = sata_read, .write = sata_write, @@ -1042,4 +979,3 @@ U_BOOT_DRIVER(fsl_ahci) = { .remove = fsl_ata_remove, .priv_auto = sizeof(struct fsl_ata_priv), }; -#endif diff --git a/drivers/ata/fsl_sata.h b/drivers/ata/fsl_sata.h index 5b9daa79e0..e1ea8eb3a1 100644 --- a/drivers/ata/fsl_sata.h +++ b/drivers/ata/fsl_sata.h @@ -319,7 +319,6 @@ typedef struct fsl_sata { #define READ_CMD 0 #define WRITE_CMD 1 -#if CONFIG_IS_ENABLED(BLK) struct fsl_ata_priv { u32 base; u32 flag; @@ -327,6 +326,5 @@ struct fsl_ata_priv { u32 offset; fsl_sata_t *fsl_sata; }; -#endif #endif /* __FSL_SATA_H__ */ diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h index bea4322c91..9ad09e5461 100644 --- a/drivers/ata/sata_sil.h +++ b/drivers/ata/sata_sil.h @@ -212,12 +212,10 @@ enum { CMD_ERR = 0x21, }; -#if CONFIG_IS_ENABLED(BLK) #define ATA_MAX_PORTS 32 struct sil_sata_priv { int port_num; struct sil_sata *sil_sata_desc[ATA_MAX_PORTS]; }; -#endif #endif diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index d6d1c6e32c..b5b482086a 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -218,3 +218,19 @@ config IDE_RESET must be defined in a board-specific file. endif # IDE + +config LBA48 + bool "Enable LBA support for disks larger than 137GB" + depends on HAVE_BLOCK_DEVICE + help + Set this to enable support for disks larger than 137GB. + Also look at CONFIG_SYS_64BIT_LBA. Without both of these, LBA48 + support uses 32bit variables and will 'only' support disks up to + 2.1TB. + +config SYS_64BIT_LBA + bool "Enable 64bit number of blocks on a block device" + depends on HAVE_BLOCK_DEVICE + help + Make the block subsystem use 64bit sector addresses, rather than the + default of 32bit. diff --git a/drivers/block/ide.c b/drivers/block/ide.c index e8518ff3a1..3270a9f032 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -695,15 +695,6 @@ void ide_init(void) unsigned char c; int i, bus; -#ifdef CONFIG_IDE_PREINIT - WATCHDOG_RESET(); - - if (ide_preinit()) { - puts("ide_preinit failed\n"); - return; - } -#endif /* CONFIG_IDE_PREINIT */ - WATCHDOG_RESET(); /* ATAPI Drives seems to need a proper IDE Reset */ diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 66ce4cc29b..e918f74694 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -237,4 +237,15 @@ config SYS_BOOTCOUNT_MAGIC help Set the magic value used for the boot counter. +choice + prompt "Endianness of bootcount accessors" + default SYS_BOOTCOUNT_LE + +config SYS_BOOTCOUNT_LE + bool "Little endian accessors" + +config SYS_BOOTCOUNT_BE + bool "Big endian accessors" + +endchoice endif diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index a1b4496ca2..623c6915b8 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -12,6 +12,7 @@ #include <asm/arch/scu_ast2500.h> #include <dm/lists.h> #include <dt-bindings/clock/aspeed-clock.h> +#include <dt-bindings/reset/ast2500-reset.h> #include <linux/delay.h> #include <linux/err.h> @@ -173,6 +174,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = ast2500_get_uart_clk_rate(priv->scu, 5); break; default: + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } @@ -425,6 +427,25 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) return new_rate; } +#define SCU_CLKSTOP_SDIO 27 +static ulong ast2500_enable_sdclk(struct ast2500_scu *scu) +{ + u32 reset_bit; + u32 clkstop_bit; + + reset_bit = BIT(ASPEED_RESET_SDIO); + clkstop_bit = BIT(SCU_CLKSTOP_SDIO); + + setbits_le32(&scu->sysreset_ctrl1, reset_bit); + udelay(100); + //enable clk + clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); + mdelay(10); + clrbits_le32(&scu->sysreset_ctrl1, reset_bit); + + return 0; +} + static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) { struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); @@ -438,6 +459,7 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) new_rate = ast2500_configure_d2pll(priv->scu, rate); break; default: + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } @@ -479,7 +501,11 @@ static int ast2500_clk_enable(struct clk *clk) case ASPEED_CLK_D2PLL: ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); break; + case ASPEED_CLK_GATE_SDCLK: + ast2500_enable_sdclk(priv->scu); + break; default: + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index f191b0f317..0df1dc3718 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -471,7 +471,7 @@ static ulong ast2600_clk_get_rate(struct clk *clk) rate = ast2600_get_uart_huxclk_rate(priv->scu); break; default: - debug("can't get clk rate\n"); + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } @@ -1073,13 +1073,13 @@ static int ast2600_clk_enable(struct clk *clk) case ASPEED_CLK_GATE_SDCLK: ast2600_enable_sdclk(priv->scu); break; - case ASPEED_CLK_GATE_SDEXTCLK: + case ASPEED_CLK_SDIO: ast2600_enable_extsdclk(priv->scu); break; case ASPEED_CLK_GATE_EMMCCLK: ast2600_enable_emmcclk(priv->scu); break; - case ASPEED_CLK_GATE_EMMCEXTCLK: + case ASPEED_CLK_EMMC: ast2600_enable_extemmcclk(priv->scu); break; case ASPEED_CLK_GATE_FSICLK: @@ -1098,7 +1098,7 @@ static int ast2600_clk_enable(struct clk *clk) ast2600_enable_rsaclk(priv->scu); break; default: - pr_err("can't enable clk\n"); + debug("%s: unknown clk %ld\n", __func__, clk->id); return -ENOENT; } diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 99e28713f9..8eb0070d22 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -245,7 +245,7 @@ config SPL_SYSCON config TPL_SYSCON bool "Support system controllers in TPL" - depends on SPL_REGMAP + depends on TPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index eec9d480b0..738b788401 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -30,5 +30,10 @@ config DDR_SPD For memory controllers that can utilize it, add enable support for using the JEDEC SDP standard. +config SYS_SPD_BUS_NUM + int "I2C bus number for DDR SPD" + depends on DDR_SPD || SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY + default 0 + source "drivers/ddr/altera/Kconfig" source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index fe69bef3d3..d93ed8d2fe 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -10,6 +10,12 @@ config SYS_FSL_MMDC help Select Freescale Multi Mode DDR controller (MMDC). +config SYS_FSL_DDR_EMU + bool + help + Specify emulator support for DDR. Some DDR features such as deskew + training are not available. + if SYS_FSL_DDR || SYS_FSL_MMDC config SYS_FSL_DDR_BE @@ -169,6 +175,13 @@ config ECC_INIT_VIA_DDRCONTROLLER Use the DDR controller to auto initialize memory. If not enabled, the DMA controller is responsible for doing this. +config SYS_DDR_RAW_TIMING + bool "Get DDR timing information from something other than SPD" + help + This is common with soldered DDR chips onboard without SPD. DDR raw + timing parameters are extracted from datasheet and hard-coded into + header files or board specific files. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index f10d1aaf4b..eae1c8ddc9 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -3,7 +3,7 @@ config FIRMWARE config SPL_FIRMWARE bool "Enable Firmware driver support in SPL" - depends on FIRMWARE + depends on FIRMWARE && SPL config SPL_ARM_PSCI_FW bool diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index 8529ef2900..5ae0556a9a 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -16,7 +16,7 @@ struct ti_sci_resource_static_data { #if IS_ENABLED(CONFIG_K3_DM_FW) -#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM) +#if IS_ENABLED(CONFIG_SOC_K3_J721E) static struct ti_sci_resource_static_data rm_static_data[] = { /* Free rings */ { @@ -48,43 +48,9 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }, { }, }; -#endif /* CONFIG_TARGET_J721E_R5_EVM */ +#endif /* CONFIG_SOC_K3_J721E */ -#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM) -static struct ti_sci_resource_static_data rm_static_data[] = { - /* Free rings */ - { - .dev_id = 235, - .subtype = 1, - .range_start = 124, - .range_num = 32, - }, - /* TX channels */ - { - .dev_id = 236, - .subtype = 13, - .range_start = 6, - .range_num = 2, - }, - /* RX channels */ - { - .dev_id = 236, - .subtype = 10, - .range_start = 6, - .range_num = 2, - }, - /* RX Free flows */ - { - .dev_id = 236, - .subtype = 0, - .range_start = 60, - .range_num = 8, - }, - { }, -}; -#endif /* CONFIG_TARGET_J7200_R5_EVM */ - -#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM) +#if IS_ENABLED(CONFIG_SOC_K3_J721S2) static struct ti_sci_resource_static_data rm_static_data[] = { /* Free rings */ { @@ -116,7 +82,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }, { }, }; -#endif /* CONFIG_TARGET_J721S2_R5_EVM */ +#endif /* CONFIG_SOC_K3_J721S2 */ #if IS_ENABLED(CONFIG_SOC_K3_AM625) static struct ti_sci_resource_static_data rm_static_data[] = { diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index dc0b3dd31b..76719517f5 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -21,6 +21,12 @@ config FPGA_SOCFPGA This provides common functionality for Gen5 and Arria10 devices. +config FPGA_STRATIX_V + bool "Enable Stratix V FPGA drivers" + depends on FPGA_ALTERA + help + Say Y here to enable the Altera Stratix V FPGA specific driver. + config FPGA_CYCLON2 bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 149a62ffe6..8ab22ed817 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -89,7 +89,7 @@ config DM_GPIO_LOOKUP_LABEL config SPL_DM_GPIO_LOOKUP_LABEL bool "Enable searching for gpio labelnames" - depends on DM_GPIO && SPL_DM && SPL_GPIO + depends on SPL_DM_GPIO help This option enables searching for gpio names in the defined gpio labels, if the search for the @@ -490,7 +490,7 @@ config DM_PCA953X config SPL_DM_PCA953X bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL" - depends on DM_GPIO + depends on SPL_DM_GPIO help Say yes here to provide access to several register-oriented SMBus I/O expanders, made mostly by NXP or TI. Compatible diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index bea609db9d..77a76c1d50 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -36,6 +36,11 @@ static struct atmel_pio4_port *atmel_pio4_port_base(u32 port) case AT91_PIO_PORTD: base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD; break; +#if (ATMEL_PIO_PORTS > 4) + case AT91_PIO_PORTE: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOE; + break; +#endif default: printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n", port); diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index 2d3fecaa14..c9ffe2d628 100644 --- a/drivers/i2c/ast_i2c.c +++ b/drivers/i2c/ast_i2c.c @@ -16,6 +16,7 @@ #include <asm/arch/scu_ast2500.h> #include <linux/delay.h> #include <linux/err.h> +#include <reset.h> #include "ast_i2c.h" @@ -108,19 +109,26 @@ static int ast_i2c_of_to_plat(struct udevice *dev) static int ast_i2c_probe(struct udevice *dev) { - struct ast2500_scu *scu; + struct reset_ctl reset_ctl; + int rc; debug("Enabling I2C%u\n", dev_seq(dev)); /* * Get all I2C devices out of Reset. - * Only needs to be done once, but doing it for every - * device does not hurt. + * + * Only needs to be done once so test before performing reset. */ - scu = ast_get_scu(); - ast_scu_unlock(scu); - clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C); - ast_scu_lock(scu); + rc = reset_get_by_index(dev, 0, &reset_ctl); + if (rc) { + printf("%s: Failed to get reset signal\n", __func__); + return rc; + } + + if (reset_status(&reset_ctl) > 0) { + reset_assert(&reset_ctl); + reset_deassert(&reset_ctl); + } ast_i2c_init_bus(dev); @@ -343,6 +351,7 @@ static const struct dm_i2c_ops ast_i2c_ops = { static const struct udevice_id ast_i2c_ids[] = { { .compatible = "aspeed,ast2400-i2c-bus" }, { .compatible = "aspeed,ast2500-i2c-bus" }, + { .compatible = "aspeed,ast2600-i2c-bus" }, { }, }; diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c index 39bcacc17a..a7349e06cf 100644 --- a/drivers/i2c/exynos_hs_i2c.c +++ b/drivers/i2c/exynos_hs_i2c.c @@ -147,7 +147,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) unsigned int i = 0, utemp0 = 0, utemp1 = 0; unsigned int t_ftl_cycle; -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) clkin = get_i2c_clk(); #else clkin = get_PCLK(); diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 39683fc43b..323c4fbe9c 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -9,7 +9,7 @@ config I2C_MUX config SPL_I2C_MUX bool "Support I2C multiplexers on SPL" - depends on I2C_MUX + depends on SPL && I2C_MUX help This enables I2C buses to be multiplexed, so that you can select one of several buses using some sort of control mechanism. The diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index aaccb3aa22..505e20bc61 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -8,7 +8,7 @@ #include <errno.h> #include <dm.h> #include <fdtdec.h> -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) #include <log.h> #include <asm/arch/clk.h> #include <asm/arch/cpu.h> @@ -53,7 +53,7 @@ static void read_write_byte(struct s3c24x0_i2c *i2c) static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) { ulong freq, pres = 16, div; -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) freq = get_i2c_clk(); #else freq = get_PCLK(); diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 418ed215c5..ccdd7d7395 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -67,7 +67,7 @@ config LED_BLINK config SPL_LED bool "Enable LED support in SPL" - depends on SPL && SPL_DM + depends on SPL_DM help The LED subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use LEDs in SPL, @@ -85,7 +85,7 @@ config LED_GPIO config SPL_LED_GPIO bool "LED support for GPIO-connected LEDs in SPL" - depends on SPL_LED && DM_GPIO + depends on SPL_LED && SPL_DM_GPIO help This option is an SPL-variant of the LED_GPIO option. See the help of LED_GPIO for details. diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c index 10bd1636c3..0ebae358eb 100644 --- a/drivers/led/led_pwm.c +++ b/drivers/led/led_pwm.c @@ -95,27 +95,17 @@ static enum led_state_t led_pwm_get_state(struct udevice *dev) static int led_pwm_probe(struct udevice *dev) { struct led_pwm_priv *priv = dev_get_priv(dev); - struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); - - /* Ignore the top-level LED node */ - if (!uc_plat->label) - return 0; return led_pwm_set_state(dev, (priv->enabled) ? LEDST_ON : LEDST_OFF); } static int led_pwm_of_to_plat(struct udevice *dev) { - struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); struct led_pwm_priv *priv = dev_get_priv(dev); struct ofnode_phandle_args args; uint def_brightness, max_brightness; int ret; - /* Ignore the top-level LED node */ - if (!uc_plat->label) - return 0; - ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0, &args); if (ret) return ret; @@ -173,10 +163,15 @@ static const struct udevice_id led_pwm_ids[] = { U_BOOT_DRIVER(led_pwm) = { .name = LEDS_PWM_DRIVER_NAME, .id = UCLASS_LED, - .of_match = led_pwm_ids, .ops = &led_pwm_ops, .priv_auto = sizeof(struct led_pwm_priv), - .bind = led_pwm_bind, .probe = led_pwm_probe, .of_to_plat = led_pwm_of_to_plat, }; + +U_BOOT_DRIVER(led_pwm_wrap) = { + .name = LEDS_PWM_DRIVER_NAME "_wrap", + .id = UCLASS_NOP, + .of_match = led_pwm_ids, + .bind = led_pwm_bind, +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 28d5da49ff..e839c08c19 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -275,6 +275,20 @@ config FSL_SEC_MON Security Monitor can be transitioned on any security failures, like software violations or hardware security violations. +choice + prompt "Security monitor interaction endianess" + depends on FSL_SEC_MON + default SYS_FSL_SEC_MON_BE if PPC + default SYS_FSL_SEC_MON_LE + +config SYS_FSL_SEC_MON_LE + bool "Security monitor interactions are little endian" + +config SYS_FSL_SEC_MON_BE + bool "Security monitor interactions are big endian" + +endchoice + config IRQ bool "Interrupt controller" help @@ -312,6 +326,12 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config NPCM_HOST + bool "Enable support espi or LPC for Host" + depends on REGMAP && SYSCON + help + Enable NPCM BMC espi or LPC support for Host reading and writing. + config SPL_MXC_OCOTP bool "Enable MXC OCOTP driver in SPL" depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 0bf05ca05e..022e54e065 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NPCM_OTP) += npcm_otp.o +obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 4302e180ac..bdd7e018cc 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -170,13 +170,6 @@ static const struct i2c_eeprom_drv_data eeprom_data = { .offset_len = 1, }; -static const struct i2c_eeprom_drv_data mc24aa02e48_data = { - .size = 256, - .pagesize = 8, - .addr_offset_mask = 0, - .offset_len = 1, -}; - static const struct i2c_eeprom_drv_data atmel24c01a_data = { .size = 128, .pagesize = 8, @@ -264,7 +257,6 @@ static const struct i2c_eeprom_drv_data atmel24c512_data = { static const struct udevice_id i2c_eeprom_std_ids[] = { { .compatible = "i2c-eeprom", (ulong)&eeprom_data }, - { .compatible = "microchip,24aa02e48", (ulong)&mc24aa02e48_data }, { .compatible = "atmel,24c01", (ulong)&atmel24c01a_data }, { .compatible = "atmel,24c01a", (ulong)&atmel24c01a_data }, { .compatible = "atmel,24c02", (ulong)&atmel24c02_data }, diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c new file mode 100644 index 0000000000..0244e40457 --- /dev/null +++ b/drivers/misc/npcm_host_intf.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Host interface (LPC or eSPI) configuration on Nuvoton BMC + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> + +#define SMC_CTL_REG_ADDR 0xc0001001 +#define SMC_CTL_HOSTWAIT 0x80 + +/* GCR Register Offsets */ +#define HIFCR 0x50 +#define MFSEL1 0x260 +#define MFSEL4 0x26c + +/* ESPI Register offsets */ +#define ESPICFG 0x4 +#define ESPIHINDP 0x80 + +/* MFSEL bit fileds */ +#define MFSEL1_LPCSEL BIT(26) +#define MFSEL4_ESPISEL BIT(8) + +/* ESPICFG bit fileds */ +#define CHSUPP_MASK GENMASK(27, 24) +#define IOMODE_MASK GENMASK(9, 8) +#define IOMODE_SDQ FIELD_PREP(IOMODE_MASK, 3) +#define MAXFREQ_MASK GENMASK(12, 10) +#define MAXFREQ_33MHZ FIELD_PREP(MAXFREQ_MASK, 2) + +/* ESPIHINDP bit fileds */ +#define AUTO_SBLD BIT(4) +#define AUTO_HS1 BIT(8) +#define AUTO_HS2 BIT(12) +#define AUTO_HS3 BIT(16) + +static int npcm_host_intf_bind(struct udevice *dev) +{ + struct regmap *syscon; + void __iomem *base; + u32 ch_supp, val; + u32 ioaddr; + const char *type; + int ret; + + /* Release host wait */ + setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT); + + syscon = syscon_regmap_lookup_by_phandle(dev, "syscon"); + if (IS_ERR(syscon)) { + dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name); + return PTR_ERR(syscon); + } + + ioaddr = dev_read_u32_default(dev, "ioaddr", 0); + if (ioaddr) + regmap_write(syscon, HIFCR, ioaddr); + + type = dev_read_string(dev, "type"); + if (!type) + return -EINVAL; + + if (!strcmp(type, "espi")) { + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + ret = dev_read_u32(dev, "channel-support", &ch_supp); + if (ret) + return ret; + + /* Select eSPI pins function */ + regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, 0); + regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, MFSEL4_ESPISEL); + + val = AUTO_SBLD | AUTO_HS1 | AUTO_HS2 | AUTO_HS3 | ch_supp; + writel(val, base + ESPIHINDP); + + val = readl(base + ESPICFG); + val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK); + val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp); + writel(val, base + ESPICFG); + } else if (!strcmp(type, "lpc")) { + /* Select LPC pin function */ + regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0); + regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL); + } + + return 0; +} + +static const struct udevice_id npcm_hostintf_ids[] = { + { .compatible = "nuvoton,npcm750-host-intf" }, + { .compatible = "nuvoton,npcm845-host-intf" }, + { } +}; + +U_BOOT_DRIVER(npcm_host_intf) = { + .name = "npcm_host_intf", + .id = UCLASS_MISC, + .of_match = npcm_hostintf_ids, + .bind = npcm_host_intf_bind, +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 5a87db6be0..6ff00a7cbd 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -123,6 +123,7 @@ config MMC_IO_VOLTAGE config SPL_MMC_IO_VOLTAGE bool "Support IO voltage configuration in SPL" + depends on SPL_MMC help IO voltage configuration allows selecting the voltage level of the IO lines (not the level of main supply). This is required for UHS @@ -153,6 +154,7 @@ config MMC_HS400_ES_SUPPORT config SPL_MMC_HS400_ES_SUPPORT bool "enable HS400 Enhanced Strobe support in SPL" + depends on SPL_MMC help The HS400 Enhanced Strobe mode is support by some eMMC. The bus frequency is up to 200MHz. This mode does not tune the IO. @@ -166,6 +168,7 @@ config MMC_HS400_SUPPORT config SPL_MMC_HS400_SUPPORT bool "enable HS400 support in SPL" + depends on SPL_MMC select SPL_MMC_HS200_SUPPORT help The HS400 mode is support by some eMMC. The bus frequency is up to @@ -179,6 +182,7 @@ config MMC_HS200_SUPPORT config SPL_MMC_HS200_SUPPORT bool "enable HS200 support in SPL" + depends on SPL_MMC help The HS200 mode is support by some eMMC. The bus frequency is up to 200MHz. This mode requires tuning the IO. @@ -342,14 +346,6 @@ config MVEBU_MMC If unsure, say N. -config PXA_MMC_GENERIC - bool "Support for MMC controllers on PXA" - help - This selects MMC controllers on PXA. - If you are on a PXA architecture, say Y here. - - If unsure, say N. - config MMC_OMAP_HS bool "TI OMAP High Speed Multimedia Card Interface support" select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR @@ -478,7 +474,7 @@ config MMC_SDHCI_ADMA config SPL_MMC_SDHCI_ADMA bool "Support SDHCI ADMA2 in SPL" - depends on MMC_SDHCI + depends on SPL_MMC && MMC_SDHCI select MMC_SDHCI_ADMA_HELPERS help This enables support for the ADMA (Advanced DMA) defined @@ -502,6 +498,7 @@ config MMC_SDHCI_ASPEED depends on ARCH_ASPEED depends on DM_MMC depends on MMC_SDHCI + select MISC help Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed SoCs. This device is compatible with SD 3.0 and/or MMC 4.3 @@ -844,6 +841,10 @@ config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH depends on FSL_ESDHC default 1 +config ESDHC_DETECT_QUIRK + bool "QIXIS-based eSDHC quirk detection" + depends on FSL_ESDHC && FSL_QIXIS + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 9627509302..7c4243289c 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -46,7 +46,6 @@ obj-$(CONFIG_MMC_MXS) += mxsmmc.o obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o obj-$(CONFIG_MMC_OWL) += owl_mmc.o obj-$(CONFIG_MMC_PCI) += pci_mmc.o -obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_$(SPL_TPL_)SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c index 4537315719..9d79bf58cc 100644 --- a/drivers/mmc/aspeed_sdhci.c +++ b/drivers/mmc/aspeed_sdhci.c @@ -10,6 +10,7 @@ #include <malloc.h> #include <sdhci.h> #include <linux/err.h> +#include <dm/lists.h> struct aspeed_sdhci_plat { struct mmc_config cfg; @@ -26,12 +27,16 @@ static int aspeed_sdhci_probe(struct udevice *dev) int ret; ret = clk_get_by_index(dev, 0, &clk); - if (ret) + if (ret) { + debug("%s: clock get failed %d\n", __func__, ret); return ret; + } ret = clk_enable(&clk); - if (ret) + if (ret) { + debug("%s: clock enable failed %d\n", __func__, ret); goto free; + } host->name = dev->name; host->ioaddr = dev_read_addr_ptr(dev); @@ -39,6 +44,7 @@ static int aspeed_sdhci_probe(struct udevice *dev) max_clk = clk_get_rate(&clk); if (IS_ERR_VALUE(max_clk)) { ret = max_clk; + debug("%s: clock rate get failed %d\n", __func__, ret); goto err; } @@ -89,3 +95,38 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = { .priv_auto = sizeof(struct sdhci_host), .plat_auto = sizeof(struct aspeed_sdhci_plat), }; + + +static int aspeed_sdc_probe(struct udevice *parent) +{ + struct clk clk; + int ret; + + ret = clk_get_by_index(parent, 0, &clk); + if (ret) { + debug("%s: clock get failed %d\n", __func__, ret); + return ret; + } + + ret = clk_enable(&clk); + if (ret) { + debug("%s: clock enable failed %d\n", __func__, ret); + return ret; + } + + return 0; +} + +static const struct udevice_id aspeed_sdc_ids[] = { + { .compatible = "aspeed,ast2400-sd-controller" }, + { .compatible = "aspeed,ast2500-sd-controller" }, + { .compatible = "aspeed,ast2600-sd-controller" }, + { } +}; + +U_BOOT_DRIVER(aspeed_sdc_drv) = { + .name = "aspeed_sdc", + .id = UCLASS_MISC, + .of_match = aspeed_sdc_ids, + .probe = aspeed_sdc_probe, +}; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4e7bfdfaa7..b49a7b425b 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -30,6 +30,7 @@ #include <linux/iopoll.h> #include <linux/dma-mapping.h> #include <sdhci.h> +#include "../../board/freescale/common/qixis.h" DECLARE_GLOBAL_DATA_PTR; @@ -773,7 +774,7 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) struct fsl_esdhc *regs = priv->esdhc_regs; #ifdef CONFIG_ESDHC_DETECT_QUIRK - if (CONFIG_ESDHC_DETECT_QUIRK) + if (qixis_esdhc_detect_quirk()) return 1; #endif if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS) diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c deleted file mode 100644 index a0e1a76d57..0000000000 --- a/drivers/mmc/pxa_mmc_gen.c +++ /dev/null @@ -1,531 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * - * Modified to add driver model (DM) support - * Copyright (C) 2019 Marcel Ziswiler <marcel@ziswiler.com> - * - * Loosely based on the old code and Linux's PXA MMC driver - */ - -#include <common.h> -#include <asm/arch/hardware.h> -#include <asm/arch/regs-mmc.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/io.h> -#include <dm.h> -#include <dm/platform_data/pxa_mmc_gen.h> -#include <malloc.h> -#include <mmc.h> - -/* PXAMMC Generic default config for various CPUs */ -#if defined(CONFIG_CPU_PXA27X) -#define PXAMMC_CRC_SKIP -#define PXAMMC_FIFO_SIZE 32 -#define PXAMMC_MIN_SPEED 304000 -#define PXAMMC_MAX_SPEED 19500000 -#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT) -#elif defined(CONFIG_CPU_MONAHANS) -#define PXAMMC_FIFO_SIZE 32 -#define PXAMMC_MIN_SPEED 304000 -#define PXAMMC_MAX_SPEED 26000000 -#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS) -#else -#error "This CPU isn't supported by PXA MMC!" -#endif - -#define MMC_STAT_ERRORS \ - (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \ - MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \ - MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR) - -/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */ -#define PXA_MMC_TIMEOUT 100 - -struct pxa_mmc_priv { - struct pxa_mmc_regs *regs; -}; - -/* Wait for bit to be set */ -static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - unsigned int timeout = PXA_MMC_TIMEOUT; - - /* Wait for bit to be set */ - while (--timeout) { - if (readl(®s->stat) & mask) - break; - udelay(10); - } - - if (!timeout) - return -ETIMEDOUT; - - return 0; -} - -static int pxa_mmc_stop_clock(struct mmc *mmc) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - unsigned int timeout = PXA_MMC_TIMEOUT; - - /* If the clock aren't running, exit */ - if (!(readl(®s->stat) & MMC_STAT_CLK_EN)) - return 0; - - /* Tell the controller to turn off the clock */ - writel(MMC_STRPCL_STOP_CLK, ®s->strpcl); - - /* Wait until the clock are off */ - while (--timeout) { - if (!(readl(®s->stat) & MMC_STAT_CLK_EN)) - break; - udelay(10); - } - - /* The clock refused to stop, scream and die a painful death */ - if (!timeout) - return -ETIMEDOUT; - - /* The clock stopped correctly */ - return 0; -} - -static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - uint32_t cmdat) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - int ret; - - /* The card can send a "busy" response */ - if (cmd->resp_type & MMC_RSP_BUSY) - cmdat |= MMC_CMDAT_BUSY; - - /* Inform the controller about response type */ - switch (cmd->resp_type) { - case MMC_RSP_R1: - case MMC_RSP_R1b: - cmdat |= MMC_CMDAT_R1; - break; - case MMC_RSP_R2: - cmdat |= MMC_CMDAT_R2; - break; - case MMC_RSP_R3: - cmdat |= MMC_CMDAT_R3; - break; - default: - break; - } - - /* Load command and it's arguments into the controller */ - writel(cmd->cmdidx, ®s->cmd); - writel(cmd->cmdarg >> 16, ®s->argh); - writel(cmd->cmdarg & 0xffff, ®s->argl); - writel(cmdat, ®s->cmdat); - - /* Start the controller clock and wait until they are started */ - writel(MMC_STRPCL_START_CLK, ®s->strpcl); - - ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN); - if (ret) - return ret; - - /* Correct and happy end */ - return 0; -} - -static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - u32 a, b, c; - int i; - int stat; - - /* Read the controller status */ - stat = readl(®s->stat); - - /* - * Linux says: - * Did I mention this is Sick. We always need to - * discard the upper 8 bits of the first 16-bit word. - */ - a = readl(®s->res) & 0xffff; - for (i = 0; i < 4; i++) { - b = readl(®s->res) & 0xffff; - c = readl(®s->res) & 0xffff; - cmd->response[i] = (a << 24) | (b << 8) | (c >> 8); - a = c; - } - - /* The command response didn't arrive */ - if (stat & MMC_STAT_TIME_OUT_RESPONSE) { - return -ETIMEDOUT; - } else if (stat & MMC_STAT_RES_CRC_ERROR && - cmd->resp_type & MMC_RSP_CRC) { -#ifdef PXAMMC_CRC_SKIP - if (cmd->resp_type & MMC_RSP_136 && - cmd->response[0] & (1 << 31)) - printf("Ignoring CRC, this may be dangerous!\n"); - else -#endif - return -EILSEQ; - } - - /* The command response was successfully read */ - return 0; -} - -static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - u32 len; - u32 *buf = (uint32_t *)data->dest; - int size; - int ret; - - len = data->blocks * data->blocksize; - - while (len) { - /* The controller has data ready */ - if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) { - size = min(len, (uint32_t)PXAMMC_FIFO_SIZE); - len -= size; - size /= 4; - - /* Read data into the buffer */ - while (size--) - *buf++ = readl(®s->rxfifo); - } - - if (readl(®s->stat) & MMC_STAT_ERRORS) - return -EIO; - } - - /* Wait for the transmission-done interrupt */ - ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE); - if (ret) - return ret; - - return 0; -} - -static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) -{ - struct pxa_mmc_priv *priv = mmc->priv; - struct pxa_mmc_regs *regs = priv->regs; - u32 len; - u32 *buf = (uint32_t *)data->src; - int size; - int ret; - - len = data->blocks * data->blocksize; - - while (len) { - /* The controller is ready to receive data */ - if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) { - size = min(len, (uint32_t)PXAMMC_FIFO_SIZE); - len -= size; - size /= 4; - - while (size--) - writel(*buf++, ®s->txfifo); - - if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32) - writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf); - } - - if (readl(®s->stat) & MMC_STAT_ERRORS) - return -EIO; - } - - /* Wait for the transmission-done interrupt */ - ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE); - if (ret) - return ret; - - /* Wait until the data are really written to the card */ - ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE); - if (ret) - return ret; - - return 0; -} - -static int pxa_mmc_send_cmd_common(struct pxa_mmc_priv *priv, struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data) -{ - struct pxa_mmc_regs *regs = priv->regs; - u32 cmdat = 0; - int ret; - - /* Stop the controller */ - ret = pxa_mmc_stop_clock(mmc); - if (ret) - return ret; - - /* If we're doing data transfer, configure the controller accordingly */ - if (data) { - writel(data->blocks, ®s->nob); - writel(data->blocksize, ®s->blklen); - /* This delay can be optimized, but stick with max value */ - writel(0xffff, ®s->rdto); - cmdat |= MMC_CMDAT_DATA_EN; - if (data->flags & MMC_DATA_WRITE) - cmdat |= MMC_CMDAT_WRITE; - } - - /* Run in 4bit mode if the card can do it */ - if (mmc->bus_width == 4) - cmdat |= MMC_CMDAT_SD_4DAT; - - /* Execute the command */ - ret = pxa_mmc_start_cmd(mmc, cmd, cmdat); - if (ret) - return ret; - - /* Wait until the command completes */ - ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES); - if (ret) - return ret; - - /* Read back the result */ - ret = pxa_mmc_cmd_done(mmc, cmd); - if (ret) - return ret; - - /* In case there was a data transfer scheduled, do it */ - if (data) { - if (data->flags & MMC_DATA_WRITE) - pxa_mmc_do_write_xfer(mmc, data); - else - pxa_mmc_do_read_xfer(mmc, data); - } - - return 0; -} - -static int pxa_mmc_set_ios_common(struct pxa_mmc_priv *priv, struct mmc *mmc) -{ - struct pxa_mmc_regs *regs = priv->regs; - u32 tmp; - u32 pxa_mmc_clock; - - if (!mmc->clock) { - pxa_mmc_stop_clock(mmc); - return 0; - } - - /* PXA3xx can do 26MHz with special settings. */ - if (mmc->clock == 26000000) { - writel(0x7, ®s->clkrt); - return 0; - } - - /* Set clock to the card the usual way. */ - pxa_mmc_clock = 0; - tmp = mmc->cfg->f_max / mmc->clock; - tmp += tmp % 2; - - while (tmp > 1) { - pxa_mmc_clock++; - tmp >>= 1; - } - - writel(pxa_mmc_clock, ®s->clkrt); - - return 0; -} - -static int pxa_mmc_init_common(struct pxa_mmc_priv *priv, struct mmc *mmc) -{ - struct pxa_mmc_regs *regs = priv->regs; - - /* Make sure the clock are stopped */ - pxa_mmc_stop_clock(mmc); - - /* Turn off SPI mode */ - writel(0, ®s->spi); - - /* Set up maximum timeout to wait for command response */ - writel(MMC_RES_TO_MAX_MASK, ®s->resto); - - /* Mask all interrupts */ - writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ), - ®s->i_mask); - - return 0; -} - -#if !CONFIG_IS_ENABLED(DM_MMC) -static int pxa_mmc_init(struct mmc *mmc) -{ - struct pxa_mmc_priv *priv = mmc->priv; - - return pxa_mmc_init_common(priv, mmc); -} - -static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct pxa_mmc_priv *priv = mmc->priv; - - return pxa_mmc_send_cmd_common(priv, mmc, cmd, data); -} - -static int pxa_mmc_set_ios(struct mmc *mmc) -{ - struct pxa_mmc_priv *priv = mmc->priv; - - return pxa_mmc_set_ios_common(priv, mmc); -} - -static const struct mmc_ops pxa_mmc_ops = { - .send_cmd = pxa_mmc_request, - .set_ios = pxa_mmc_set_ios, - .init = pxa_mmc_init, -}; - -static struct mmc_config pxa_mmc_cfg = { - .name = "PXA MMC", - .ops = &pxa_mmc_ops, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .f_max = PXAMMC_MAX_SPEED, - .f_min = PXAMMC_MIN_SPEED, - .host_caps = PXAMMC_HOST_CAPS, - .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, -}; - -int pxa_mmc_register(int card_index) -{ - struct mmc *mmc; - struct pxa_mmc_priv *priv; - u32 reg; - int ret = -ENOMEM; - - priv = malloc(sizeof(struct pxa_mmc_priv)); - if (!priv) - goto err0; - - memset(priv, 0, sizeof(*priv)); - - switch (card_index) { - case 0: - priv->regs = (struct pxa_mmc_regs *)MMC0_BASE; - break; - case 1: - priv->regs = (struct pxa_mmc_regs *)MMC1_BASE; - break; - default: - ret = -EINVAL; - printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n", - card_index); - goto err1; - } - -#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ - reg = readl(CKEN); - reg |= CKEN12_MMC; - writel(reg, CKEN); -#else /* PXA3xx */ - reg = readl(CKENA); - reg |= CKENA_12_MMC0 | CKENA_13_MMC1; - writel(reg, CKENA); -#endif - - mmc = mmc_create(&pxa_mmc_cfg, priv); - if (!mmc) - goto err1; - - return 0; - -err1: - free(priv); -err0: - return ret; -} -#else /* !CONFIG_IS_ENABLED(DM_MMC) */ -static int pxa_mmc_probe(struct udevice *dev) -{ - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct pxa_mmc_plat *plat = dev_get_plat(dev); - struct mmc_config *cfg = &plat->cfg; - struct mmc *mmc = &plat->mmc; - struct pxa_mmc_priv *priv = dev_get_priv(dev); - u32 reg; - - upriv->mmc = mmc; - - cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - cfg->f_max = PXAMMC_MAX_SPEED; - cfg->f_min = PXAMMC_MIN_SPEED; - cfg->host_caps = PXAMMC_HOST_CAPS; - cfg->name = dev->name; - cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - - mmc->priv = priv; - - priv->regs = plat->base; - -#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ - reg = readl(CKEN); - reg |= CKEN12_MMC; - writel(reg, CKEN); -#else /* PXA3xx */ - reg = readl(CKENA); - reg |= CKENA_12_MMC0 | CKENA_13_MMC1; - writel(reg, CKENA); -#endif - - return pxa_mmc_init_common(priv, mmc); -} - -static int pxa_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct pxa_mmc_plat *plat = dev_get_plat(dev); - struct pxa_mmc_priv *priv = dev_get_priv(dev); - - return pxa_mmc_send_cmd_common(priv, &plat->mmc, cmd, data); -} - -static int pxa_mmc_set_ios(struct udevice *dev) -{ - struct pxa_mmc_plat *plat = dev_get_plat(dev); - struct pxa_mmc_priv *priv = dev_get_priv(dev); - - return pxa_mmc_set_ios_common(priv, &plat->mmc); -} - -static const struct dm_mmc_ops pxa_mmc_ops = { - .get_cd = NULL, - .send_cmd = pxa_mmc_send_cmd, - .set_ios = pxa_mmc_set_ios, -}; - -#if CONFIG_IS_ENABLED(BLK) -static int pxa_mmc_bind(struct udevice *dev) -{ - struct pxa_mmc_plat *plat = dev_get_plat(dev); - - return mmc_bind(dev, &plat->mmc, &plat->cfg); -} -#endif - -U_BOOT_DRIVER(pxa_mmc) = { -#if CONFIG_IS_ENABLED(BLK) - .bind = pxa_mmc_bind, -#endif - .id = UCLASS_MMC, - .name = "pxa_mmc", - .ops = &pxa_mmc_ops, - .priv_auto = sizeof(struct pxa_mmc_priv), - .probe = pxa_mmc_probe, -}; -#endif /* !CONFIG_IS_ENABLED(DM_MMC) */ diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index d0ab7c18c6..3d1f6e43fd 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -168,6 +168,9 @@ config STM32_FLASH This is the driver of embedded flash for some STMicroelectronics STM32 MCU. +config SAMSUNG_ONENAND + bool "Samsung OneNAND driver support" + config USE_SYS_MAX_FLASH_BANKS bool "Enable Max number of Flash memory banks" help diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 4129a33866..190300fc17 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -73,6 +73,7 @@ config PMECC_SECTOR_SIZE config SPL_GENERATE_ATMEL_PMECC_HEADER bool "Atmel PMECC Header Generation" + depends on SPL select ATMEL_NAND_HWECC select ATMEL_NAND_HW_PMECC help @@ -647,7 +648,7 @@ config SYS_NAND_U_BOOT_OFFS_REDUND config SPL_NAND_AM33XX_BCH bool "Enables SPL-NAND driver which supports ELM based" - depends on NAND_OMAP_GPMC && !OMAP34XX + depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX default y help Hardware ECC correction. This is useful for platforms which have ELM @@ -658,6 +659,7 @@ config SPL_NAND_AM33XX_BCH config SPL_NAND_DENALI bool "Support Denali NAND controller for SPL" + depends on SPL_NAND_SUPPORT help This is a small implementation of the Denali NAND controller for use on SPL. @@ -673,7 +675,7 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES config SPL_NAND_SIMPLE bool "Use simple SPL NAND driver" - depends on !SPL_NAND_AM33XX_BCH + depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT help Support for NAND boot using simple NAND drivers that expose the cmd_ctrl() interface. diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index b0e3eb607e..48a3687f27 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -745,7 +745,11 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) return ret; /* If nand_scan_ident() has not selected ecc.mode, do it now */ - if (nand->ecc.mode == NAND_ECC_NONE) { + if (nand->ecc.mode == 0 +#if CONFIG_IS_ENABLED(OF_CONTROL) + && !ofnode_read_string(nand->flash_node, "nand-ecc-mode") +#endif + ) { /* If CS Base Register selects full hardware ECC then use it */ if ((br & BR_DECC) == BR_DECC_CHK_GEN) { nand->ecc.mode = NAND_ECC_HW; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6f81257cf1..e8ece0a4a0 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -974,6 +974,22 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) return ret; } +static int nand_onfi_set_timings(struct mtd_info *mtd, struct nand_chip *chip) +{ + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) + return 0; + + u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { + chip->onfi_timing_mode_default, + }; + + return chip->onfi_set_features(mtd, chip, + ONFI_FEATURE_ADDR_TIMING_MODE, + tmode_param); +} + /** * nand_setup_data_interface - Setup the best data interface and timings * @chip: The NAND chip @@ -999,17 +1015,9 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) * Ensure the timing mode has been changed on the chip side * before changing timings on the controller side. */ - if (chip->onfi_version) { - u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { - chip->onfi_timing_mode_default, - }; - - ret = chip->onfi_set_features(mtd, chip, - ONFI_FEATURE_ADDR_TIMING_MODE, - tmode_param); - if (ret) - goto err; - } + ret = nand_onfi_set_timings(mtd, chip); + if (ret) + goto err; ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface); err: diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index f350c7e5dc..f83876c576 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -248,7 +248,7 @@ config SPI_FLASH_MTD config SPL_SPI_FLASH_MTD bool "SPI flash MTD support for SPL" - depends on SPI_FLASH + depends on SPI_FLASH && SPL help Enable the MTD support for the SPI flash layer in SPL. diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 20cd4d7fc9..67278c40e3 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = { /* EON -- en25xxx */ { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif @@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, @@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, @@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_4B_OPCODES) }, { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, @@ -208,8 +226,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_MT35XU + { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ @@ -225,6 +245,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, @@ -275,6 +296,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) }, { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, @@ -312,11 +334,19 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { + INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, + { INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { + INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, + { INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) @@ -363,6 +393,11 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { + INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) @@ -370,6 +405,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -378,6 +414,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XMC /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 84d859c21e..b671e72580 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -239,6 +239,10 @@ config E1000 <http://support.intel.com/support/network/adapter/pro100/21397.htm> +config E1000_NO_NVM + bool "Intel PRO/1000 has no NVMEM / EEPROM" + depends on E1000 + config E1000_SPI_GENERIC bool "Allow access to the Intel 8257x SPI bus" depends on E1000 @@ -308,6 +312,7 @@ config ETH_DESIGNWARE_MESON8B config ETH_DESIGNWARE_SOCFPGA select REGMAP select SYSCON + select DW_ALTDESCRIPTOR bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" depends on DM_ETH && ETH_DESIGNWARE help @@ -322,6 +327,10 @@ config ETH_DESIGNWARE_S700 This provides glue layer to use Synopsys Designware Ethernet MAC present on Actions S700 SoC. +config DW_ALTDESCRIPTOR + bool "Designware Ethernet MAC uses alternate (enhanced) descriptors" + depends on ETH_DESIGNWARE + config ETHOC bool "OpenCores 10/100 Mbps Ethernet MAC" help @@ -391,19 +400,27 @@ config FTGMAC100 offers high-priority transmit queue for QoS and CoS applications. +config SYS_DISCOVER_PHY + bool config MCFFEC bool "ColdFire Ethernet Support" depends on DM_ETH select PHYLIB + select SYS_DISCOVER_PHY help This driver supports the network interface units in the ColdFire family. +config SYS_UNIFY_CACHE + depends on MCFFEC + bool "Invalidate icache during ethernet operations" + config FSLDMAFEC bool "ColdFire DMA Ethernet Support" depends on DM_ETH select PHYLIB + select SYS_DISCOVER_PHY help This driver supports the network interface units in the ColdFire family. @@ -719,6 +736,7 @@ config MPC8XX_FEC bool "Fast Ethernet Controller on MPC8XX" depends on MPC8xx select MII + select SYS_DISCOVER_PHY help This driver implements support for the Fast Ethernet Controller on MPC8XX diff --git a/drivers/net/designware.h b/drivers/net/designware.h index ddc3d4f150..3793d55098 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -85,10 +85,8 @@ struct eth_dma_regs { #define DW_DMA_BASE_OFFSET (0x1000) -/* Default DMA Burst length */ -#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL -#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 -#endif +/* DMA Burst length */ +#define GMAC_DEFAULT_DMA_PBL 8 /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) @@ -96,7 +94,7 @@ struct eth_dma_regs { #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) -#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) +#define DMA_PBL (GMAC_DEFAULT_DMA_PBL << 8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0) diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index e103f79305..6825f9e27c 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -243,16 +243,8 @@ static int fec_init(struct udevice *dev) fecpin_setclear(info, 1); fec_halt(dev); -#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ - defined (CONFIG_SYS_DISCOVER_PHY) - mii_init(); set_fec_duplex_speed(fecp, info->dup_spd); -#else -#ifndef CONFIG_SYS_DISCOVER_PHY - set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED); -#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ -#endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ fecp->eimr = 0; diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index cef9eecac2..4dd848932b 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -278,17 +278,9 @@ int mcffec_init(struct udevice *dev) fecpin_setclear(info, 1); fec_reset(info); -#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ - defined (CONFIG_SYS_DISCOVER_PHY) - mii_init(); set_fec_duplex_speed(fecp, info->dup_spd); -#else -#ifndef CONFIG_SYS_DISCOVER_PHY - set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED); -#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ -#endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ fecp->eimr = 0; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index fd2203420c..436acca898 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -48,6 +48,10 @@ config PCI_REGION_MULTI_ENTRY region type. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on the PCI bus. +config PCI_CONFIG_HOST_BRIDGE + bool "Configure PCI host bridges" + default y if X86 + config PCI_MAP_SYSTEM_MEMORY bool "Map local system memory from a virtual base address" depends on MIPS @@ -81,6 +85,10 @@ config PCI_ARID support on PCI devices. This helps to skip some devices in BDF scan that are not present. +config PCI_SCAN_SHOW + bool "Show PCI devices during startup" + depends on PCIE_IMX + config PCIE_ECAM_GENERIC bool "Generic ECAM-based PCI host controller support" help @@ -97,6 +105,10 @@ config PCIE_ECAM_SYNQUACER Note that this must be configured when boot because Linux driver expects the PCIe RC has been configured in the bootloader. +config PCI_GT64120 + bool "GT64120 PCI support" + depends on MIPS + config PCI_PHYTIUM bool "Phytium PCIe support" help @@ -121,8 +133,12 @@ config PCIE_DW_SIFIVE Say Y here if you want to enable PCIe controller support on FU740. +config SYS_FSL_PCI_VER_3_X + bool + config PCIE_FSL bool "FSL PowerPC PCIe support" + select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240 help Say Y here if you want to enable PCIe controller support on FSL PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. @@ -134,6 +150,10 @@ config PCI_MPC85XX Say Y here if you want to enable PCI controller support on FSL PowerPC MPC85xx SoC. +config PCI_MSC01 + bool "MSC01 PCI support" + depends on TARGET_MALTA + config PCI_RCAR_GEN2 bool "Renesas RCar Gen2 PCIe driver" depends on RCAR_32 @@ -159,6 +179,12 @@ config PCI_SANDBOX the device tree but the normal PCI scan technique is used to find then. +config SH7751_PCI + bool "SH7751 PCI controller support" + depends on SH + help + SuperH PCI Bridge Configuration + config PCI_TEGRA bool "Tegra PCI support" depends on ARCH_TEGRA @@ -254,6 +280,10 @@ config FSL_PCIE_EP_COMPAT This compatible is used to find pci controller ep node in Kernel DT to complete fixup. +config PCIE_IMX + bool "i.MX PCIe support" + depends on ARCH_MX6 + config PCIE_INTEL_FPGA bool "Intel FPGA PCIe support" help diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 04f623652f..cfcd6fd6c5 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -20,7 +20,6 @@ obj-$(CONFIG_PCIE_IMX) += pcie_imx.o obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o -obj-$(CONFIG_SH4_PCI) += pci_sh4.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o diff --git a/drivers/pci/pci_sh4.c b/drivers/pci/pci_sh4.c deleted file mode 100644 index aac9be055e..0000000000 --- a/drivers/pci/pci_sh4.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SH4 PCI Controller (PCIC) for U-Boot. - * (C) Dustin McIntire (dustin@sensoria.com) - * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> - * - * u-boot/arch/sh/cpu/sh4/pci-sh4.c - */ - -#include <common.h> -#include <linux/delay.h> - -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <pci.h> - -int pci_sh4_init(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->region_count = 0; - hose->last_busno = 0xff; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - hose->region_count++; - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - hose->region_count++; - -#if defined(CONFIG_PCI_SYS_BUS) - /* PCI System Memory space */ - pci_set_region(hose->regions + 2, - CONFIG_PCI_SYS_BUS, - CONFIG_PCI_SYS_PHYS, - CONFIG_PCI_SYS_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - hose->region_count++; -#endif - - udelay(1000); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - pci_sh4_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - pci_sh4_write_config_dword); - - pci_register_hose(hose); - - udelay(1000); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - hose->last_busno = pci_hose_scan(hose); - return 0; -} - -int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) -{ - return 0; -} - -#ifdef CONFIG_PCI_SCAN_SHOW -int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) -{ - return 1; -} -#endif /* CONFIG_PCI_SCAN_SHOW */ diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c01d9e09b9..4a3856d3c2 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -274,6 +274,13 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout. +config PHY_NPCM_USB + bool "Nuvoton NPCM USB PHY support" + depends on PHY + depends on ARCH_NPCM + help + Support the USB PHY in NPCM SoCs + config PHY_IMX8MQ_USB bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver" depends on PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index bf9b40932f..d95439c425 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ diff --git a/drivers/phy/phy-npcm-usb.c b/drivers/phy/phy-npcm-usb.c new file mode 100644 index 0000000000..24eba66554 --- /dev/null +++ b/drivers/phy/phy-npcm-usb.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <dm.h> +#include <generic-phy.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/delay.h> + +/* GCR Register Offsets */ +#define GCR_INTCR3 0x9C +#define GCR_USB1PHYCTL 0x140 +#define GCR_USB2PHYCTL 0x144 +#define GCR_USB3PHYCTL 0x148 + +/* USBnPHYCTL bit fields */ +#define PHYCTL_RS BIT(28) + +#define USBPHY2SW GENMASK(13, 12) +#define USBPHY3SW GENMASK(15, 14) + +#define USBPHY2SW_DEV9_PHY1 FIELD_PREP(USBPHY2SW, 0) +#define USBPHY2SW_HOST1 FIELD_PREP(USBPHY2SW, 1) +#define USBPHY2SW_DEV9_PHY2 FIELD_PREP(USBPHY2SW, 3) +#define USBPHY3SW_DEV8_PHY1 FIELD_PREP(USBPHY3SW, 0) +#define USBPHY3SW_HOST2 FIELD_PREP(USBPHY3SW, 1) +#define USBPHY3SW_DEV8_PHY3 FIELD_PREP(USBPHY3SW, 3) + +enum controller_id { + UDC0_7, + UDC8, + UDC9, + USBH1, + USBH2, +}; + +enum phy_id { + PHY1 = 1, + PHY2, + PHY3, +}; + +/* Phy Switch Settings */ +#define USBDPHY1 ((PHY1 << 8) | UDC0_7) /* Connect UDC0~7 to PHY1 */ +#define USBD8PHY1 ((PHY1 << 8) | UDC8) /* Connect UDC8 to PHY1 */ +#define USBD9PHY1 ((PHY1 << 8) | UDC9) /* Connect UDC9 to PHY1 */ +#define USBD9PHY2 ((PHY2 << 8) | UDC9) /* Connect UDC9 to PHY2 */ +#define USBH1PHY2 ((PHY2 << 8) | USBH1) /* Connect USBH1 to PHY2 */ +#define USBD8PHY3 ((PHY3 << 8) | UDC8) /* Connect UDC8 to PHY3 */ +#define USBH2PHY3 ((PHY3 << 8) | USBH2) /* Connect USBH2 to PHY3 */ + +struct npcm_usbphy { + struct regmap *syscon; + u8 id; + u16 phy_switch; /* (phy_id << 8) | controller_id */ +}; + +static int npcm_usb_phy_init(struct phy *phy) +{ + struct npcm_usbphy *priv = dev_get_priv(phy->dev); + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(phy->dev, 0, &reset); + if (ret && ret != -ENOENT && ret != -ENOTSUPP) { + dev_err(phy->dev, "can't get phy reset ctrl (err %d)", ret); + return ret; + } + + /* setup PHY switch */ + switch (priv->phy_switch) { + case USBD8PHY1: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW, + USBPHY3SW_DEV8_PHY1); + break; + case USBD8PHY3: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW, + USBPHY3SW_DEV8_PHY3); + break; + case USBD9PHY1: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW, + USBPHY2SW_DEV9_PHY1); + break; + case USBD9PHY2: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW, + USBPHY2SW_DEV9_PHY2); + break; + case USBH1PHY2: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW, + USBPHY2SW_HOST1); + break; + case USBH2PHY3: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW, + USBPHY3SW_HOST2); + break; + default: + break; + } + /* reset phy */ + if (reset_valid(&reset)) + reset_assert(&reset); + + /* Wait for PHY clocks to stablize for 50us or more */ + udelay(100); + + /* release phy from reset */ + if (reset_valid(&reset)) + reset_deassert(&reset); + + /* PHY RS bit should be set after reset */ + switch (priv->id) { + case PHY1: + regmap_update_bits(priv->syscon, GCR_USB1PHYCTL, PHYCTL_RS, PHYCTL_RS); + break; + case PHY2: + regmap_update_bits(priv->syscon, GCR_USB2PHYCTL, PHYCTL_RS, PHYCTL_RS); + break; + case PHY3: + regmap_update_bits(priv->syscon, GCR_USB3PHYCTL, PHYCTL_RS, PHYCTL_RS); + break; + default: + break; + } + + return 0; +} + +static int npcm_usb_phy_exit(struct phy *phy) +{ + struct npcm_usbphy *priv = dev_get_priv(phy->dev); + + /* set PHY switch to default state */ + switch (priv->phy_switch) { + case USBD8PHY1: + case USBD8PHY3: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW, + USBPHY3SW_HOST2); + break; + case USBD9PHY1: + case USBD9PHY2: + regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW, + USBPHY2SW_HOST1); + break; + default: + break; + } + return 0; +} + +static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args) +{ + struct npcm_usbphy *priv = dev_get_priv(phy->dev); + u16 phy_switch; + + if (args->args_count < 1 || args->args[0] > USBH2) + return -EINVAL; + + phy_switch = (priv->id << 8) | args->args[0]; + switch (phy_switch) { + case USBD9PHY1: + case USBH2PHY3: + case USBD8PHY3: + if (!IS_ENABLED(CONFIG_ARCH_NPCM8XX)) + return -EINVAL; + case USBDPHY1: + case USBD8PHY1: + case USBD9PHY2: + case USBH1PHY2: + priv->phy_switch = phy_switch; + return 0; + default: + return -EINVAL; + } +} + +static int npcm_usb_phy_probe(struct udevice *dev) +{ + struct npcm_usbphy *priv = dev_get_priv(dev); + + priv->syscon = syscon_regmap_lookup_by_phandle(dev->parent, "syscon"); + if (IS_ERR(priv->syscon)) { + dev_err(dev, "%s: unable to get syscon\n", __func__); + return PTR_ERR(priv->syscon); + } + priv->id = dev_read_u32_default(dev, "reg", -1); + + return 0; +} + +static const struct udevice_id npcm_phy_ids[] = { + { .compatible = "nuvoton,npcm845-usb-phy",}, + { .compatible = "nuvoton,npcm750-usb-phy",}, + { } +}; + +static struct phy_ops npcm_phy_ops = { + .init = npcm_usb_phy_init, + .exit = npcm_usb_phy_exit, + .of_xlate = npcm_usb_phy_xlate, +}; + +U_BOOT_DRIVER(npcm_phy) = { + .name = "npcm-usb-phy", + .id = UCLASS_PHY, + .of_match = npcm_phy_ids, + .ops = &npcm_phy_ops, + .probe = npcm_usb_phy_probe, + .priv_auto = sizeof(struct npcm_usbphy), +}; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 2c20dc7c83..bc47cf144d 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -29,6 +29,7 @@ config POWER_LEGACY config SPL_POWER_LEGACY bool "Legacy power support in SPL" + depends on SPL && !SPL_DM_PMIC default y if POWER_LEGACY help Note: This is a legacy option. Use SPL_DM_PMIC instead. @@ -425,6 +426,10 @@ config POWER_MT6323 This adds poweroff driver for mt6323 this pmic is used on mt7623 / Bananapi R2 +config PALMAS_POWER + bool "Palmas power support" + depends on OMAP54XX + config POWER_I2C bool "I2C-based power control for legacy power" depends on POWER_LEGACY diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig index fcd50e36ca..629acb0714 100644 --- a/drivers/power/acpi_pmc/Kconfig +++ b/drivers/power/acpi_pmc/Kconfig @@ -8,6 +8,7 @@ config ACPI_PMC config SPL_ACPI_PMC bool "Power Manager (x86 PMC) support in SPL" + depends on SPL default y if ACPI_PMC help Enable support for an x86-style power-management controller which @@ -17,6 +18,7 @@ config SPL_ACPI_PMC config TPL_ACPI_PMC bool "Power Manager (x86 PMC) support in TPL" + depends on TPL default y if ACPI_PMC help Enable support for an x86-style power-management controller which diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index d6cea8ec66..c519e066ef 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -55,7 +55,7 @@ config DM_REGULATOR_BD71837 config SPL_DM_REGULATOR_BD71837 bool "Enable Driver Model for ROHM BD71837/BD71847 regulators in SPL" - depends on DM_REGULATOR_BD71837 + depends on DM_REGULATOR_BD71837 && SPL help This config enables implementation of driver-model regulator uclass features for regulators on ROHM BD71837 and BD71847 in SPL. @@ -70,7 +70,7 @@ config DM_REGULATOR_PCA9450 config SPL_DM_REGULATOR_PCA9450 bool "Enable Driver Model for NXP PCA9450 regulators in SPL" - depends on DM_REGULATOR_PCA9450 + depends on DM_REGULATOR_PCA9450 && SPL help This config enables implementation of driver-model regulator uclass features for regulators on ROHM PCA9450 in SPL. @@ -115,7 +115,7 @@ config REGULATOR_PWM config SPL_REGULATOR_PWM bool "Enable Driver for PWM regulators in SPL" - depends on REGULATOR_PWM + depends on REGULATOR_PWM && SPL help This config enables implementation of driver-model regulator uclass features for PWM regulators in SPL. @@ -163,7 +163,7 @@ config DM_REGULATOR_FIXED config SPL_DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value in SPL" - depends on DM_REGULATOR_FIXED + depends on DM_REGULATOR_FIXED && SPL select SPL_DM_REGULATOR_COMMON ---help--- This config enables implementation of driver-model regulator uclass @@ -345,7 +345,7 @@ config SPL_DM_REGULATOR_STPMIC1 config SPL_DM_REGULATOR_PALMAS bool "Enable driver for PALMAS PMIC regulators" - depends on SPL_PMIC_PALMAS + depends on SPL_PMIC_PALMAS help This enables implementation of driver-model regulator uclass features for REGULATOR PALMAS and the family of PALMAS PMICs. @@ -353,7 +353,7 @@ config SPL_DM_REGULATOR_PALMAS config SPL_DM_REGULATOR_LP87565 bool "Enable driver for LP87565 PMIC regulators" - depends on SPL_PMIC_LP87565 + depends on SPL_PMIC_LP87565 help This enables implementation of driver-model regulator uclass features for REGULATOR LP87565 and the family of LP87565 PMICs. diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cb54e67fae..8fd5a2e205 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -84,6 +84,11 @@ config PWM_SANDBOX useful. The PWM can be enabled but is not connected to any outputs so this is not very useful. +config PWM_S5P + bool "Enable non-DM support for S5P PWM" + depends on (S5P || ARCH_NEXELL) + default y + config PWM_SIFIVE bool "Enable support for SiFive PWM" depends on DM_PWM diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index a4f9f1aad2..7c346180ba 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -19,7 +19,7 @@ config SPL_RAM config TPL_RAM bool "Enable RAM support in TPL" - depends on RAM + depends on RAM && TPL help The RAM subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use RAM drivers in diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c index 0a1dd236af..d9cecf3a72 100644 --- a/drivers/reset/reset-ast2500.c +++ b/drivers/reset/reset-ast2500.c @@ -48,6 +48,24 @@ static int ast2500_reset_deassert(struct reset_ctl *reset_ctl) return 0; } +static int ast2500_reset_status(struct reset_ctl *reset_ctl) +{ + struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ast2500_scu *scu = priv->scu; + int status; + + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id); + + if (reset_ctl->id < 32) + status = BIT(reset_ctl->id) & readl(&scu->sysreset_ctrl1); + else + status = BIT(reset_ctl->id - 32) & readl(&scu->sysreset_ctrl2); + + return !!status; +} + + + static int ast2500_reset_probe(struct udevice *dev) { int rc; @@ -79,6 +97,7 @@ static const struct udevice_id ast2500_reset_ids[] = { struct reset_ops ast2500_reset_ops = { .rst_assert = ast2500_reset_assert, .rst_deassert = ast2500_reset_deassert, + .rst_status = ast2500_reset_status, }; U_BOOT_DRIVER(ast2500_reset) = { diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c index 985235a3ac..1732a450ef 100644 --- a/drivers/reset/reset-ast2600.c +++ b/drivers/reset/reset-ast2600.c @@ -47,6 +47,22 @@ static int ast2600_reset_deassert(struct reset_ctl *reset_ctl) return 0; } +static int ast2600_reset_status(struct reset_ctl *reset_ctl) +{ + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ast2600_scu *scu = priv->scu; + int status; + + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id); + + if (reset_ctl->id < 32) + status = BIT(reset_ctl->id) & readl(&scu->modrst_ctrl1); + else + status = BIT(reset_ctl->id - 32) & readl(&scu->modrst_ctrl2); + + return !!status; +} + static int ast2600_reset_probe(struct udevice *dev) { int rc; @@ -78,6 +94,7 @@ static const struct udevice_id ast2600_reset_ids[] = { struct reset_ops ast2600_reset_ops = { .rst_assert = ast2600_reset_assert, .rst_deassert = ast2600_reset_deassert, + .rst_status = ast2600_reset_status, }; U_BOOT_DRIVER(ast2600_reset) = { diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index f585622fdb..de02e08a29 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -940,12 +940,6 @@ config OWL_SERIAL serial port, say Y to this option. If unsure, say N. Single baudrate is supported in current implementation (115200). -config PXA_SERIAL - bool "PXA serial port support" - help - If you have a machine based on a Marvell XScale PXA2xx CPU you - can enable its onboard serial ports by enabling this option. - config HTIF_CONSOLE bool "RISC-V HTIF console support" depends on DM_SERIAL && 64BIT diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 51de06a78c..eb7b8f23ee 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -43,7 +43,6 @@ obj-$(CONFIG_MCFUART) += serial_mcf.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o obj-$(CONFIG_MXC_UART) += serial_mxc.o -obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o obj-$(CONFIG_MESON_SERIAL) += serial_meson.o obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 78bfe6281c..47bad6f8e2 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -328,6 +328,10 @@ static inline void _debug_uart_init(void) struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); int baud_divisor; + /* Wait until tx buffer is empty */ + while (!(serial_din(&com_port->lsr) & UART_LSR_TEMT)) + ; + /* * We copy the code from above because it is already horribly messy. * Trying to refactor to nicely remove the duplication doesn't seem diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c deleted file mode 100644 index aa928efdc0..0000000000 --- a/drivers/serial/serial_pxa.c +++ /dev/null @@ -1,342 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * Modified to add driver model (DM) support - * (C) Copyright 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com> - */ - -#include <common.h> -#include <hang.h> -#include <asm/arch/pxa-regs.h> -#include <asm/arch/regs-uart.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <dm.h> -#include <dm/platform_data/serial_pxa.h> -#include <linux/compiler.h> -#include <serial.h> -#include <watchdog.h> - -DECLARE_GLOBAL_DATA_PTR; - -static uint32_t pxa_uart_get_baud_divider(int baudrate) -{ - return 921600 / baudrate; -} - -static void pxa_uart_toggle_clock(uint32_t uart_index, int enable) -{ - uint32_t clk_reg, clk_offset, reg; - - clk_reg = UART_CLK_REG; - clk_offset = UART_CLK_BASE << uart_index; - - reg = readl(clk_reg); - - if (enable) - reg |= clk_offset; - else - reg &= ~clk_offset; - - writel(reg, clk_reg); -} - -/* - * Enable clock and set baud rate, parity etc. - */ -void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate) -{ - uint32_t divider = pxa_uart_get_baud_divider(baudrate); - if (!divider) - hang(); - - - pxa_uart_toggle_clock(port, 1); - - /* Disable interrupts and FIFOs */ - writel(0, &uart_regs->ier); - writel(0, &uart_regs->fcr); - - /* Set baud rate */ - writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr); - writel(divider & 0xff, &uart_regs->dll); - writel(divider >> 8, &uart_regs->dlh); - writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr); - - /* Enable UART */ - writel(IER_UUE, &uart_regs->ier); -} - -#ifndef CONFIG_DM_SERIAL -static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index) -{ - switch (uart_index) { - case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE; - case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE; - case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE; - default: - return NULL; - } -} - -/* - * Enable clock and set baud rate, parity etc. - */ -void pxa_setbrg_dev(uint32_t uart_index) -{ - struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - panic("Failed getting UART registers\n"); - - pxa_setbrg_common(uart_regs, uart_index, gd->baudrate); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -int pxa_init_dev(unsigned int uart_index) -{ - pxa_setbrg_dev(uart_index); - return 0; -} - -/* - * Output a single byte to the serial port. - */ -void pxa_putc_dev(unsigned int uart_index, const char c) -{ - struct pxa_uart_regs *uart_regs; - - /* If \n, also do \r */ - if (c == '\n') - pxa_putc_dev(uart_index, '\r'); - - uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - hang(); - - while (!(readl(&uart_regs->lsr) & LSR_TEMT)) - WATCHDOG_RESET(); - writel(c, &uart_regs->thr); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int pxa_tstc_dev(unsigned int uart_index) -{ - struct pxa_uart_regs *uart_regs; - - uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - return -1; - - return readl(&uart_regs->lsr) & LSR_DR; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int pxa_getc_dev(unsigned int uart_index) -{ - struct pxa_uart_regs *uart_regs; - - uart_regs = pxa_uart_index_to_regs(uart_index); - if (!uart_regs) - return -1; - - while (!(readl(&uart_regs->lsr) & LSR_DR)) - WATCHDOG_RESET(); - return readl(&uart_regs->rbr) & 0xff; -} - -void pxa_puts_dev(unsigned int uart_index, const char *s) -{ - while (*s) - pxa_putc_dev(uart_index, *s++); -} - -#define pxa_uart(uart, UART) \ - int uart##_init(void) \ - { \ - return pxa_init_dev(UART##_INDEX); \ - } \ - \ - void uart##_setbrg(void) \ - { \ - return pxa_setbrg_dev(UART##_INDEX); \ - } \ - \ - void uart##_putc(const char c) \ - { \ - return pxa_putc_dev(UART##_INDEX, c); \ - } \ - \ - void uart##_puts(const char *s) \ - { \ - return pxa_puts_dev(UART##_INDEX, s); \ - } \ - \ - int uart##_getc(void) \ - { \ - return pxa_getc_dev(UART##_INDEX); \ - } \ - \ - int uart##_tstc(void) \ - { \ - return pxa_tstc_dev(UART##_INDEX); \ - } \ - -#define pxa_uart_desc(uart) \ - struct serial_device serial_##uart##_device = \ - { \ - .name = "serial_"#uart, \ - .start = uart##_init, \ - .stop = NULL, \ - .setbrg = uart##_setbrg, \ - .getc = uart##_getc, \ - .tstc = uart##_tstc, \ - .putc = uart##_putc, \ - .puts = uart##_puts, \ - }; - -#define pxa_uart_multi(uart, UART) \ - pxa_uart(uart, UART) \ - pxa_uart_desc(uart) - -#if defined(CONFIG_HWUART) - pxa_uart_multi(hwuart, HWUART) -#endif -#if defined(CONFIG_STUART) - pxa_uart_multi(stuart, STUART) -#endif -#if defined(CONFIG_FFUART) - pxa_uart_multi(ffuart, FFUART) -#endif -#if defined(CONFIG_BTUART) - pxa_uart_multi(btuart, BTUART) -#endif - -__weak struct serial_device *default_serial_console(void) -{ -#if CONFIG_CONS_INDEX == 1 - return &serial_hwuart_device; -#elif CONFIG_CONS_INDEX == 2 - return &serial_stuart_device; -#elif CONFIG_CONS_INDEX == 3 - return &serial_ffuart_device; -#elif CONFIG_CONS_INDEX == 4 - return &serial_btuart_device; -#else -#error "Bad CONFIG_CONS_INDEX." -#endif -} - -void pxa_serial_initialize(void) -{ -#if defined(CONFIG_FFUART) - serial_register(&serial_ffuart_device); -#endif -#if defined(CONFIG_BTUART) - serial_register(&serial_btuart_device); -#endif -#if defined(CONFIG_STUART) - serial_register(&serial_stuart_device); -#endif -} -#endif /* CONFIG_DM_SERIAL */ - -#ifdef CONFIG_DM_SERIAL -static int pxa_serial_probe(struct udevice *dev) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - - pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port, - plat->baudrate); - return 0; -} - -static int pxa_serial_putc(struct udevice *dev, const char ch) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; - - /* Wait for last character to go. */ - if (!(readl(&uart_regs->lsr) & LSR_TEMT)) - return -EAGAIN; - - writel(ch, &uart_regs->thr); - - return 0; -} - -static int pxa_serial_getc(struct udevice *dev) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; - - /* Wait for a character to arrive. */ - if (!(readl(&uart_regs->lsr) & LSR_DR)) - return -EAGAIN; - - return readl(&uart_regs->rbr) & 0xff; -} - -int pxa_serial_setbrg(struct udevice *dev, int baudrate) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; - int port = plat->port; - - pxa_setbrg_common(uart_regs, port, baudrate); - - return 0; -} - -static int pxa_serial_pending(struct udevice *dev, bool input) -{ - struct pxa_serial_plat *plat = dev_get_plat(dev); - struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; - - if (input) - return readl(&uart_regs->lsr) & LSR_DR ? 1 : 0; - else - return readl(&uart_regs->lsr) & LSR_TEMT ? 0 : 1; - - return 0; -} - -static const struct dm_serial_ops pxa_serial_ops = { - .putc = pxa_serial_putc, - .pending = pxa_serial_pending, - .getc = pxa_serial_getc, - .setbrg = pxa_serial_setbrg, -}; - -U_BOOT_DRIVER(serial_pxa) = { - .name = "serial_pxa", - .id = UCLASS_SERIAL, - .probe = pxa_serial_probe, - .ops = &pxa_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; -#endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 05b3c01e5f..0d89fc085f 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -13,8 +13,6 @@ #include <usbdevice.h> #if defined(CONFIG_PPC) #include <usb/mpc8xx_udc.h> -#elif defined(CONFIG_CPU_PXA27X) -#include <usb/pxa27x_udc.h> #elif defined(CONFIG_DW_UDC) #include <usb/designware_udc.h> #elif defined(CONFIG_CI_UDC) diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 42344145f9..b1e7c4ae5f 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -64,8 +64,8 @@ static char *j721e_rev_string_map[] = { "1.0", "1.1", }; -static char *am65x_rev_string_map[] = { - "1.0", "2.0", +static char *typical_rev_string_map[] = { + "1.0", "2.0", "3.0", }; static const char *get_rev_string(u32 idreg) @@ -82,16 +82,10 @@ static const char *get_rev_string(u32 idreg) goto bail; return j721e_rev_string_map[rev]; - case AM65X: - if (rev > ARRAY_SIZE(am65x_rev_string_map)) - goto bail; - return am65x_rev_string_map[rev]; - - case AM64X: - case J7200: default: - if (!rev) - return "1.0"; + if (rev > ARRAY_SIZE(typical_rev_string_map)) + goto bail; + return typical_rev_string_map[rev]; }; bail: diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index 8d674bcb4f..c1edef4436 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -23,6 +23,7 @@ #define DA7219_ACPI_HID "DLGS7219" +__maybe_unused static int da7219_acpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) { @@ -171,10 +172,12 @@ static int da7219_acpi_setup_nhlt(const struct udevice *dev, #endif struct acpi_ops da7219_acpi_ops = { +#ifdef CONFIG_ACPIGEN .fill_ssdt = da7219_acpi_fill_ssdt, #ifdef CONFIG_X86 .setup_nhlt = da7219_acpi_setup_nhlt, #endif +#endif }; static const struct udevice_id da7219_ids[] = { diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index a2088f0301..bdf6dc236e 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -38,6 +38,7 @@ static int max98357a_of_to_plat(struct udevice *dev) return 0; } +__maybe_unused static int max98357a_acpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) { @@ -137,10 +138,12 @@ static int max98357a_acpi_setup_nhlt(const struct udevice *dev, #endif struct acpi_ops max98357a_acpi_ops = { +#ifdef CONFIG_ACPIGEN .fill_ssdt = max98357a_acpi_fill_ssdt, #ifdef CONFIG_X86 .setup_nhlt = max98357a_acpi_setup_nhlt, #endif +#endif }; static const struct audio_codec_ops max98357a_ops = { diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e48d72d744..766d5636c0 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -136,6 +136,14 @@ config CQSPI_REF_CLK int "Cadence QSPI reference clock value in Hz" depends on HAS_CQSPI_REF_CLK +config CADENCE_OSPI_VERSAL + bool "Configure Versal OSPI" + depends on ARCH_VERSAL && CADENCE_QSPI + imply DM_GPIO + help + This option is used to enable Versal OSPI DMA operations which + are used for ospi flash read using cadence qspi controller. + config CF_SPI bool "ColdFire SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8755408e62..4de77c260a 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_$(SPL_TPL_)DM_SPI obj-y += spi-uclass.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o +obj-$(CONFIG_CADENCE_OSPI_VERSAL) += cadence_ospi_versal.o obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o obj-$(CONFIG_SPI_MEM) += spi-mem.o diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c new file mode 100644 index 0000000000..52bcad053f --- /dev/null +++ b/drivers/spi/cadence_ospi_versal.c @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Xilinx + * + * Cadence QSPI controller DMA operations + */ + +#include <clk.h> +#include <common.h> +#include <memalign.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/cache.h> +#include <cpu_func.h> +#include <zynqmp_firmware.h> +#include <asm/arch/hardware.h> +#include "cadence_qspi.h" +#include <dt-bindings/power/xlnx-versal-power.h> + +#define CMD_4BYTE_READ 0x13 +#define CMD_4BYTE_FAST_READ 0x0C + +int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data; + u8 opcode, addr_bytes, *rxbuf, dummy_cycles; + + n_rx = op->data.nbytes; + rxbuf = op->data.buf.in; + rx_rem = n_rx % 4; + bytes_to_dma = n_rx - rx_rem; + + if (bytes_to_dma) { + cadence_qspi_apb_enable_linear_mode(false); + reg = readl(plat->regbase + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_ENBL_DMA; + writel(reg, plat->regbase + CQSPI_REG_CONFIG); + + writel(bytes_to_dma, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); + + writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE, + plat->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE); + writel(CQSPI_DFLT_DMA_PERIPH_CFG, + plat->regbase + CQSPI_REG_DMA_PERIPH_CFG); + writel((unsigned long)rxbuf, plat->regbase + + CQSPI_DMA_DST_ADDR_REG); + writel(plat->trigger_address, plat->regbase + + CQSPI_DMA_SRC_RD_ADDR_REG); + writel(bytes_to_dma, plat->regbase + + CQSPI_DMA_DST_SIZE_REG); + flush_dcache_range((unsigned long)rxbuf, + (unsigned long)rxbuf + bytes_to_dma); + writel(CQSPI_DFLT_DST_CTRL_REG_VAL, + plat->regbase + CQSPI_DMA_DST_CTRL_REG); + + /* Start the indirect read transfer */ + writel(CQSPI_REG_INDIRECTRD_START, plat->regbase + + CQSPI_REG_INDIRECTRD); + /* Wait for dma to complete transfer */ + ret = cadence_qspi_apb_wait_for_dma_cmplt(plat); + if (ret) + return ret; + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + + CQSPI_REG_INDIRECTRD); + rxbuf += bytes_to_dma; + } + + if (rx_rem) { + reg = readl(plat->regbase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENBL_DMA; + writel(reg, plat->regbase + CQSPI_REG_CONFIG); + + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); + reg += bytes_to_dma; + writel(reg, plat->regbase + CQSPI_REG_CMDADDRESS); + + addr_bytes = readl(plat->regbase + CQSPI_REG_SIZE) & + CQSPI_REG_SIZE_ADDRESS_MASK; + + opcode = CMD_4BYTE_FAST_READ; + dummy_cycles = 8; + writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode, + plat->regbase + CQSPI_REG_RD_INSTR); + + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; + reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + dummy_cycles = (readl(plat->regbase + CQSPI_REG_RD_INSTR) >> + CQSPI_REG_RD_INSTR_DUMMY_LSB) & + CQSPI_REG_RD_INSTR_DUMMY_MASK; + reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) << + CQSPI_REG_CMDCTRL_DUMMY_LSB; + reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + ret = cadence_qspi_apb_exec_flash_cmd(plat->regbase, reg); + if (ret) + return ret; + + data = readl(plat->regbase + CQSPI_REG_CMDREADDATALOWER); + memcpy(rxbuf, &data, rx_rem); + } + + return 0; +} + +int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat) +{ + u32 timeout = CQSPI_DMA_TIMEOUT; + + while (!(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG) & + CQSPI_DMA_DST_I_STS_DONE) && timeout--) + udelay(1); + + if (!timeout) { + printf("DMA timeout\n"); + return -ETIMEDOUT; + } + + writel(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG), + plat->regbase + CQSPI_DMA_DST_I_STS_REG); + return 0; +} + +#if defined(CONFIG_DM_GPIO) +int cadence_spi_versal_flash_reset(struct udevice *dev) +{ + struct gpio_desc gpio; + u32 reset_gpio; + int ret; + + /* request gpio and set direction as output set to 1 */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + printf("%s: unable to reset ospi flash device", __func__); + return ret; + } + + reset_gpio = PMIO_NODE_ID_BASE + gpio.offset; + + /* Request for pin */ + xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL); + + /* Enable hysteresis in cmos receiver */ + xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, + PM_PINCTRL_CONFIG_SCHMITT_CMOS, + PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL); + + /* Disable Tri-state */ + xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, + PM_PINCTRL_CONFIG_TRI_STATE, + PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL); + udelay(1); + + /* Set value 0 to pin */ + dm_gpio_set_value(&gpio, 0); + udelay(1); + + /* Set value 1 to pin */ + dm_gpio_set_value(&gpio, 1); + udelay(1); + + return 0; +} +#else +int cadence_spi_versal_flash_reset(struct udevice *dev) +{ + /* CRP WPROT */ + writel(0, WPROT_CRP); + /* GPIO Reset */ + writel(0, RST_GPIO); + + /* disable IOU write protection */ + writel(0, WPROT_LPD_MIO); + + /* set direction as output */ + writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)), + BOOT_MODE_POR_0); + + /* Data output enable */ + writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)), + BOOT_MODE_POR_1); + + /* IOU SLCR write enable */ + writel(0, WPROT_PMC_MIO); + + /* set MIO as GPIO */ + writel(0x60, MIO_PIN_12); + + /* Set value 1 to pin */ + writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + /* Disable Tri-state */ + writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI); + udelay(1); + + /* Set value 0 to pin */ + writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + /* Set value 1 to pin */ + writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + return 0; +} +#endif + +void cadence_qspi_apb_enable_linear_mode(bool enable) +{ + if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) { + if (enable) + /* ahb read mode */ + xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI, + IOCTL_OSPI_MUX_SELECT, + PM_OSPI_MUX_SEL_LINEAR, 0, NULL); + else + /* DMA mode */ + xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI, + IOCTL_OSPI_MUX_SELECT, + PM_OSPI_MUX_SEL_DMA, 0, NULL); + } else { + if (enable) + writel(readl(VERSAL_AXI_MUX_SEL) | + VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); + else + writel(readl(VERSAL_AXI_MUX_SEL) & + ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); + } +} diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 7209bb43a7..907f5dadc4 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -18,7 +18,9 @@ #include <linux/err.h> #include <linux/errno.h> #include <linux/sizes.h> +#include <zynqmp_firmware.h> #include "cadence_qspi.h" +#include <dt-bindings/power/xlnx-versal-power.h> #define NSEC_PER_SEC 1000000000L @@ -27,6 +29,17 @@ #define CQSPI_READ 2 #define CQSPI_WRITE 3 +__weak int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + return 0; +} + +__weak int cadence_qspi_versal_flash_reset(struct udevice *dev) +{ + return 0; +} + static int cadence_spi_write_speed(struct udevice *bus, uint hz) { struct cadence_spi_plat *plat = dev_get_plat(bus); @@ -138,7 +151,7 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) struct cadence_spi_priv *priv = dev_get_priv(bus); int err; - if (hz > plat->max_hz) + if (!hz || hz > plat->max_hz) hz = plat->max_hz; /* Disable QSPI */ @@ -185,6 +198,11 @@ static int cadence_spi_probe(struct udevice *bus) priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; + if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) + xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI, + ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, + ZYNQMP_PM_REQUEST_ACK_NO, NULL); + if (plat->ref_clk_hz == 0) { ret = clk_get_by_index(bus, 0, &clk); if (ret) { @@ -214,6 +232,16 @@ static int cadence_spi_probe(struct udevice *bus) plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz); + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) { + /* Versal platform uses spi calibration to set read delay */ + if (plat->read_delay >= 0) + plat->read_delay = -1; + /* Reset ospi flash device */ + ret = cadence_qspi_versal_flash_reset(bus); + if (ret) + return ret; + } + return 0; } @@ -288,8 +316,12 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, break; case CQSPI_READ: err = cadence_qspi_apb_read_setup(plat, op); - if (!err) - err = cadence_qspi_apb_read_execute(plat, op); + if (!err) { + if (plat->is_dma) + err = cadence_qspi_apb_dma_read(plat, op); + else + err = cadence_qspi_apb_read_execute(plat, op); + } break; case CQSPI_WRITE: err = cadence_qspi_apb_write_setup(plat, op); @@ -342,6 +374,8 @@ static int cadence_spi_of_to_plat(struct udevice *bus) if (plat->ahbsize >= SZ_8M) plat->use_dac_mode = true; + plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); + /* All other paramters are embedded in the child node */ subnode = dev_read_first_subnode(bus); if (!ofnode_valid(subnode)) { diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index a2b620a5fe..c8d16bb0e4 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -8,6 +8,8 @@ #define __CADENCE_QSPI_H__ #include <reset.h> +#include <linux/mtd/spi-nor.h> +#include <spi-mem.h> #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) @@ -15,6 +17,186 @@ #define CQSPI_DECODER_MAX_CS 16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16 +#define CQSPI_REG_POLL_US 1 /* 1us */ +#define CQSPI_REG_RETRY 10000 +#define CQSPI_POLL_IDLE_RETRY 3 + +/* Transfer mode */ +#define CQSPI_INST_TYPE_SINGLE 0 +#define CQSPI_INST_TYPE_DUAL 1 +#define CQSPI_INST_TYPE_QUAD 2 +#define CQSPI_INST_TYPE_OCTAL 3 + +#define CQSPI_STIG_DATA_LEN_MAX 8 + +#define CQSPI_DUMMY_CLKS_PER_BYTE 8 +#define CQSPI_DUMMY_BYTES_MAX 4 +#define CQSPI_DUMMY_CLKS_MAX 31 + +/**************************************************************************** + * Controller's configuration and status register (offset from QSPI_BASE) + ****************************************************************************/ +#define CQSPI_REG_CONFIG 0x00 +#define CQSPI_REG_CONFIG_ENABLE BIT(0) +#define CQSPI_REG_CONFIG_CLK_POL BIT(1) +#define CQSPI_REG_CONFIG_CLK_PHA BIT(2) +#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3) +#define CQSPI_REG_CONFIG_DIRECT BIT(7) +#define CQSPI_REG_CONFIG_DECODE BIT(9) +#define CQSPI_REG_CONFIG_ENBL_DMA BIT(15) +#define CQSPI_REG_CONFIG_XIP_IMM BIT(18) +#define CQSPI_REG_CONFIG_DTR_PROT_EN_MASK BIT(24) +#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 +#define CQSPI_REG_CONFIG_BAUD_LSB 19 +#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) +#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) +#define CQSPI_REG_CONFIG_IDLE_LSB 31 +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF +#define CQSPI_REG_CONFIG_BAUD_MASK 0xF + +#define CQSPI_REG_RD_INSTR 0x04 +#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 +#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 +#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 +#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F + +#define CQSPI_REG_WR_INSTR 0x08 +#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 + +#define CQSPI_REG_DELAY 0x0C +#define CQSPI_REG_DELAY_TSLCH_LSB 0 +#define CQSPI_REG_DELAY_TCHSH_LSB 8 +#define CQSPI_REG_DELAY_TSD2D_LSB 16 +#define CQSPI_REG_DELAY_TSHSL_LSB 24 +#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF +#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF +#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF +#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF + +#define CQSPI_REG_RD_DATA_CAPTURE 0x10 +#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) +#define CQSPI_REG_READCAPTURE_DQS_ENABLE BIT(8) +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF + +#define CQSPI_REG_SIZE 0x14 +#define CQSPI_REG_SIZE_ADDRESS_LSB 0 +#define CQSPI_REG_SIZE_PAGE_LSB 4 +#define CQSPI_REG_SIZE_BLOCK_LSB 16 +#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF +#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF +#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F + +#define CQSPI_REG_SRAMPARTITION 0x18 +#define CQSPI_REG_INDIRECTTRIGGER 0x1C + +#define CQSPI_REG_REMAP 0x24 +#define CQSPI_REG_MODE_BIT 0x28 + +#define CQSPI_REG_SDRAMLEVEL 0x2C +#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 +#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 +#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF +#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF + +#define CQSPI_REG_WR_COMPLETION_CTRL 0x38 +#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) + +#define CQSPI_REG_IRQSTATUS 0x40 +#define CQSPI_REG_IRQMASK 0x44 + +#define CQSPI_REG_INDIRECTRD 0x60 +#define CQSPI_REG_INDIRECTRD_START BIT(0) +#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) +#define CQSPI_REG_INDIRECTRD_DONE BIT(5) + +#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 +#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 +#define CQSPI_REG_INDIRECTRDBYTES 0x6C + +#define CQSPI_REG_CMDCTRL 0x90 +#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0) +#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1) +#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 +#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 +#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 +#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 +#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 +#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 +#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF + +#define CQSPI_REG_INDIRECTWR 0x70 +#define CQSPI_REG_INDIRECTWR_START BIT(0) +#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2) +#define CQSPI_REG_INDIRECTWR_DONE BIT(5) + +#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 +#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 +#define CQSPI_REG_INDIRECTWRBYTES 0x7C + +#define CQSPI_REG_CMDADDRESS 0x94 +#define CQSPI_REG_CMDREADDATALOWER 0xA0 +#define CQSPI_REG_CMDREADDATAUPPER 0xA4 +#define CQSPI_REG_CMDWRITEDATALOWER 0xA8 +#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC + +#define CQSPI_REG_OP_EXT_LOWER 0xE0 +#define CQSPI_REG_OP_EXT_READ_LSB 24 +#define CQSPI_REG_OP_EXT_WRITE_LSB 16 +#define CQSPI_REG_OP_EXT_STIG_LSB 0 + +#define CQSPI_REG_PHY_CONFIG 0xB4 +#define CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK 0x40000000 + +#define CQSPI_DMA_DST_ADDR_REG 0x1800 +#define CQSPI_DMA_DST_SIZE_REG 0x1804 +#define CQSPI_DMA_DST_STS_REG 0x1808 +#define CQSPI_DMA_DST_CTRL_REG 0x180C +#define CQSPI_DMA_DST_I_STS_REG 0x1814 +#define CQSPI_DMA_DST_I_ENBL_REG 0x1818 +#define CQSPI_DMA_DST_I_DISBL_REG 0x181C +#define CQSPI_DMA_DST_CTRL2_REG 0x1824 +#define CQSPI_DMA_DST_ADDR_MSB_REG 0x1828 + +#define CQSPI_DMA_SRC_RD_ADDR_REG 0x1000 + +#define CQSPI_REG_DMA_PERIPH_CFG 0x20 +#define CQSPI_REG_INDIR_TRIG_ADDR_RANGE 0x80 +#define CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE 6 +#define CQSPI_DFLT_DMA_PERIPH_CFG 0x602 +#define CQSPI_DFLT_DST_CTRL_REG_VAL 0xF43FFA00 + +#define CQSPI_DMA_DST_I_STS_DONE BIT(1) +#define CQSPI_DMA_TIMEOUT 10000000 + +#define CQSPI_REG_IS_IDLE(base) \ + ((readl((base) + CQSPI_REG_CONFIG) >> \ + CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) + +#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ + (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) + +#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ + (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) + struct cadence_spi_plat { unsigned int ref_clk_hz; unsigned int max_hz; @@ -42,6 +224,7 @@ struct cadence_spi_plat { u8 addr_width; u8 data_width; bool dtr; + bool is_dma; }; struct cadence_spi_priv { @@ -96,5 +279,11 @@ void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); void cadence_qspi_apb_readdata_capture(void *reg_base, unsigned int bypass, unsigned int delay); unsigned int cm_get_qspi_controller_clk_hz(void); +int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat); +int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); +int cadence_qspi_versal_flash_reset(struct udevice *dev); +void cadence_qspi_apb_enable_linear_mode(bool enable); #endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2cdf4c9c9f..c00755050e 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -38,156 +38,10 @@ #include <malloc.h> #include "cadence_qspi.h" -#define CQSPI_REG_POLL_US 1 /* 1us */ -#define CQSPI_REG_RETRY 10000 -#define CQSPI_POLL_IDLE_RETRY 3 - -/* Transfer mode */ -#define CQSPI_INST_TYPE_SINGLE 0 -#define CQSPI_INST_TYPE_DUAL 1 -#define CQSPI_INST_TYPE_QUAD 2 -#define CQSPI_INST_TYPE_OCTAL 3 - -#define CQSPI_STIG_DATA_LEN_MAX 8 - -#define CQSPI_DUMMY_CLKS_PER_BYTE 8 -#define CQSPI_DUMMY_CLKS_MAX 31 - -/**************************************************************************** - * Controller's configuration and status register (offset from QSPI_BASE) - ****************************************************************************/ -#define CQSPI_REG_CONFIG 0x00 -#define CQSPI_REG_CONFIG_ENABLE BIT(0) -#define CQSPI_REG_CONFIG_CLK_POL BIT(1) -#define CQSPI_REG_CONFIG_CLK_PHA BIT(2) -#define CQSPI_REG_CONFIG_DIRECT BIT(7) -#define CQSPI_REG_CONFIG_DECODE BIT(9) -#define CQSPI_REG_CONFIG_XIP_IMM BIT(18) -#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 -#define CQSPI_REG_CONFIG_BAUD_LSB 19 -#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) -#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) -#define CQSPI_REG_CONFIG_IDLE_LSB 31 -#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF -#define CQSPI_REG_CONFIG_BAUD_MASK 0xF - -#define CQSPI_REG_RD_INSTR 0x04 -#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 -#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 -#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 -#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 -#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 -#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 -#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 -#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 -#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 -#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F - -#define CQSPI_REG_WR_INSTR 0x08 -#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 -#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 -#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 - -#define CQSPI_REG_DELAY 0x0C -#define CQSPI_REG_DELAY_TSLCH_LSB 0 -#define CQSPI_REG_DELAY_TCHSH_LSB 8 -#define CQSPI_REG_DELAY_TSD2D_LSB 16 -#define CQSPI_REG_DELAY_TSHSL_LSB 24 -#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF -#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF -#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF -#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF - -#define CQSPI_REG_RD_DATA_CAPTURE 0x10 -#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) -#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 -#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF - -#define CQSPI_REG_SIZE 0x14 -#define CQSPI_REG_SIZE_ADDRESS_LSB 0 -#define CQSPI_REG_SIZE_PAGE_LSB 4 -#define CQSPI_REG_SIZE_BLOCK_LSB 16 -#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF -#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF -#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F - -#define CQSPI_REG_SRAMPARTITION 0x18 -#define CQSPI_REG_INDIRECTTRIGGER 0x1C - -#define CQSPI_REG_REMAP 0x24 -#define CQSPI_REG_MODE_BIT 0x28 - -#define CQSPI_REG_SDRAMLEVEL 0x2C -#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 -#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 -#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF -#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF - -#define CQSPI_REG_WR_COMPLETION_CTRL 0x38 -#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) - -#define CQSPI_REG_IRQSTATUS 0x40 -#define CQSPI_REG_IRQMASK 0x44 - -#define CQSPI_REG_INDIRECTRD 0x60 -#define CQSPI_REG_INDIRECTRD_START BIT(0) -#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1) -#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) -#define CQSPI_REG_INDIRECTRD_DONE BIT(5) - -#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 -#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 -#define CQSPI_REG_INDIRECTRDBYTES 0x6C - -#define CQSPI_REG_CMDCTRL 0x90 -#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0) -#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1) -#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 -#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 -#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 -#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 -#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 -#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 -#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 -#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 -#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F -#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 -#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 -#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 -#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF - -#define CQSPI_REG_INDIRECTWR 0x70 -#define CQSPI_REG_INDIRECTWR_START BIT(0) -#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1) -#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2) -#define CQSPI_REG_INDIRECTWR_DONE BIT(5) - -#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 -#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 -#define CQSPI_REG_INDIRECTWRBYTES 0x7C - -#define CQSPI_REG_CMDADDRESS 0x94 -#define CQSPI_REG_CMDREADDATALOWER 0xA0 -#define CQSPI_REG_CMDREADDATAUPPER 0xA4 -#define CQSPI_REG_CMDWRITEDATALOWER 0xA8 -#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC - -#define CQSPI_REG_OP_EXT_LOWER 0xE0 -#define CQSPI_REG_OP_EXT_READ_LSB 24 -#define CQSPI_REG_OP_EXT_WRITE_LSB 16 -#define CQSPI_REG_OP_EXT_STIG_LSB 0 - -#define CQSPI_REG_IS_IDLE(base) \ - ((readl(base + CQSPI_REG_CONFIG) >> \ - CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) - -#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ - (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ - CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) - -#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ - (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ - CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) +__weak void cadence_qspi_apb_enable_linear_mode(bool enable) +{ + return; +} void cadence_qspi_apb_controller_enable(void *reg_base) { @@ -487,8 +341,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat) cadence_qspi_apb_controller_enable(plat->regbase); } -static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, - unsigned int reg) +int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg) { unsigned int retry = CQSPI_REG_RETRY; @@ -882,6 +735,9 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat, void *buf = op->data.buf.in; size_t len = op->data.nbytes; + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) + cadence_qspi_apb_enable_linear_mode(true); + if (plat->use_dac_mode && (from + len < plat->ahbsize)) { if (len < 256 || dma_memcpy(buf, plat->ahbbase + from, len) < 0) { @@ -1049,6 +905,9 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat, const void *buf = op->data.buf.out; size_t len = op->data.nbytes; + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) + cadence_qspi_apb_enable_linear_mode(true); + /* * Some flashes like the Cypress Semper flash expect a dummy 4-byte * address (all 0s) with the read status register command in DTR mode. diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c index 4d7a2acd8e..00b8cd368b 100644 --- a/drivers/usb/common/fsl-dt-fixup.c +++ b/drivers/usb/common/fsl-dt-fixup.c @@ -16,10 +16,6 @@ #include <fsl_usb.h> #include <fdt_support.h> -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - /* USB Controllers */ #define FSL_USB2_MPH "fsl-usb2-mph" #define FSL_USB2_DR "fsl-usb2-dr" diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index d81a9c5a10..350036f208 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -92,6 +92,11 @@ config USB_GADGET_DWC2_OTG if USB_GADGET_DWC2_OTG +config USB_GADGET_DWC2_OTG_PHY + bool "DesignWare USB2.0 HS OTG PHY" + help + Enable the DesignWare USB2.0 HS OTG physical device interface. + config USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 bool "DesignWare USB2.0 HS OTG controller 8-bit PHY bus width" help diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index d8de8efa0a..306dd3127f 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -43,6 +43,5 @@ ifdef CONFIG_USB_DEVICE obj-y += core.o obj-y += ep0.o obj-$(CONFIG_DW_UDC) += designware_udc.o -obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o endif endif diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index 01337d6511..bb0d2971d0 100644 --- a/drivers/usb/gadget/epautoconf.c +++ b/drivers/usb/gadget/epautoconf.c @@ -79,12 +79,6 @@ static int ep_matches( */ if ('s' == tmp[2]) /* == "-iso" */ return 0; - /* for now, avoid PXA "interrupt-in"; - * it's documented as never using DATA1. - */ - if (gadget_is_pxa(gadget) - && 'i' == tmp[1]) - return 0; break; case USB_ENDPOINT_XFER_BULK: if ('b' != tmp[1]) /* != "-bulk" */ diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 4307328657..72b4f7f306 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -1325,24 +1325,6 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) if (!cdc_active(dev) && wIndex != 0) break; - /* - * PXA hardware partially handles SET_INTERFACE; - * we need to kluge around that interference. - */ - if (gadget_is_pxa(gadget)) { - value = eth_set_config(dev, DEV_CONFIG_VALUE, - GFP_ATOMIC); - /* - * PXA25x driver use non-CDC ethernet gadget. - * But only _CDC and _RNDIS code can signalize - * that network is working. So we signalize it - * here. - */ - dev->network_started = 1; - debug("USB network up!\n"); - goto done_set_intf; - } - #ifdef CONFIG_USB_ETH_CDC switch (wIndex) { case 0: /* control/master intf */ @@ -1386,8 +1368,6 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) */ debug("set_interface ignored!\n"); #endif /* CONFIG_USB_ETH_CDC */ - -done_set_intf: break; case USB_REQ_GET_INTERFACE: if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE) @@ -2032,10 +2012,7 @@ static int eth_bind(struct usb_gadget *gadget) * standard protocol is _strongly_ preferred for interop purposes. * (By everyone except Microsoft.) */ - if (gadget_is_pxa(gadget)) { - /* pxa doesn't support altsettings */ - cdc = 0; - } else if (gadget_is_musbhdrc(gadget)) { + if (gadget_is_musbhdrc(gadget)) { /* reduce tx dma overhead by avoiding special cases */ zlp = 0; } else if (gadget_is_sh(gadget)) { diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 06e6a48949..66ccd05417 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -32,12 +32,6 @@ #define gadget_is_dummy(g) 0 #endif -#ifdef CONFIG_USB_GADGET_PXA2XX -#define gadget_is_pxa(g) (!strcmp("pxa2xx_udc", (g)->name)) -#else -#define gadget_is_pxa(g) 0 -#endif - #ifdef CONFIG_USB_GADGET_GOKU #define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name)) #else @@ -78,13 +72,6 @@ #define gadget_is_n9604(g) 0 #endif -/* various unstable versions available */ -#ifdef CONFIG_USB_GADGET_PXA27X -#define gadget_is_pxa27x(g) (!strcmp("pxa27x_udc", (g)->name)) -#else -#define gadget_is_pxa27x(g) 0 -#endif - #ifdef CONFIG_USB_GADGET_ATMEL_USBA #define gadget_is_atmel_usba(g) (!strcmp("atmel_usba_udc", (g)->name)) #else @@ -194,8 +181,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x01; else if (gadget_is_dummy(gadget)) return 0x02; - else if (gadget_is_pxa(gadget)) - return 0x03; else if (gadget_is_sh(gadget)) return 0x04; else if (gadget_is_sa1100(gadget)) @@ -208,8 +193,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x08; else if (gadget_is_n9604(gadget)) return 0x09; - else if (gadget_is_pxa27x(gadget)) - return 0x10; else if (gadget_is_at91(gadget)) return 0x12; else if (gadget_is_imx(gadget)) diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c deleted file mode 100644 index 583ceb4d55..0000000000 --- a/drivers/usb/gadget/pxa27x_udc.c +++ /dev/null @@ -1,703 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PXA27x USB device driver for u-boot. - * - * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it> - * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it> - * Copyright (C) 2008 Vivek Kutal <vivek.kutal@azingo.com> - */ - - -#include <common.h> -#include <asm/arch/hardware.h> -#include <asm/byteorder.h> -#include <asm/io.h> -#include <usbdevice.h> -#include <linux/delay.h> -#include <usb/pxa27x_udc.h> -#include <usb/udc.h> - -#include "ep0.h" - -/* number of endpoints on this UDC */ -#define UDC_MAX_ENDPOINTS 24 - -static struct urb *ep0_urb; -static struct usb_device_instance *udc_device; -static int ep0state = EP0_IDLE; - -#ifdef USBDDBG -static void udc_dump_buffer(char *name, u8 *buf, int len) -{ - usbdbg("%s - buf %p, len %d", name, buf, len); - print_buffer(0, buf, 1, len, 0); -} -#else -#define udc_dump_buffer(name, buf, len) /* void */ -#endif - -static inline void udc_ack_int_UDCCR(int mask) -{ - writel(readl(USIR1) | mask, USIR1); -} - -/* - * If the endpoint has an active tx_urb, then the next packet of data from the - * URB is written to the tx FIFO. - * The total amount of data in the urb is given by urb->actual_length. - * The maximum amount of data that can be sent in any one packet is given by - * endpoint->tx_packetSize. - * The number of data bytes from this URB that have already been transmitted - * is given by endpoint->sent. - * endpoint->last is updated by this routine with the number of data bytes - * transmitted in this packet. - */ -static int udc_write_urb(struct usb_endpoint_instance *endpoint) -{ - struct urb *urb = endpoint->tx_urb; - int ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - u32 *data32 = (u32 *) urb->buffer; - u8 *data8 = (u8 *) urb->buffer; - unsigned int i, n, w, b, is_short; - int timeout = 2000; /* 2ms */ - - if (!urb || !urb->actual_length) - return -1; - - n = min_t(unsigned int, urb->actual_length - endpoint->sent, - endpoint->tx_packetSize); - if (n <= 0) - return -1; - - usbdbg("write urb on ep %d", ep_num); -#if defined(USBDDBG) && defined(USBDPARANOIA) - usbdbg("urb: buf %p, buf_len %d, actual_len %d", - urb->buffer, urb->buffer_length, urb->actual_length); - usbdbg("endpoint: sent %d, tx_packetSize %d, last %d", - endpoint->sent, endpoint->tx_packetSize, endpoint->last); -#endif - - is_short = n != endpoint->tx_packetSize; - w = n / 4; - b = n % 4; - usbdbg("n %d%s w %d b %d", n, is_short ? "-s" : "", w, b); - udc_dump_buffer("urb write", data8 + endpoint->sent, n); - - /* Prepare for data send */ - if (ep_num) - writel(UDCCSR_PC ,UDCCSN(ep_num)); - - for (i = 0; i < w; i++) - writel(data32[endpoint->sent / 4 + i], UDCDN(ep_num)); - - for (i = 0; i < b; i++) - writeb(data8[endpoint->sent + w * 4 + i], UDCDN(ep_num)); - - /* Set "Packet Complete" if less data then tx_packetSize */ - if (is_short) - writel(ep_num ? UDCCSR_SP : UDCCSR0_IPR, UDCCSN(ep_num)); - - /* Wait for data sent */ - if (ep_num) { - while (!(readl(UDCCSN(ep_num)) & UDCCSR_PC)) { - if (timeout-- == 0) - return -1; - else - udelay(1); - } - } - - endpoint->last = n; - - if (ep_num) { - usbd_tx_complete(endpoint); - } else { - endpoint->sent += n; - endpoint->last -= n; - } - - if (endpoint->sent >= urb->actual_length) { - urb->actual_length = 0; - endpoint->sent = 0; - endpoint->last = 0; - } - - if ((endpoint->sent >= urb->actual_length) && (!ep_num)) { - usbdbg("ep0 IN stage done"); - if (is_short) - ep0state = EP0_IDLE; - else - ep0state = EP0_XFER_COMPLETE; - } - - return 0; -} - -static int udc_read_urb(struct usb_endpoint_instance *endpoint) -{ - struct urb *urb = endpoint->rcv_urb; - int ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - u32 *data32 = (u32 *) urb->buffer; - unsigned int i, n; - - usbdbg("read urb on ep %d", ep_num); -#if defined(USBDDBG) && defined(USBDPARANOIA) - usbdbg("urb: buf %p, buf_len %d, actual_len %d", - urb->buffer, urb->buffer_length, urb->actual_length); - usbdbg("endpoint: rcv_packetSize %d", - endpoint->rcv_packetSize); -#endif - - if (readl(UDCCSN(ep_num)) & UDCCSR_BNE) - n = readl(UDCBCN(ep_num)) & 0x3ff; - else /* zlp */ - n = 0; - - usbdbg("n %d%s", n, n != endpoint->rcv_packetSize ? "-s" : ""); - for (i = 0; i < n; i += 4) - data32[urb->actual_length / 4 + i / 4] = readl(UDCDN(ep_num)); - - udc_dump_buffer("urb read", (u8 *) data32, urb->actual_length + n); - usbd_rcv_complete(endpoint, n, 0); - - return 0; -} - -static int udc_read_urb_ep0(void) -{ - u32 *data32 = (u32 *) ep0_urb->buffer; - u8 *data8 = (u8 *) ep0_urb->buffer; - unsigned int i, n, w, b; - - usbdbg("read urb on ep 0"); -#if defined(USBDDBG) && defined(USBDPARANOIA) - usbdbg("urb: buf %p, buf_len %d, actual_len %d", - ep0_urb->buffer, ep0_urb->buffer_length, ep0_urb->actual_length); -#endif - - n = readl(UDCBCR0); - w = n / 4; - b = n % 4; - - for (i = 0; i < w; i++) { - data32[ep0_urb->actual_length / 4 + i] = readl(UDCDN(0)); - /* ep0_urb->actual_length += 4; */ - } - - for (i = 0; i < b; i++) { - data8[ep0_urb->actual_length + w * 4 + i] = readb(UDCDN(0)); - /* ep0_urb->actual_length++; */ - } - - ep0_urb->actual_length += n; - - udc_dump_buffer("urb read", (u8 *) data32, ep0_urb->actual_length); - - writel(UDCCSR0_OPC | UDCCSR0_IPR, UDCCSR0); - if (ep0_urb->actual_length == ep0_urb->device_request.wLength) - return 1; - - return 0; -} - -static void udc_handle_ep0(struct usb_endpoint_instance *endpoint) -{ - u32 udccsr0 = readl(UDCCSR0); - u32 *data = (u32 *) &ep0_urb->device_request; - int i; - - usbdbg("udccsr0 %x", udccsr0); - - /* Clear stall status */ - if (udccsr0 & UDCCSR0_SST) { - usberr("clear stall status"); - writel(UDCCSR0_SST, UDCCSR0); - ep0state = EP0_IDLE; - } - - /* previous request unfinished? non-error iff back-to-back ... */ - if ((udccsr0 & UDCCSR0_SA) != 0 && ep0state != EP0_IDLE) - ep0state = EP0_IDLE; - - switch (ep0state) { - - case EP0_IDLE: - udccsr0 = readl(UDCCSR0); - /* Start control request? */ - if ((udccsr0 & (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)) - == (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)) { - - /* Read SETUP packet. - * SETUP packet size is 8 bytes (aka 2 words) - */ - usbdbg("try reading SETUP packet"); - for (i = 0; i < 2; i++) { - if ((readl(UDCCSR0) & UDCCSR0_RNE) == 0) { - usberr("setup packet too short:%d", i); - goto stall; - } - data[i] = readl(UDCDR0); - } - - writel(readl(UDCCSR0) | UDCCSR0_OPC | UDCCSR0_SA, UDCCSR0); - if ((readl(UDCCSR0) & UDCCSR0_RNE) != 0) { - usberr("setup packet too long"); - goto stall; - } - - udc_dump_buffer("ep0 setup read", (u8 *) data, 8); - - if (ep0_urb->device_request.wLength == 0) { - usbdbg("Zero Data control Packet\n"); - if (ep0_recv_setup(ep0_urb)) { - usberr("Invalid Setup Packet\n"); - udc_dump_buffer("ep0 setup read", - (u8 *)data, 8); - goto stall; - } - writel(UDCCSR0_IPR, UDCCSR0); - ep0state = EP0_IDLE; - } else { - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType & - USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - ep0state = EP0_OUT_DATA; - ep0_urb->buffer = - (u8 *)ep0_urb->buffer_data; - ep0_urb->buffer_length = - sizeof(ep0_urb->buffer_data); - ep0_urb->actual_length = 0; - writel(UDCCSR0_IPR, UDCCSR0); - } else { - /* The ep0_recv_setup function has - * already placed our response packet - * data in ep0_urb->buffer and the - * packet length in - * ep0_urb->actual_length. - */ - if (ep0_recv_setup(ep0_urb)) { -stall: - usberr("Invalid setup packet"); - udc_dump_buffer("ep0 setup read" - , (u8 *) data, 8); - ep0state = EP0_IDLE; - - writel(UDCCSR0_SA | - UDCCSR0_OPC | UDCCSR0_FST | - UDCCS0_FTF, UDCCSR0); - - return; - } - - endpoint->tx_urb = ep0_urb; - endpoint->sent = 0; - usbdbg("EP0_IN_DATA"); - ep0state = EP0_IN_DATA; - if (udc_write_urb(endpoint) < 0) - goto stall; - - } - } - return; - } else if ((udccsr0 & (UDCCSR0_OPC | UDCCSR0_SA)) - == (UDCCSR0_OPC|UDCCSR0_SA)) { - usberr("Setup Active but no data. Stalling ....\n"); - goto stall; - } else { - usbdbg("random early IRQs"); - /* Some random early IRQs: - * - we acked FST - * - IPR cleared - * - OPC got set, without SA (likely status stage) - */ - writel(udccsr0 & (UDCCSR0_SA | UDCCSR0_OPC), UDCCSR0); - } - break; - - case EP0_OUT_DATA: - - if ((udccsr0 & UDCCSR0_OPC) && !(udccsr0 & UDCCSR0_SA)) { - if (udc_read_urb_ep0()) { -read_complete: - ep0state = EP0_IDLE; - if (ep0_recv_setup(ep0_urb)) { - /* Not a setup packet, stall next - * EP0 transaction - */ - udc_dump_buffer("ep0 setup read", - (u8 *) data, 8); - usberr("can't parse setup packet\n"); - goto stall; - } - } - } else if (!(udccsr0 & UDCCSR0_OPC) && - !(udccsr0 & UDCCSR0_IPR)) { - if (ep0_urb->device_request.wLength == - ep0_urb->actual_length) - goto read_complete; - - usberr("Premature Status\n"); - ep0state = EP0_IDLE; - } - break; - - case EP0_IN_DATA: - /* GET_DESCRIPTOR etc */ - if (udccsr0 & UDCCSR0_OPC) { - writel(UDCCSR0_OPC | UDCCSR0_FTF, UDCCSR0); - usberr("ep0in premature status"); - ep0state = EP0_IDLE; - } else { - /* irq was IPR clearing */ - if (udc_write_urb(endpoint) < 0) { - usberr("ep0_write_error\n"); - goto stall; - } - } - break; - - case EP0_XFER_COMPLETE: - writel(UDCCSR0_IPR, UDCCSR0); - ep0state = EP0_IDLE; - break; - - default: - usbdbg("Default\n"); - } - writel(USIR0_IR0, USIR0); -} - -static void udc_handle_ep(struct usb_endpoint_instance *endpoint) -{ - int ep_addr = endpoint->endpoint_address; - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - int ep_isout = (ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT; - - u32 flags = readl(UDCCSN(ep_num)) & (UDCCSR_SST | UDCCSR_TRN); - if (flags) - writel(flags, UDCCSN(ep_num)); - - if (ep_isout) - udc_read_urb(endpoint); - else - udc_write_urb(endpoint); - - writel(UDCCSR_PC, UDCCSN(ep_num)); -} - -static void udc_state_changed(void) -{ - - writel(readl(UDCCR) | UDCCR_SMAC, UDCCR); - - usbdbg("New UDC settings are: conf %d - inter %d - alter %d", - (readl(UDCCR) & UDCCR_ACN) >> UDCCR_ACN_S, - (readl(UDCCR) & UDCCR_AIN) >> UDCCR_AIN_S, - (readl(UDCCR) & UDCCR_AAISN) >> UDCCR_AAISN_S); - - usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); - writel(UDCISR1_IRCC, UDCISR1); -} - -void udc_irq(void) -{ - int handled; - struct usb_endpoint_instance *endpoint; - int ep_num, i; - u32 udcisr0; - - do { - handled = 0; - /* Suspend Interrupt Request */ - if (readl(USIR1) & UDCCR_SUSIR) { - usbdbg("Suspend\n"); - udc_ack_int_UDCCR(UDCCR_SUSIR); - handled = 1; - ep0state = EP0_IDLE; - } - - /* Resume Interrupt Request */ - if (readl(USIR1) & UDCCR_RESIR) { - udc_ack_int_UDCCR(UDCCR_RESIR); - handled = 1; - usbdbg("USB resume\n"); - } - - if (readl(USIR1) & (1<<31)) { - handled = 1; - udc_state_changed(); - } - - /* Reset Interrupt Request */ - if (readl(USIR1) & UDCCR_RSTIR) { - udc_ack_int_UDCCR(UDCCR_RSTIR); - handled = 1; - usbdbg("Reset\n"); - usbd_device_event_irq(udc_device, DEVICE_RESET, 0); - } else { - if (readl(USIR0)) - usbdbg("UISR0: %x \n", readl(USIR0)); - - if (readl(USIR0) & 0x2) - writel(0x2, USIR0); - - /* Control traffic */ - if (readl(USIR0) & USIR0_IR0) { - handled = 1; - writel(USIR0_IR0, USIR0); - udc_handle_ep0(udc_device->bus->endpoint_array); - } - - endpoint = udc_device->bus->endpoint_array; - for (i = 0; i < udc_device->bus->max_endpoints; i++) { - ep_num = (endpoint[i].endpoint_address) & - USB_ENDPOINT_NUMBER_MASK; - if (!ep_num) - continue; - udcisr0 = readl(UDCISR0); - if (udcisr0 & - UDCISR_INT(ep_num, UDC_INT_PACKETCMP)) { - writel(UDCISR_INT(ep_num, UDC_INT_PACKETCMP), - UDCISR0); - udc_handle_ep(&endpoint[i]); - } - } - } - - } while (handled); -} - -/* The UDCCR reg contains mask and interrupt status bits, - * so using '|=' isn't safe as it may ack an interrupt. - */ -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE) - -static inline void udc_set_mask_UDCCR(int mask) -{ - writel((readl(UDCCR) & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR); -} - -static inline void udc_clear_mask_UDCCR(int mask) -{ - writel((readl(UDCCR) & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR); -} - -static void pio_irq_enable(int ep_num) -{ - if (ep_num < 16) - writel(readl(UDCICR0) | 3 << (ep_num * 2), UDCICR0); - else { - ep_num -= 16; - writel(readl(UDCICR1) | 3 << (ep_num * 2), UDCICR1); - } -} - -/* - * udc_set_nak - * - * Allow upper layers to signal lower layers should not accept more RX data - */ -void udc_set_nak(int ep_num) -{ - /* TODO */ -} - -/* - * udc_unset_nak - * - * Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint. - * Switch off NAKing on this endpoint to accept more data output from host. - */ -void udc_unset_nak(int ep_num) -{ - /* TODO */ -} - -int udc_endpoint_write(struct usb_endpoint_instance *endpoint) -{ - return udc_write_urb(endpoint); -} - -/* Associate a physical endpoint with endpoint instance */ -void udc_setup_ep(struct usb_device_instance *device, unsigned int id, - struct usb_endpoint_instance *endpoint) -{ - int ep_num, ep_addr, ep_isout, ep_type, ep_size; - int config, interface, alternate; - u32 tmp; - - usbdbg("setting up endpoint id %d", id); - - if (!endpoint) { - usberr("endpoint void!"); - return; - } - - ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - if (ep_num >= UDC_MAX_ENDPOINTS) { - usberr("unable to setup ep %d!", ep_num); - return; - } - - pio_irq_enable(ep_num); - if (ep_num == 0) { - /* Done for ep0 */ - return; - } - - config = 1; - interface = 0; - alternate = 0; - - usbdbg("config %d - interface %d - alternate %d", - config, interface, alternate); - - ep_addr = endpoint->endpoint_address; - ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - ep_isout = (ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT; - ep_type = ep_isout ? endpoint->rcv_attributes : endpoint->tx_attributes; - ep_size = ep_isout ? endpoint->rcv_packetSize : endpoint->tx_packetSize; - - usbdbg("addr %x, num %d, dir %s, type %s, packet size %d", - ep_addr, ep_num, - ep_isout ? "out" : "in", - ep_type == USB_ENDPOINT_XFER_ISOC ? "isoc" : - ep_type == USB_ENDPOINT_XFER_BULK ? "bulk" : - ep_type == USB_ENDPOINT_XFER_INT ? "int" : "???", - ep_size - ); - - /* Configure UDCCRx */ - tmp = 0; - tmp |= (config << UDCCONR_CN_S) & UDCCONR_CN; - tmp |= (interface << UDCCONR_IN_S) & UDCCONR_IN; - tmp |= (alternate << UDCCONR_AISN_S) & UDCCONR_AISN; - tmp |= (ep_num << UDCCONR_EN_S) & UDCCONR_EN; - tmp |= (ep_type << UDCCONR_ET_S) & UDCCONR_ET; - tmp |= ep_isout ? 0 : UDCCONR_ED; - tmp |= (ep_size << UDCCONR_MPS_S) & UDCCONR_MPS; - tmp |= UDCCONR_EE; - - writel(tmp, UDCCN(ep_num)); - - usbdbg("UDCCR%c = %x", 'A' + ep_num-1, readl(UDCCN(ep_num))); - usbdbg("UDCCSR%c = %x", 'A' + ep_num-1, readl(UDCCSN(ep_num))); -} - -/* Connect the USB device to the bus */ -void udc_connect(void) -{ - usbdbg("UDC connect"); - -#ifdef CONFIG_USB_DEV_PULLUP_GPIO - /* Turn on the USB connection by enabling the pullup resistor */ - writel(readl(GPDR(CONFIG_USB_DEV_PULLUP_GPIO)) - | GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), - GPDR(CONFIG_USB_DEV_PULLUP_GPIO)); - writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPSR(CONFIG_USB_DEV_PULLUP_GPIO)); -#else - /* Host port 2 transceiver D+ pull up enable */ - writel(readl(UP2OCR) | UP2OCR_DPPUE, UP2OCR); -#endif -} - -/* Disconnect the USB device to the bus */ -void udc_disconnect(void) -{ - usbdbg("UDC disconnect"); - -#ifdef CONFIG_USB_DEV_PULLUP_GPIO - /* Turn off the USB connection by disabling the pullup resistor */ - writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPCR(CONFIG_USB_DEV_PULLUP_GPIO)); -#else - /* Host port 2 transceiver D+ pull up disable */ - writel(readl(UP2OCR) & ~UP2OCR_DPPUE, UP2OCR); -#endif -} - -/* Switch on the UDC */ -void udc_enable(struct usb_device_instance *device) -{ - - ep0state = EP0_IDLE; - - /* enable endpoint 0, A, B's Packet Complete Interrupt. */ - writel(0xffffffff, UDCICR0); - writel(0xa8000000, UDCICR1); - - /* clear the interrupt status/control registers */ - writel(0xffffffff, UDCISR0); - writel(0xffffffff, UDCISR1); - - /* set UDC-enable */ - udc_set_mask_UDCCR(UDCCR_UDE); - - udc_device = device; - if (!ep0_urb) - ep0_urb = usbd_alloc_urb(udc_device, - udc_device->bus->endpoint_array); - else - usbinfo("ep0_urb %p already allocated", ep0_urb); - - usbdbg("UDC Enabled\n"); -} - -/* Need to check this again */ -void udc_disable(void) -{ - usbdbg("disable UDC"); - - udc_clear_mask_UDCCR(UDCCR_UDE); - - /* Disable clock for USB device */ - writel(readl(CKEN) & ~CKEN11_USB, CKEN); - - /* Free ep0 URB */ - if (ep0_urb) { - usbd_dealloc_urb(ep0_urb); - ep0_urb = NULL; - } - - /* Reset device pointer */ - udc_device = NULL; -} - -/* Allow udc code to do any additional startup */ -void udc_startup_events(struct usb_device_instance *device) -{ - /* The DEVICE_INIT event puts the USB device in the state STATE_INIT */ - usbd_device_event_irq(device, DEVICE_INIT, 0); - - /* The DEVICE_CREATE event puts the USB device in the state - * STATE_ATTACHED */ - usbd_device_event_irq(device, DEVICE_CREATE, 0); - - /* Some USB controller driver implementations signal - * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. - * DEVICE_HUB_CONFIGURED causes a transition to the state - * STATE_POWERED, and DEVICE_RESET causes a transition to - * the state STATE_DEFAULT. - */ - udc_enable(device); -} - -/* Initialize h/w stuff */ -int udc_init(void) -{ - udc_device = NULL; - usbdbg("PXA27x usbd start"); - - /* Enable clock for USB device */ - writel(readl(CKEN) | CKEN11_USB, CKEN); - - /* Disable the UDC */ - udc_clear_mask_UDCCR(UDCCR_UDE); - - /* Disable IRQs: we don't use them */ - writel(0, UDCICR0); - writel(0, UDCICR1); - - return 0; -} diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 8f77412cc7..31ae9f74e7 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -32,6 +32,14 @@ config USB_XHCI_DWC3_OF_SIMPLE Support USB2/3 functionality in simple SoC integrations with USB controller based on the DesignWare USB3 IP Core. +config USB_XHCI_EXYNOS + bool "Support for Samsung Exynos5 family on-chip xHCI USB controller" + depends on ARCH_EXYNOS5 + default y + help + Enables support for he on-chip xHCI controller on Samsung Exynos5 + SoCs. + config USB_XHCI_MTK bool "Support for MediaTek on-chip xHCI USB controller" depends on ARCH_MEDIATEK @@ -116,11 +124,19 @@ config USB_XHCI_BRCM endif # USB_XHCI_HCD +config EHCI_DESC_BIG_ENDIAN + bool + +config EHCI_MMIO_BIG_ENDIAN + bool + config USB_EHCI_HCD bool "EHCI HCD (USB 2.0) support" default y if ARCH_MX5 || ARCH_MX6 depends on DM && OF_CONTROL select USB_HOST + select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN + select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN ---help--- The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. @@ -149,6 +165,14 @@ config USB_EHCI_ATMEL ---help--- Enables support for the on-chip EHCI controller on Atmel chips. +config USB_EHCI_EXYNOS + bool "Support for Samsung Exynos EHCI USB controller" + depends on ARCH_EXYNOS + default y + ---help--- + Enables support for the on-chip EHCI controller on Samsung Exynos + SoCs. + config USB_EHCI_MARVELL bool "Support for Marvell on-chip EHCI USB controller" depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X @@ -166,6 +190,7 @@ config USB_EHCI_MX5 config USB_EHCI_MX6 bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller" depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT + select EHCI_HCD_INIT_AFTER_RESET default y ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. @@ -173,6 +198,7 @@ config USB_EHCI_MX6 config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" depends on ARCH_MX7 || IMX8M + select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7 select PHY if IMX8M select NOP_PHY if IMX8M default y @@ -250,17 +276,38 @@ config USB_EHCI_GENERIC ---help--- Enables support for generic EHCI controller. +config EHCI_HCD_INIT_AFTER_RESET + bool + config USB_EHCI_FSL bool "Support for FSL on-chip EHCI USB controller" - select CONFIG_EHCI_HCD_INIT_AFTER_RESET + select EHCI_HCD_INIT_AFTER_RESET ---help--- Enables support for the on-chip EHCI controller on FSL chips. + +config USB_EHCI_TXFIFO_THRESH + hex + depends on USB_EHCI_TEGRA + default 0x10 + help + This parameter affects a TXFILLTUNING field that controls how much + data is sent to the latency fifo before it is sent to the wire. + Without this parameter, the default (2) causes occasional Data Buffer + Errors in OUT packets depending on the buffer address and size. + endif # USB_EHCI_HCD +config USB_OHCI_NEW + bool + +config SYS_USB_OHCI_CPU_INIT + bool + config USB_OHCI_HCD bool "OHCI HCD (USB 1.1) support" depends on DM && OF_CONTROL select USB_HOST + select USB_OHCI_NEW ---help--- The Open Host Controller Interface (OHCI) is a standard for accessing USB 1.1 host controller hardware. It does more in hardware than Intel's @@ -292,6 +339,19 @@ config USB_OHCI_DA8XX endif # USB_OHCI_HCD +config SYS_USB_OHCI_SLOT_NAME + string "Display name for the OHCI controller" + depends on USB_OHCI_NEW && !DM_USB + +config SYS_USB_OHCI_MAX_ROOT_PORTS + int "Maximal number of ports of the root hub" + depends on USB_OHCI_NEW + default 1 if ARCH_SUNXI + +config SYS_OHCI_SWAP_REG_ACCESS + bool "Perform byte swapping on OHCI controller register accesses" + depends on USB_OHCI_NEW + config USB_UHCI_HCD bool "UHCI HCD (most Intel and VIA) support" select USB_HOST @@ -340,3 +400,33 @@ config USB_R8A66597_HCD ---help--- This enables support for the on-chip Renesas R8A66597 USB 2.0 controller, present in various RZ and SH SoCs. + +config USB_ATMEL + bool "AT91 OHCI USB support" + depends on ARCH_AT91 + select SYS_USB_OHCI_CPU_INIT + select USB_OHCI_NEW + +choice + prompt "Clock for OHCI" + depends on USB_ATMEL + +config USB_ATMEL_CLK_SEL_PLLB + bool "PLLB" + +config USB_ATMEL_CLK_SEL_UPLL + bool "UPLL" + +endchoice + +config USB_OHCI_LPC32XX + bool "LPC32xx USB OHCI support" + depends on ARCH_LPC32XX + select SYS_USB_OHCI_CPU_INIT + select USB_OHCI_NEW + +config USB_MAX_CONTROLLER_COUNT + int "Maximum number of USB host controllers" + depends on USB_EHCI_FSL || USB_XHCI_FSL || \ + (SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB) + default 1 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7785b3744e..5fdb804116 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o -obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index cf1f882441..0569dd54ff 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -25,26 +25,15 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -#if CONFIG_IS_ENABLED(DM_USB) struct ehci_fsl_priv { struct ehci_ctrl ehci; fdt_addr_t hcd_base; char *phy_type; }; -#endif static void set_txfifothresh(struct usb_ehci *, u32); -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, struct ehci_hccr *hccr, struct ehci_hcor *hcor); -#else -static int ehci_fsl_init(int index, struct usb_ehci *ehci, - struct ehci_hccr *hccr, struct ehci_hcor *hcor); -#endif /* Check USB PHY clock valid */ static int usb_phy_clk_valid(struct usb_ehci *ehci) @@ -58,7 +47,6 @@ static int usb_phy_clk_valid(struct usb_ehci *ehci) } } -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_of_to_plat(struct udevice *dev) { struct ehci_fsl_priv *priv = dev_get_priv(dev); @@ -150,64 +138,11 @@ U_BOOT_DRIVER(ehci_fsl) = { .priv_auto = sizeof(struct ehci_fsl_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#else -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - * - * Excerpts from linux ehci fsl driver. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct ehci_ctrl *ehci_ctrl = container_of(hccr, - struct ehci_ctrl, hccr); - struct usb_ehci *ehci = NULL; - - switch (index) { - case 0: - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - break; - case 1: - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; - break; - default: - printf("ERROR: wrong controller index!!\n"); - return -EINVAL; - }; - - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275(); - - return ehci_fsl_init(index, ehci, *hccr, *hcor); -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} -#endif - -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, struct ehci_hccr *hccr, struct ehci_hcor *hcor) -#else -static int ehci_fsl_init(int index, struct usb_ehci *ehci, - struct ehci_hccr *hccr, struct ehci_hcor *hcor) -#endif { const char *phy_type = NULL; -#if !CONFIG_IS_ENABLED(DM_USB) - size_t len; - char current_usb_controller[5]; -#endif #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY char usb_phy[5]; @@ -230,18 +165,8 @@ static int ehci_fsl_init(int index, struct usb_ehci *ehci, out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ -#if CONFIG_IS_ENABLED(DM_USB) if (priv->phy_type) phy_type = priv->phy_type; -#else - memset(current_usb_controller, '\0', 5); - snprintf(current_usb_controller, sizeof(current_usb_controller), - "usb%d", index+1); - - if (hwconfig_sub(current_usb_controller, "phy_type")) - phy_type = hwconfig_subarg(current_usb_controller, - "phy_type", &len); -#endif else phy_type = env_get("usb_phy_type"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index e6355263cb..f033198a7c 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -25,10 +25,6 @@ #include "ehci.h" -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - /* * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. * Let's time out after 8 to have a little safety margin on top of that. diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index ab863f41b2..964a53bb7c 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -228,52 +228,6 @@ __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, mdelay(50); } -#if !CONFIG_IS_ENABLED(DM_USB) -static const struct ehci_ops mx5_ehci_ops = { - .powerup_fixup = mx5_ehci_powerup_fixup, -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct usb_ehci *ehci; - - /* The only user for this is efikamx-usb */ - ehci_set_controller_priv(index, NULL, &mx5_ehci_ops); - set_usboh3_clk(); - enable_usboh3_clk(true); - set_usb_phy_clk(); - enable_usb_phy1_clk(true); - enable_usb_phy2_clk(true); - mdelay(1); - - /* Do board specific initialization */ - board_ehci_hcd_init(CONFIG_MXC_USB_PORT); - - ehci = (struct usb_ehci *)(OTG_BASE_ADDR + - (0x200 * CONFIG_MXC_USB_PORT)); - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - setbits_le32(&ehci->usbmode, CM_HOST); - - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - setbits_le32(&ehci->portsc, USB_EN); - - mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); - mdelay(10); - - /* Do board specific post-initialization */ - board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); - - return 0; -} - -int ehci_hcd_stop(int index) -{ - return 0; -} -#else /* CONFIG_IS_ENABLED(DM_USB) */ struct ehci_mx5_priv_data { struct ehci_ctrl ctrl; struct usb_ehci *ehci; @@ -372,4 +326,3 @@ U_BOOT_DRIVER(usb_mx5) = { .priv_auto = sizeof(struct ehci_mx5_priv_data), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* !CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c deleted file mode 100644 index 1fb685e58d..0000000000 --- a/drivers/usb/host/ehci-mxc.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - */ - - -#include <common.h> -#include <usb.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <linux/delay.h> -#include <usb/ehci-ci.h> -#include <errno.h> - -#include "ehci.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX25_OTG_SIC_SHIFT 29 -#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) -#define MX25_OTG_PM_BIT (1 << 24) -#define MX25_OTG_PP_BIT (1 << 11) -#define MX25_OTG_OCPOL_BIT (1 << 3) - -#define MX25_H1_SIC_SHIFT 21 -#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) -#define MX25_H1_PP_BIT (1 << 18) -#define MX25_H1_PM_BIT (1 << 16) -#define MX25_H1_IPPUE_UP_BIT (1 << 7) -#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX25_H1_TLL_BIT (1 << 5) -#define MX25_H1_USBTE_BIT (1 << 4) -#define MX25_H1_OCPOL_BIT (1 << 2) - -#define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) - -#define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) - -#define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) - -#define MX35_OTG_SIC_SHIFT 29 -#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) -#define MX35_OTG_PM_BIT (1 << 24) -#define MX35_OTG_PP_BIT (1 << 11) -#define MX35_OTG_OCPOL_BIT (1 << 3) - -#define MX35_H1_SIC_SHIFT 21 -#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PP_BIT (1 << 18) -#define MX35_H1_PM_BIT (1 << 16) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) -#define MX35_H1_OCPOL_BIT (1 << 2) - -static int mxc_set_usbcontrol(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); -#if defined(CONFIG_MX31) - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } -#else -#error MXC EHCI USB driver not supported on this platform -#endif - writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); - - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct usb_ehci *ehci; -#ifdef CONFIG_MX31 - struct clock_control_regs *sc_regs = - (struct clock_control_regs *)CCM_BASE; - - __raw_readl(&sc_regs->ccmr); - __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; -#endif - - udelay(80); - - ehci = (struct usb_ehci *)(IMX_USB_BASE + - IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT); - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - setbits_le32(&ehci->usbmode, CM_HOST); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); - - udelay(10000); - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 9a614955fc..147b2fa145 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -112,82 +112,6 @@ static int __ehci_hcd_stop(struct ehci_mxs_port *port) return ehci_mxs_toggle_clock(port, 0); } -#if !CONFIG_IS_ENABLED(DM_USB) -static const struct ehci_mxs_port mxs_port[] = { -#ifdef CONFIG_EHCI_MXS_PORT0 - { - MXS_USBCTRL0_BASE, - (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE, - (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + - offsetof(struct mxs_clkctrl_regs, - hw_clkctrl_pll0ctrl0_reg)), - CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, - CLKCTRL_PLL0CTRL0_EN_USB_CLKS, - HW_DIGCTL_CTRL_USB0_CLKGATE, - }, -#endif -#ifdef CONFIG_EHCI_MXS_PORT1 - { - MXS_USBCTRL1_BASE, - (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE, - (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + - offsetof(struct mxs_clkctrl_regs, - hw_clkctrl_pll1ctrl0_reg)), - CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, - CLKCTRL_PLL1CTRL0_EN_USB_CLKS, - HW_DIGCTL_CTRL_USB1_CLKGATE, - }, -#endif -}; - -int __weak board_ehci_hcd_init(int port) -{ - return 0; -} - -int __weak board_ehci_hcd_exit(int port) -{ - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - - int ret; - const struct ehci_mxs_port *port; - - if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { - printf("Invalid port index (index = %d)!\n", index); - return -EINVAL; - } - - ret = board_ehci_hcd_init(index); - if (ret) - return ret; - - port = &mxs_port[index]; - return __ehci_hcd_init(port, init, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - int ret; - const struct ehci_mxs_port *port; - - if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { - printf("Invalid port index (index = %d)!\n", index); - return -EINVAL; - } - - port = &mxs_port[index]; - - ret = __ehci_hcd_stop(port); - board_ehci_hcd_exit(index); - - return ret; -} -#else /* CONFIG_IS_ENABLED(DM_USB) */ struct ehci_mxs_priv_data { struct ehci_ctrl ctrl; struct usb_ehci *ehci; @@ -367,4 +291,3 @@ U_BOOT_DRIVER(usb_mxs) = { .priv_auto = sizeof(struct ehci_mxs_priv_data), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* !CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 8ceabaf45c..9b955c1bd6 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -5,9 +5,6 @@ */ #include <common.h> - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) - #include <asm/arch/clk.h> int usb_cpu_init(void) @@ -65,5 +62,3 @@ int usb_cpu_init_fail(void) { return usb_cpu_stop(); } - -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index 163f0ef17b..5d23058aaf 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -14,10 +14,6 @@ #include <reset.h> #include "ohci.h" -#if !defined(CONFIG_USB_OHCI_NEW) -# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW" -#endif - struct generic_ohci { ohci_t ohci; struct clk *clocks; /* clock list */ diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index fedf0db9c7..9acef5ee4f 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -35,13 +35,6 @@ #include <asm/cache.h> #include <linux/delay.h> -#if defined(CONFIG_PCI_OHCI) -# include <pci.h> -#if !defined(CONFIG_PCI_OHCI_DEVNO) -#define CONFIG_PCI_OHCI_DEVNO 0 -#endif -#endif - #include <malloc.h> #include <memalign.h> #include <usb.h> @@ -53,7 +46,6 @@ #endif #if defined(CONFIG_CPU_ARM920T) || \ - defined(CONFIG_PCI_OHCI) || \ defined(CONFIG_PCI) || \ defined(CONFIG_SYS_OHCI_USE_NPS) # define OHCI_USE_NPS /* force NoPowerSwitching mode */ @@ -68,26 +60,6 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#if !CONFIG_IS_ENABLED(DM_USB) -#ifdef CONFIG_PCI_OHCI -static struct pci_device_id ohci_pci_ids[] = { - {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ - {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ - {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ - /* Please add supported PCI OHCI controller ids here */ - {0, 0} -}; -#endif -#endif - -#ifdef CONFIG_PCI_EHCI_DEVNO -static struct pci_device_id ehci_pci_ids[] = { - {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ - /* Please add supported PCI EHCI controller ids here */ - {0, 0} -}; -#endif - #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) #else @@ -2007,21 +1979,6 @@ static char ohci_inited = 0; int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { -#ifdef CONFIG_PCI_OHCI - pci_dev_t pdev; -#endif - -#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT - /* cpu dependant init */ - if (usb_cpu_init()) - return -1; -#endif - -#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT - /* board dependant init */ - if (board_usb_init(index, USB_INIT_HOST)) - return -1; -#endif memset(&gohci, 0, sizeof(ohci_t)); /* align the storage */ @@ -2036,28 +1993,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) gohci.disabled = 1; gohci.sleeping = 0; gohci.irq = -1; -#ifdef CONFIG_PCI_OHCI - pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); - - if (pdev != -1) { - u16 vid, did; - u32 base; - pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); - pci_read_config_word(pdev, PCI_DEVICE_ID, &did); - printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", - vid, did, (pdev >> 16) & 0xff, - (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); - printf("OHCI regs address 0x%08x\n", base); - gohci.regs = (struct ohci_regs *)base; - } else { - printf("%s: OHCI devnr: %d not found\n", __func__, - CONFIG_PCI_OHCI_DEVNO); - return -1; - } -#else gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; -#endif gohci.flags = 0; gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; @@ -2065,15 +2001,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) if (hc_reset (&gohci) < 0) { hc_release_ohci (&gohci); err ("can't reset usb-%s", gohci.slot_name); -#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT - /* board dependant cleanup */ - board_usb_cleanup(index, USB_INIT_HOST); -#endif - -#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT - /* cpu dependant cleanup */ - usb_cpu_init_fail(); -#endif return -1; } @@ -2081,15 +2008,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */ -#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT - /* board dependant cleanup */ - usb_board_stop(); -#endif - -#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT - /* cpu dependant cleanup */ - usb_cpu_stop(); -#endif return -1; } @@ -2112,17 +2030,6 @@ int usb_lowlevel_stop(int index) /* call hc_release_ohci() here ? */ hc_reset(&gohci); -#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT - /* board dependant cleanup */ - if (usb_board_stop()) - return -1; -#endif - -#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT - /* cpu dependant cleanup */ - if (usb_cpu_stop()) - return -1; -#endif /* This driver is no longer initialised. It needs a new low-level * init (board/cpu) before it can be used again. */ ohci_inited = 0; diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index a38cd25eb8..7699f2e6b1 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -151,7 +151,7 @@ struct ohci_hcca { * Maximum number of root hub ports. */ #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS -# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #endif /* diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 80871908dc..e67e09e31e 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -20,16 +20,11 @@ #include <dm.h> /* Declare global data pointer */ -#if !CONFIG_IS_ENABLED(DM_USB) -static struct fsl_xhci fsl_xhci; -unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; -#else struct xhci_fsl_priv { struct xhci_ctrl xhci; fdt_addr_t hcd_base; struct fsl_xhci ctx; }; -#endif __weak int __board_usb_init(int index, enum usb_init_type init) { @@ -108,7 +103,6 @@ static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) return 0; } -#if CONFIG_IS_ENABLED(DM_USB) static int xhci_fsl_probe(struct udevice *dev) { struct xhci_fsl_priv *priv = dev_get_priv(dev); @@ -174,44 +168,3 @@ U_BOOT_DRIVER(xhci_fsl) = { .priv_auto = sizeof(struct xhci_fsl_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#else -int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) -{ - struct fsl_xhci *ctx = &fsl_xhci; - int ret = 0; - - ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; - ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); - - ret = board_usb_init(index, USB_INIT_HOST); - if (ret != 0) { - puts("Failed to initialize board for USB\n"); - return ret; - } - - fsl_apply_xhci_errata(); - - ret = fsl_xhci_core_init(ctx); - if (ret < 0) { - puts("Failed to initialize xhci\n"); - return ret; - } - - *hccr = (struct xhci_hccr *)ctx->hcd; - *hcor = (struct xhci_hcor *)((uintptr_t) *hccr - + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); - - debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n", - (uintptr_t)*hccr, (uintptr_t)*hcor, - (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); - - return ret; -} - -void xhci_hcd_stop(int index) -{ - struct fsl_xhci *ctx = &fsl_xhci; - - fsl_xhci_core_exit(ctx); -} -#endif diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index ad73ba12e2..dbeb88afe3 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -37,10 +37,6 @@ #include <linux/errno.h> #include <linux/iopoll.h> -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - static struct descriptor { struct usb_hub_descriptor hub; struct usb_device_descriptor device; @@ -115,13 +111,8 @@ static struct descriptor { }, }; -#if !CONFIG_IS_ENABLED(DM_USB) -static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; -#endif - struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) { -#if CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; /* Find the USB controller */ @@ -130,9 +121,6 @@ struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) dev = dev->parent) ; return dev_get_priv(dev); -#else - return udev->controller; -#endif } /** @@ -752,13 +740,6 @@ static int _xhci_alloc_device(struct usb_device *udev) return 0; } -#if !CONFIG_IS_ENABLED(DM_USB) -int usb_alloc_device(struct usb_device *udev) -{ - return _xhci_alloc_device(udev); -} -#endif - /* * Full speed devices may have a max packet size greater than 8 bytes, but the * USB core doesn't know that until it reads the first 8 bytes of the @@ -1267,95 +1248,6 @@ static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl) return 0; } -#if !CONFIG_IS_ENABLED(DM_USB) -int submit_control_msg(struct usb_device *udev, unsigned long pipe, - void *buffer, int length, struct devrequest *setup) -{ - struct usb_device *hop = udev; - - if (hop->parent) - while (hop->parent->parent) - hop = hop->parent; - - return _xhci_submit_control_msg(udev, pipe, buffer, length, setup, - hop->portnr); -} - -int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer, - int length) -{ - return _xhci_submit_bulk_msg(udev, pipe, buffer, length); -} - -int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer, - int length, int interval, bool nonblock) -{ - return _xhci_submit_int_msg(udev, pipe, buffer, length, interval, - nonblock); -} - -/** - * Intialises the XHCI host controller - * and allocates the necessary data structures - * - * @param index index to the host controller data structure - * Return: pointer to the intialised controller - */ -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - struct xhci_hccr *hccr; - struct xhci_hcor *hcor; - struct xhci_ctrl *ctrl; - int ret; - - *controller = NULL; - - if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0) - return -ENODEV; - - if (xhci_reset(hcor) != 0) - return -ENODEV; - - ctrl = &xhcic[index]; - - ctrl->hccr = hccr; - ctrl->hcor = hcor; - - ret = xhci_lowlevel_init(ctrl); - - if (ret) { - ctrl->hccr = NULL; - ctrl->hcor = NULL; - } else { - *controller = &xhcic[index]; - } - - return ret; -} - -/** - * Stops the XHCI host controller - * and cleans up all the related data structures - * - * @param index index to the host controller data structure - * Return: none - */ -int usb_lowlevel_stop(int index) -{ - struct xhci_ctrl *ctrl = (xhcic + index); - - if (ctrl->hcor) { - xhci_lowlevel_stop(ctrl); - xhci_hcd_stop(index); - xhci_cleanup(ctrl); - } - - return 0; -} -#endif /* CONFIG_IS_ENABLED(DM_USB) */ - -#if CONFIG_IS_ENABLED(DM_USB) - static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) @@ -1546,5 +1438,3 @@ struct dm_usb_ops xhci_usb_ops = { .update_hub_device = xhci_update_hub_device, .get_max_xfer_size = xhci_get_max_xfer_size, }; - -#endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 965b587927..4ecc158c46 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -583,6 +583,8 @@ config ATMEL_HLCD source "drivers/video/ti/Kconfig" +source "drivers/video/exynos/Kconfig" + config LOGICORE_DP_TX bool "Enable Logicore DP TX driver" depends on DISPLAY diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 259658074b..7019b26396 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -36,9 +36,7 @@ obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o obj-$(CONFIG_NXP_TDA19988) += tda19988.o obj-$(CONFIG_OSD) += video_osd-uclass.o -obj-$(CONFIG_PXA_LCD) += pxa_lcd.o obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o -obj-$(CONFIG_S6E8AX0) += s6e8ax0.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig new file mode 100644 index 0000000000..37e661b1ed --- /dev/null +++ b/drivers/video/exynos/Kconfig @@ -0,0 +1,20 @@ + +menuconfig VIDEO_EXYNOS + bool "Enable Exynos video support" + depends on DM_VIDEO + help + Enable support for various video output options on Exynos SoCs. + +if VIDEO_EXYNOS + +config EXYNOS_DP + bool "Exynos Display Port support" + +config EXYNOS_FB + bool "Exynos FIMD support" + +config EXYNOS_MIPI_DSIM + bool "Exynos MIPI DSI support" + depends on EXYNOS_FB + +endif diff --git a/drivers/video/exynos/exynos_pwm_bl.c b/drivers/video/exynos/exynos_pwm_bl.c deleted file mode 100644 index a3d467aa23..0000000000 --- a/drivers/video/exynos/exynos_pwm_bl.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PWM BACKLIGHT driver for Board based on EXYNOS. - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - * - * Derived from linux/drivers/video/backlight/pwm_backlight.c - */ - -#include <common.h> -#include <pwm.h> -#include <linux/types.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/arch/pwm.h> -#include <asm/arch/pwm_backlight.h> - -static struct pwm_backlight_data *pwm; - -static int exynos_pwm_backlight_update_status(void) -{ - int brightness = pwm->brightness; - int max = pwm->max_brightness; - - if (brightness == 0) { - pwm_config(pwm->pwm_id, 0, pwm->period); - pwm_disable(pwm->pwm_id); - } else { - pwm_config(pwm->pwm_id, - brightness * pwm->period / max, pwm->period); - pwm_enable(pwm->pwm_id); - } - return 0; -} - -int exynos_pwm_backlight_init(struct pwm_backlight_data *pd) -{ - pwm = pd; - - exynos_pwm_backlight_update_status(); - - return 0; -} diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c deleted file mode 100644 index 21ade8d93c..0000000000 --- a/drivers/video/pxa_lcd.c +++ /dev/null @@ -1,549 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PXA LCD Controller - * - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -#include <common.h> -#include <log.h> -#include <asm/arch/pxa-regs.h> -#include <asm/io.h> -#include <lcd.h> -#include <linux/types.h> -#include <stdarg.h> -#include <stdio_dev.h> - -/* #define DEBUG */ - -#ifdef CONFIG_LCD - -/*----------------------------------------------------------------------*/ -/* - * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for - * your display. - */ - -#ifdef CONFIG_PXA_VGA -/* LCD outputs connected to a video DAC */ -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f8 -# define REG_LCCR3 0x0300FF01 - -/* 640x480x16 @ 61 Hz */ -vidinfo_t panel_info = { - .vl_col = 640, - .vl_row = 480, - .vl_width = 640, - .vl_height = 480, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 0, - .vl_clor = 0, - .vl_tft = 1, - .vl_hpw = 40, - .vl_blw = 56, - .vl_elw = 56, - .vl_vpw = 20, - .vl_bfw = 8, - .vl_efw = 8, -}; -#endif /* CONFIG_PXA_VIDEO */ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_SHARP_LM8V31 - -# define LCD_BPP LCD_COLOR8 -# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x0030087C -# define REG_LCCR3 0x0340FF08 - -vidinfo_t panel_info = { - .vl_col = 640, - .vl_row = 480, - .vl_width = 157, - .vl_height = 118, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 0, - .vl_hpw = 1, - .vl_blw = 3, - .vl_elw = 3, - .vl_vpw = 1, - .vl_bfw = 0, - .vl_efw = 0, -}; -#endif /* CONFIG_SHARP_LM8V31 */ -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_VOIPAC_LCD - -# define LCD_BPP LCD_COLOR8 -# define LCD_INVERT_COLORS - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x043008f8 -# define REG_LCCR3 0x0340FF08 - -vidinfo_t panel_info = { - .vl_col = 640, - .vl_row = 480, - .vl_width = 157, - .vl_height = 118, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 32, - .vl_blw = 144, - .vl_elw = 32, - .vl_vpw = 2, - .vl_bfw = 13, - .vl_efw = 30, -}; -#endif /* CONFIG_VOIPAC_LCD */ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_HITACHI_SX14 -/* Hitachi SX14Q004-ZZA color STN LCD */ -#define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -#define REG_LCCR0 0x00301079 -#define REG_LCCR3 0x0340FF20 - -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 240, - .vl_width = 167, - .vl_height = 109, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 1, - .vl_splt = 0, - .vl_clor = 1, - .vl_tft = 0, - .vl_hpw = 1, - .vl_blw = 1, - .vl_elw = 1, - .vl_vpw = 7, - .vl_bfw = 0, - .vl_efw = 0, -}; -#endif /* CONFIG_HITACHI_SX14 */ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_LMS283GF05 - -# define LCD_BPP LCD_COLOR8 -/*# define LCD_INVERT_COLORS*/ - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x043008f8 -# define REG_LCCR3 0x03b00009 - -vidinfo_t panel_info = { - .vl_col = 240, - .vl_row = 320, - .vl_rot = 3, - .vl_width = 240, - .vl_height = 320, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 4, - .vl_blw = 4, - .vl_elw = 8, - .vl_vpw = 4, - .vl_bfw = 4, - .vl_efw = 8, -}; -#endif /* CONFIG_LMS283GF05 */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_LQ038J7DH53 - -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f9 -# define REG_LCCR3 0x03700004 - -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 480, - .vl_width = 320, - .vl_height = 480, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 0x04, - .vl_blw = 0x20, - .vl_elw = 0x01, - .vl_vpw = 0x01, - .vl_bfw = 0x04, - .vl_efw = 0x01, -}; -#endif /* CONFIG_LQ038J7DH53 */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_LITTLETON_LCD -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f8 -# define REG_LCCR3 0x0300FF04 - -vidinfo_t panel_info = { - .vl_col = 480, - .vl_row = 640, - .vl_width = 480, - .vl_height = 640, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 0, - .vl_clor = 0, - .vl_tft = 1, - .vl_hpw = 9, - .vl_blw = 8, - .vl_elw = 24, - .vl_vpw = 2, - .vl_bfw = 2, - .vl_efw = 4, -}; -#endif /* CONFIG_LITTLETON_LCD */ - -/*----------------------------------------------------------------------*/ - -static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid); -static void pxafb_setup_gpio (vidinfo_t *vid); -static void pxafb_enable_controller (vidinfo_t *vid); -static int pxafb_init (vidinfo_t *vid); - -/************************************************************************/ -/* --------------- PXA chipset specific functions ------------------- */ -/************************************************************************/ - -ushort *configuration_get_cmap(void) -{ - struct pxafb_info *fbi = &panel_info.pxa; - return (ushort *)fbi->palette; -} - -void lcd_ctrl_init (void *lcdbase) -{ - pxafb_init_mem(lcdbase, &panel_info); - pxafb_init(&panel_info); - pxafb_setup_gpio(&panel_info); - pxafb_enable_controller(&panel_info); -} - -/*----------------------------------------------------------------------*/ -#if LCD_BPP == LCD_COLOR8 -void -lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ - struct pxafb_info *fbi = &panel_info.pxa; - unsigned short *palette = (unsigned short *)fbi->palette; - u_int val; - - if (regno < fbi->palette_size) { - val = ((red << 8) & 0xf800); - val |= ((green << 4) & 0x07e0); - val |= (blue & 0x001f); - -#ifdef LCD_INVERT_COLORS - palette[regno] = ~val; -#else - palette[regno] = val; -#endif - } - - debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", - regno, &palette[regno], - red, green, blue, - palette[regno]); -} -#endif /* LCD_COLOR8 */ - -/*----------------------------------------------------------------------*/ -__weak void lcd_enable(void) -{ -} - -/************************************************************************/ -/* ** PXA255 specific routines */ -/************************************************************************/ - -/* - * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, - * descriptors and palette areas. - */ -ulong calc_fbsize (void) -{ - ulong size; - int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; - - size = line_length * panel_info.vl_row; - size += PAGE_SIZE; - - return size; -} - -static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid) -{ - u_long palette_mem_size; - struct pxafb_info *fbi = &vid->pxa; - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; - - fbi->screen = (u_long)lcdbase; - - fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; - palette_mem_size = fbi->palette_size * sizeof(u16); - - debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); - /* locate palette and descs at end of page following fb */ - fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; - - return 0; -} -#ifdef CONFIG_CPU_MONAHANS -static inline void pxafb_setup_gpio (vidinfo_t *vid) {} -#else -static void pxafb_setup_gpio (vidinfo_t *vid) -{ - u_long lccr0; - - /* - * setup is based on type of panel supported - */ - - lccr0 = vid->pxa.reg_lccr0; - - /* 4 bit interface */ - if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD)) - { - debug("Setting GPIO for 4 bit data\n"); - /* bits 58-61 */ - writel(readl(GPDR1) | (0xf << 26), GPDR1); - writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20), - GAFR1_U); - - /* bits 74-77 */ - writel(readl(GPDR2) | (0xf << 10), GPDR2); - writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), - GAFR2_L); - } - - /* 8 bit interface */ - else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) || - (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS))) - { - debug("Setting GPIO for 8 bit data\n"); - /* bits 58-65 */ - writel(readl(GPDR1) | (0x3f << 26), GPDR1); - writel(readl(GPDR2) | (0x3), GPDR2); - - writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), - GAFR1_U); - writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L); - - /* bits 74-77 */ - writel(readl(GPDR2) | (0xf << 10), GPDR2); - writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), - GAFR2_L); - } - - /* 16 bit interface */ - else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS))) - { - debug("Setting GPIO for 16 bit data\n"); - /* bits 58-77 */ - writel(readl(GPDR1) | (0x3f << 26), GPDR1); - writel(readl(GPDR2) | 0x00003fff, GPDR2); - - writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), - GAFR1_U); - writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L); - } - else - { - printf("pxafb_setup_gpio: unable to determine bits per pixel\n"); - } -} -#endif - -static void pxafb_enable_controller (vidinfo_t *vid) -{ - debug("Enabling LCD controller\n"); - - /* Sequence from 11.7.10 */ - writel(vid->pxa.reg_lccr3, LCCR3); - writel(vid->pxa.reg_lccr2, LCCR2); - writel(vid->pxa.reg_lccr1, LCCR1); - writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0); - writel(vid->pxa.fdadr0, FDADR0); - writel(vid->pxa.fdadr1, FDADR1); - writel(readl(LCCR0) | LCCR0_ENB, LCCR0); - -#ifdef CONFIG_CPU_MONAHANS - writel(readl(CKENA) | CKENA_1_LCD, CKENA); -#else - writel(readl(CKEN) | CKEN16_LCD, CKEN); -#endif - - debug("FDADR0 = 0x%08x\n", readl(FDADR0)); - debug("FDADR1 = 0x%08x\n", readl(FDADR1)); - debug("LCCR0 = 0x%08x\n", readl(LCCR0)); - debug("LCCR1 = 0x%08x\n", readl(LCCR1)); - debug("LCCR2 = 0x%08x\n", readl(LCCR2)); - debug("LCCR3 = 0x%08x\n", readl(LCCR3)); -} - -static int pxafb_init (vidinfo_t *vid) -{ - struct pxafb_info *fbi = &vid->pxa; - - debug("Configuring PXA LCD\n"); - - fbi->reg_lccr0 = REG_LCCR0; - fbi->reg_lccr3 = REG_LCCR3; - - debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n", - vid->vl_col, vid->vl_hpw, - vid->vl_blw, vid->vl_elw); - debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n", - vid->vl_row, vid->vl_vpw, - vid->vl_bfw, vid->vl_efw); - - fbi->reg_lccr1 = - LCCR1_DisWdth(vid->vl_col) + - LCCR1_HorSnchWdth(vid->vl_hpw) + - LCCR1_BegLnDel(vid->vl_blw) + - LCCR1_EndLnDel(vid->vl_elw); - - fbi->reg_lccr2 = - LCCR2_DisHght(vid->vl_row) + - LCCR2_VrtSnchWdth(vid->vl_vpw) + - LCCR2_BegFrmDel(vid->vl_bfw) + - LCCR2_EndFrmDel(vid->vl_efw); - - fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP); - fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH) - | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH); - - - /* setup dma descriptors */ - fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); - fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); - fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); - - #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \ - (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \ - (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)) - - /* populate descriptors */ - fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; - fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL; - fbi->dmadesc_fblow->fidr = 0; - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL; - - fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */ - - fbi->dmadesc_fbhigh->fsadr = fbi->screen; - fbi->dmadesc_fbhigh->fidr = 0; - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL; - - fbi->dmadesc_palette->fsadr = fbi->palette; - fbi->dmadesc_palette->fidr = 0; - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; - - if( NBITS(vid->vl_bpix) < 12) - { - /* assume any mode with <12 bpp is palette driven */ - fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh; - fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette; - /* flips back and forth between pal and fbhigh */ - fbi->fdadr0 = (u_long)fbi->dmadesc_palette; - } - else - { - /* palette shouldn't be loaded in true-color mode */ - fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh; - fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */ - } - - debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow); - debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh); - debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette); - - debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr); - debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr); - debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr); - - debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr); - debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr); - debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr); - - debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd); - debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd); - debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd); - - return 0; -} - -/************************************************************************/ -/************************************************************************/ - -#endif /* CONFIG_LCD */ diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c deleted file mode 100644 index 497258f3de..0000000000 --- a/drivers/video/s6e8ax0.c +++ /dev/null @@ -1,265 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - */ - -#include <common.h> -#include <asm/arch/mipi_dsim.h> -#include <linux/delay.h> - -#include "exynos/exynos_mipi_dsi_lowlevel.h" -#include "exynos/exynos_mipi_dsi_common.h" - -static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - int reverse = dsim_dev->dsim_lcd_dev->reverse_panel; - static const unsigned char data_to_send[] = { - 0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c, - 0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20, - 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, - 0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3, - 0xff, 0xff, 0xc8 - }; - - static const unsigned char data_to_send_reverse[] = { - 0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c, - 0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20, - 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, - 0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1, - 0xf6, 0xf6, 0xc1 - }; - - if (reverse) { - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send_reverse, - ARRAY_SIZE(data_to_send_reverse)); - } else { - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); - } -} - -static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf2, 0x80, 0x03, 0x0d - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - /* 7500K 2.2 Set : 30cd */ - static const unsigned char data_to_send[] = { - 0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad, - 0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1, - 0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74, - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf7, 0x03 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf6, 0x00, 0x02, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0, - 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe3, 0x40 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xb1, 0x04, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0x29, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0x11, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf0, 0x5a, 0x5a - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf1, 0x5a, 0x5a - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev) -{ - /* - * in case of setting gamma and panel condition at first, - * it shuold be setting like below. - * set_gamma() -> set_panel_condition() - */ - - s6e8ax0_apply_level1_key(dsim_dev); - s6e8ax0_apply_mtp_key(dsim_dev); - - s6e8ax0_sleep_out(dsim_dev); - mdelay(5); - s6e8ax0_panel_cond(dsim_dev); - s6e8ax0_display_cond(dsim_dev); - s6e8ax0_gamma_cond(dsim_dev); - s6e8ax0_gamma_update(dsim_dev); - - s6e8ax0_etc_source_control(dsim_dev); - s6e8ax0_elvss_set(dsim_dev); - s6e8ax0_etc_pentile_control(dsim_dev); - s6e8ax0_etc_mipi_control1(dsim_dev); - s6e8ax0_etc_mipi_control2(dsim_dev); - s6e8ax0_etc_power_control(dsim_dev); - s6e8ax0_etc_mipi_control3(dsim_dev); - s6e8ax0_etc_mipi_control4(dsim_dev); -} - -static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev) -{ - s6e8ax0_panel_init(dsim_dev); - - return 0; -} - -static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev) -{ - s6e8ax0_display_on(dsim_dev); -} - -static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = { - .name = "s6e8ax0", - .id = -1, - - .mipi_panel_init = s6e8ax0_panel_set, - .mipi_display_on = s6e8ax0_display_enable, -}; - -void s6e8ax0_init(void) -{ - exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver); -} diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index c3eb8a8aec..532ada89c1 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -64,8 +64,8 @@ config ULP_WATCHDOG config DESIGNWARE_WATCHDOG bool "Designware watchdog timer support" - select HW_WATCHDOG if !WDT - default y if WDT && ROCKCHIP_RK3399 + depends on WDT + default y if ROCKCHIP_RK3399 help Enable this to support Designware Watchdog Timer IP, present e.g. on Altera SoCFPGA SoCs. diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index cfec29bd15..cad756aeaf 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -60,26 +60,6 @@ static void designware_wdt_reset_common(void __iomem *base) writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR); } -#if !CONFIG_IS_ENABLED(WDT) -void hw_watchdog_reset(void) -{ - designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE); -} - -void hw_watchdog_init(void) -{ - /* reset to disable the watchdog */ - hw_watchdog_reset(); - /* set timer in miliseconds */ - designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE, - CONFIG_DW_WDT_CLOCK_KHZ, - CONFIG_WATCHDOG_TIMEOUT_MSECS); - /* enable the watchdog */ - designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE); - /* reset the watchdog */ - hw_watchdog_reset(); -} -#else static int designware_wdt_reset(struct udevice *dev) { struct designware_wdt_priv *priv = dev_get_priv(dev); @@ -195,4 +175,3 @@ U_BOOT_DRIVER(designware_wdt) = { .ops = &designware_wdt_ops, .flags = DM_FLAG_PRE_RELOC, }; -#endif diff --git a/dts/Kconfig b/dts/Kconfig index f1d05cc080..bc5f22029f 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -534,6 +534,7 @@ endif config VPL_OF_REAL def_bool y + depends on VPL help Indicates that a real devicetree is available which can be accessed at runtime. This means that dev_read_...() functions can be used to diff --git a/env/Kconfig b/env/Kconfig index 2f625b2257..238e4c70cf 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -30,6 +30,22 @@ config ENV_OVERWRITE Use this to permit overriding of certain environmental variables like Ethernet and Serial +config ENV_MIN_ENTRIES + int "Minimum number of entries in the environment hashtable" + default 64 + help + Minimum number of entries in the hash table that is used internally + to store the environment settings. + +config ENV_MAX_ENTRIES + int "Maximumm number of entries in the environment hashtable" + default 512 + help + Maximum number of entries in the hash table that is used internally + to store the environment settings. The default setting is supposed to + be generous and should work in most cases. This setting can be used + to tune behaviour; see lib/hashtable.c for details. + config ENV_IS_NOWHERE bool "Environment is not stored" default y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ @@ -248,14 +264,6 @@ config ENV_IS_IN_NAND during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be aligned to an erase block boundary. - - CONFIG_ENV_RANGE (optional): - - Specifies the length of the region in which the environment - can be written. This should be a multiple of the NAND device's - block size. Specifying a range with more erase blocks than - are needed to hold CONFIG_ENV_SIZE allows bad blocks within - the range to be avoided. - - CONFIG_ENV_OFFSET_OOB (optional): Enables support for dynamically retrieving the offset of the @@ -264,6 +272,16 @@ config ENV_IS_IN_NAND Currently, CONFIG_ENV_OFFSET_REDUND is not supported when using CONFIG_ENV_OFFSET_OOB. +config ENV_RANGE + hex "Length of the region in which the environment can be written" + depends on ENV_IS_IN_NAND + range ENV_SIZE 0x7fffffff + default ENV_SIZE + help + This should be a multiple of the NAND device's block size. + Specifying a range with more erase blocks than are needed to hold + CONFIG_ENV_SIZE allows bad blocks within the range to be avoided. + config ENV_IS_IN_NVRAM bool "Environment in a non-volatile RAM" depends on !CHAIN_OF_TRUST diff --git a/env/ext4.c b/env/ext4.c index 9f65afb8a4..47e05a4891 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -31,6 +31,7 @@ #include <errno.h> #include <ext4fs.h> #include <mmc.h> +#include <scsi.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; @@ -146,6 +147,10 @@ static int env_ext4_load(void) if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) + if (!strcmp(ifname, "scsi")) + scsi_scan(true); +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); @@ -17,6 +17,7 @@ #include <errno.h> #include <fat.h> #include <mmc.h> +#include <scsi.h> #include <asm/cache.h> #include <asm/global_data.h> #include <linux/stddef.h> @@ -128,7 +129,12 @@ static int env_fat_load(void) if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif - +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) + if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) + scsi_scan(true); +#endif +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); if (part < 0) diff --git a/env/nand.c b/env/nand.c index 21aa367d5b..df300b1317 100644 --- a/env/nand.c +++ b/env/nand.c @@ -33,10 +33,6 @@ #error CONFIG_ENV_OFFSET_REDUND must have CONFIG_CMD_SAVEENV & CONFIG_CMD_NAND #endif -#ifndef CONFIG_ENV_RANGE -#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE -#endif - #if defined(ENV_IS_EMBEDDED) static env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) @@ -201,10 +197,6 @@ static int env_nand_save(void) #endif }; - - if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) - return 1; - ret = env_export(env_new); if (ret) return ret; diff --git a/fs/cbfs/Kconfig b/fs/cbfs/Kconfig index 03980d830d..b6639928f4 100644 --- a/fs/cbfs/Kconfig +++ b/fs/cbfs/Kconfig @@ -9,6 +9,7 @@ config FS_CBFS config SPL_FS_CBFS bool "Enable CBFS (Coreboot Filesystem) in SPL" + depends on SPL help Define this to enable support for reading from a Coreboot filesystem. This is a ROM-based filesystem used for accessing files diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index e3a4c0bca2..034c41a703 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -1757,6 +1757,8 @@ void ubifs_umount(struct ubifs_info *c) kfree(c->bottom_up_buf); ubifs_debugging_exit(c); #ifdef __UBOOT__ + ubi_close_volume(c->ubi); + mutex_unlock(&c->umount_mutex); /* Finally free U-Boot's global copy of superblock */ if (ubifs_sb != NULL) { free(ubifs_sb->s_fs_info); @@ -2058,9 +2060,9 @@ static void ubifs_put_super(struct super_block *sb) ubifs_umount(c); #ifndef __UBOOT__ bdi_destroy(&c->bdi); -#endif ubi_close_volume(c->ubi); mutex_unlock(&c->umount_mutex); +#endif } #endif @@ -2327,6 +2329,9 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) out_umount: ubifs_umount(c); +#ifdef __UBOOT__ + goto out; +#endif out_unlock: mutex_unlock(&c->umount_mutex); #ifndef __UBOOT__ diff --git a/include/bootcount.h b/include/bootcount.h index fccee7e15b..bfa5d46427 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -72,14 +72,6 @@ ulong bootcount_load(void); #if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_TPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT) -#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE) -# if __BYTE_ORDER == __LITTLE_ENDIAN -# define CONFIG_SYS_BOOTCOUNT_LE -# else -# define CONFIG_SYS_BOOTCOUNT_BE -# endif -#endif - #ifdef CONFIG_SYS_BOOTCOUNT_LE static inline void raw_bootcount_store(volatile u32 *addr, u32 data) { diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index c55023889c..c6e9c49741 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -70,18 +70,23 @@ #ifdef CONFIG_CMD_UBIFS #define BOOTENV_SHARED_UBIFS \ "ubifs_boot=" \ - "env exists bootubipart || " \ - "env set bootubipart UBI; " \ - "env exists bootubivol || " \ - "env set bootubivol boot; " \ "if ubi part ${bootubipart} && " \ - "ubifsmount ubi${devnum}:${bootubivol}; " \ + "ubifsmount ubi0:${bootubivol}; " \ "then " \ "devtype=ubi; " \ + "devnum=ubi0; " \ + "bootfstype=ubifs; " \ + "distro_bootpart=${bootubivol}; " \ "run scan_dev_for_boot; " \ + "ubifsumount; " \ "fi\0" -#define BOOTENV_DEV_UBIFS BOOTENV_DEV_BLKDEV -#define BOOTENV_DEV_NAME_UBIFS BOOTENV_DEV_NAME_BLKDEV +#define BOOTENV_DEV_UBIFS(devtypeu, devtypel, instance, bootubipart, bootubivol) \ + "bootcmd_ubifs" #instance "=" \ + "bootubipart=" #bootubipart "; " \ + "bootubivol=" #bootubivol "; " \ + "run ubifs_boot\0" +#define BOOTENV_DEV_NAME_UBIFS(devtypeu, devtypel, instance, bootubipart, bootubivol) \ + #devtypel #instance " " #else #define BOOTENV_SHARED_UBIFS #define BOOTENV_DEV_UBIFS \ @@ -411,13 +416,13 @@ BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE #endif -#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \ - BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance, ...) \ + BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance, ## __VA_ARGS__) #define BOOTENV_BOOT_TARGETS \ "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0" -#define BOOTENV_DEV(devtypeu, devtypel, instance) \ - BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance) +#define BOOTENV_DEV(devtypeu, devtypel, instance, ...) \ + BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance, ## __VA_ARGS__) #define BOOTENV \ BOOTENV_SHARED_HOST \ BOOTENV_SHARED_MMC \ diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 3922241be0..380c906ba8 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -10,10 +10,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST -#ifndef CONFIG_EXTRA_ENV -#define CONFIG_EXTRA_ENV "" -#endif - /* * Control should not reach back to uboot after validation of images * for secure boot flow and therefore bootscript should have @@ -21,43 +17,22 @@ * after validating images, core should just spin. */ -/* - * Define the key hash for boot script here if public/private key pair used to - * sign bootscript are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_BOOTSCRIPT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - */ - #ifdef CONFIG_USE_BOOTARGS -#define CONFIG_SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" +#define SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" #else -#define CONFIG_SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ +#define SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ "rw console=ttyS0,115200 ramdisk_size=600000\';" #endif - -#ifdef CONFIG_BOOTSCRIPT_KEY_HASH -#define CONFIG_SECBOOT \ +#define SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - CONFIG_SET_BOOTARGS \ - CONFIG_EXTRA_ENV \ - "esbc_validate $bs_hdraddr " \ - __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ - "source $img_addr;" \ - "esbc_halt\0" -#else -#define CONFIG_SECBOOT \ - "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - CONFIG_SET_BOOTARGS \ - CONFIG_EXTRA_ENV \ + SET_BOOTARGS \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt\0" -#endif #ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_COPY_ENV \ +#define BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ "setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ @@ -68,33 +43,28 @@ /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_NAND_BOOT) || \ defined(CONFIG_SD_BOOT) -#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_COPY_CMD \ +#if defined(CONFIG_NAND_BOOT) +#define BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "nand read $bs_ram $bs_device $bs_size ;" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_BS_COPY_CMD \ +#define BS_COPY_CMD \ "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "mmc read $bs_ram $bs_device $bs_size ;" #endif #else -#define CONFIG_BS_COPY_CMD \ +#define BS_COPY_CMD \ "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ "cp.b $bs_device $bs_ram $bs_size ;" #endif +#else /* !CONFIG_BOOTSCRIPT_COPY_RAM */ +#define BS_COPY_ENV +#define BS_COPY_CMD #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ -#ifndef CONFIG_BS_COPY_ENV -#define CONFIG_BS_COPY_ENV -#endif - -#ifndef CONFIG_BS_COPY_CMD -#define CONFIG_BS_COPY_CMD -#endif - -#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \ - CONFIG_BS_COPY_CMD \ - CONFIG_SECBOOT +#define CHAIN_BOOT_CMD BS_COPY_ENV \ + BS_COPY_CMD \ + SECBOOT #endif #endif diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index fec73ba342..c773164c86 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -17,15 +17,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -87,7 +78,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index ea89b03c66..79448cf440 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -22,15 +22,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) @@ -93,7 +84,6 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 4c1348c79d..cac9b24ead 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -19,12 +19,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*); -#ifdef CONFIG_IDE -/* ATA */ -# define CONFIG_IDE_PREINIT 1 -# undef CONFIG_LBA48 -#endif - #ifdef CONFIG_DRIVER_DM9000 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE @@ -96,7 +90,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /* FLASH organization */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 4a2b37653e..2fa1e4356e 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -32,15 +32,6 @@ env/embedded.o(.text); #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 # define CONFIG_SERVERIP 192.162.1.1 diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 5e6d085624..292578fc15 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -33,15 +33,6 @@ /* Available command configuration */ -#ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#endif -#endif - /* I2C */ #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) @@ -96,7 +87,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index bb6fbac687..9f06f41ce1 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -30,15 +30,6 @@ env/embedded.o(.text*); #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 # define CONFIG_SERVERIP 192.162.1.1 diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index b38260ed09..4d8f752777 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -22,18 +22,9 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 -#define CONFIG_SYS_UNIFY_CACHE - #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_TX_ETH_BUFFER 8 # define CONFIG_SYS_FEC_BUF_USE_SRAM - -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ #endif #define CONFIG_SYS_RTC_CNT (0x8000) @@ -101,7 +92,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index c65f26cc09..87d3e8fb15 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -22,17 +22,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#define CONFIG_SYS_UNIFY_CACHE - -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -97,7 +86,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 7e45d35879..d920587c37 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -24,17 +24,6 @@ #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ -#define CONFIG_SYS_UNIFY_CACHE - -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* I2C */ #ifdef CONFIG_MCFFEC @@ -99,7 +88,6 @@ * the maximum mapped by the Linux kernel during initialization ?? */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 01b33c77a8..41ab860850 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -86,7 +86,6 @@ /* environment is in FLASH */ /* Ethernet configuration part */ -#define CONFIG_SYS_DISCOVER_PHY 1 /* NAND configuration part */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index d356ff9594..d56d60306a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -61,7 +61,6 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 -#define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) @@ -127,12 +126,6 @@ * The reserved memory */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ /* @@ -198,43 +191,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ /* * TSEC @@ -255,7 +220,6 @@ #ifdef CONFIG_TSEC2 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define TSEC2_PHY_ADDR 0x1c #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC2_PHYIDX 0 @@ -263,22 +227,6 @@ #endif /* - * SATA - */ -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* * Environment */ @@ -300,15 +248,11 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration */ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - #define CONFIG_NETDEV "eth1" #define CONFIG_HOSTNAME "mpc837x_rdb" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index d8ffa2e28a..c3c68071f2 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -16,10 +16,6 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_PCI1 /* PCI controller 1 */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#undef CONFIG_PCI2 - #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #ifndef __ASSEMBLY__ @@ -34,7 +30,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR @@ -264,8 +259,6 @@ */ #if !CONFIG_IS_ENABLED(DM_I2C) #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -#else -#define CONFIG_SYS_SPD_BUS_NUM 0 #endif /* EEPROM */ @@ -319,10 +312,6 @@ #endif #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ -#if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - #if defined(CONFIG_TSEC_ENET) #define CONFIG_TSEC1 1 @@ -367,7 +356,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ce63e640d5..d263999b5a 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -20,7 +20,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif #ifdef CONFIG_SPIFLASH @@ -32,7 +31,6 @@ #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif #endif @@ -43,7 +41,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #else #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) @@ -51,16 +48,11 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 -#else -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif #endif #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ -#define CONFIG_RAMBOOT_NAND #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif @@ -71,9 +63,6 @@ /* High Level Configuration Options */ #if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - /* * PCI Windows * Memory space is mapped 1-1, but I/O space must start from 0. @@ -105,8 +94,6 @@ #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif #define CONFIG_HWCONFIG @@ -115,12 +102,7 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ - -#define CONFIG_ENABLE_36BIT_PHYS - /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -360,13 +342,6 @@ extern unsigned long get_sdram_size(void); FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ - defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ @@ -472,46 +447,16 @@ extern unsigned long get_sdram_size(void); #endif /* CONFIG_TSEC_ENET */ -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif /* #ifdef CONFIG_FSL_SATA */ - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #endif -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#else -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ -#endif #endif #endif @@ -532,7 +477,6 @@ extern unsigned long get_sdram_size(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 9cce6cf68d..64f4c244fa 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -25,17 +25,12 @@ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ @@ -43,11 +38,6 @@ #define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) - #define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - #ifndef __ASSEMBLY__ #include <linux/stringify.h> #endif @@ -58,8 +48,6 @@ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -91,7 +79,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -141,10 +128,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 @@ -332,24 +315,6 @@ #define CONFIG_SYS_DPAA_PME #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 @@ -373,16 +338,6 @@ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT @@ -398,7 +353,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index f1417b1bfc..bc8aa3ce05 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -9,9 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN #define CONFIG_SYS_SRIO diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 8a0c7039f6..6375c65d48 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -9,10 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 - -#define CONFIG_LBA48 - #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index fc2a07b974..fb73f0b953 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -9,8 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 8114373655..e42e6d5653 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -9,10 +9,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - /* * NS16550 Configuration */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index b70829c09d..8926c26b0b 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -9,10 +9,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - /* * NS16550 Configuration */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 618b8ed845..3df6ec6246 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -14,10 +14,7 @@ #include <linux/stringify.h> /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL @@ -28,9 +25,6 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH @@ -39,9 +33,6 @@ #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -50,9 +41,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -136,11 +124,9 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SDRAM_SIZE 2048 #endif @@ -300,10 +286,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -364,9 +346,6 @@ * General PCIe * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ @@ -392,18 +371,11 @@ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif /* * SDHC @@ -485,7 +457,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 3f4e59fa8a..8503fd1087 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -32,9 +32,6 @@ #endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH @@ -43,9 +40,6 @@ #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -54,34 +48,17 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_NXP_ESBC -#define CONFIG_RAMBOOT_NAND -#define CONFIG_BOOTSCRIPT_COPY_RAM -#endif -#endif /* * These can be toggled for performance analysis, otherwise use default. @@ -92,8 +69,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ @@ -117,7 +92,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -284,10 +258,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -386,30 +356,11 @@ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -/* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR @@ -496,7 +447,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Dynamic MTD Partition support with mtdparts diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index b4a91eacb9..e981f621c3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -15,17 +15,13 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #if defined(CONFIG_ARCH_T2080) -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL @@ -36,9 +32,6 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH @@ -47,9 +40,6 @@ #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -58,9 +48,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -106,7 +93,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -280,10 +266,6 @@ #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -380,10 +362,6 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull @@ -407,10 +385,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_BMAN_NUM_PORTALS 18 @@ -459,25 +433,8 @@ #endif /* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* * USB */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB -#endif /* * SDHC @@ -507,7 +464,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 84e5d5df38..48cdc75a08 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -14,13 +14,9 @@ #include <linux/stringify.h> #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_FSL_SATA_V2 /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL @@ -31,9 +27,6 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SPIFLASH @@ -42,9 +35,6 @@ #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #ifdef CONFIG_SDCARD @@ -53,9 +43,6 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -101,7 +88,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -239,10 +225,6 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -333,10 +315,6 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull @@ -360,10 +338,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_BMAN_NUM_PORTALS 18 @@ -415,25 +389,8 @@ #endif /* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* * USB */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB -#endif /* * SDHC @@ -461,7 +418,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2ab1b647a8..c31b0b6841 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -12,9 +12,6 @@ #include <linux/stringify.h> -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE4 - #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL @@ -31,26 +28,18 @@ #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif #endif #endif /* CONFIG_RAMBOOT_PBL */ /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ /* * These can be toggled for performance analysis, otherwise use default. @@ -60,8 +49,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ @@ -149,22 +136,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * Environment */ @@ -181,7 +152,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration @@ -196,7 +166,6 @@ /* * DDR Setup */ -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS3 0x56 @@ -350,10 +319,6 @@ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* I2C */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ @@ -433,23 +398,9 @@ #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR #endif -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - /* * USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 13d11084cd..4b59759f81 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -19,16 +19,12 @@ #include <configs/ti_am335x_common.h> #include <linux/sizes.h> -#define CONFIG_SYS_BOOTM_LEN SZ_16M - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ @@ -172,14 +168,6 @@ /* PMIC support */ #define CONFIG_POWER_TPS65910 -/* SPL */ -#ifndef CONFIG_NOR_BOOT -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - -/* USB gadget RNDIS */ -#endif - #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index b92703205c..7fa1847c1f 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -12,8 +12,6 @@ #include <configs/ti_am335x_common.h> -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -29,7 +27,7 @@ "ramdisk_addr_r=0x88080000\0" \ #define BOOT_TARGET_DEVICES(func) \ - func(UBIFS, ubifs, 0) + func(UBIFS, ubifs, 0, UBI, rootfs) #define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" @@ -52,9 +50,7 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV \ GUARDIAN_DEFAULT_PROD_ENV \ - "autoload=no\0" \ "backlight_brightness=50\0" \ - "bootubivol=rootfs\0" \ "distro_bootcmd=" \ "setenv rootflags \"bulk_read,chk_data_crc\"; " \ "setenv ethact usb_ether; " \ @@ -94,9 +90,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_LE - #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index 2cf77a67c0..3952783ee1 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -20,7 +20,6 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "bootdir=/boot\0" \ @@ -55,8 +54,6 @@ "bootz ${loadaddr} - ${fdtaddr};" \ "fi;" \ "fi;\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=1\0" \ "nandrootfstype=ubifs rootwait\0" \ "nandload=ubi part UBI; " \ @@ -89,7 +86,6 @@ "setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \ "if test ${fdtfile} = ''; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 5964ccc74c..08bae9b886 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -16,8 +16,6 @@ /* settings we don;t want on this board */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index a57d551bcf..7df5f14055 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -10,14 +10,10 @@ #include <configs/ti_am335x_common.h> -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x80000000\0" \ "pxefile_addr_r=0x80100000\0" \ @@ -39,8 +35,6 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV -#endif - /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ @@ -54,9 +48,6 @@ /* SPL */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* Network. */ #endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index b896f962f0..e6c9039d16 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -49,8 +49,6 @@ "bootenv=uEnv.txt\0" \ "cmdline=\0" \ "optargs=\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index e0138fe1db..87d3a27099 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -48,12 +48,6 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -/* SPL USB Support */ - -#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 -#endif - #ifndef CONFIG_SPL_BUILD /* USB Device Firmware Update support */ #define DFUARGS \ @@ -152,8 +146,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 26 #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c36311e06d..d8b0531673 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -16,8 +16,6 @@ #define CONFIG_IODELAY_RECALIBRATION -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 6da11b86c4..140940730d 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -106,6 +106,4 @@ /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 - #endif /* __CONFIG_AM642_EVM_H */ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index db35af98d9..0345160787 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -17,8 +17,6 @@ /* DDR Configuration */ #define CONFIG_SYS_SDRAM_BASE1 0x880000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define PARTS_DEFAULT \ /* Linux partitions */ \ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" @@ -65,14 +63,6 @@ "0 /lib/firmware/am65x-mcu-r5f0_0-fw " \ "1 /lib/firmware/am65x-mcu-r5f0_1-fw " -#ifdef CONFIG_TARGET_AM654_A53_EVM -#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD -#endif - #define EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \ "init_ubi=run args_all args_ubi; sf probe; " \ "ubi part ospi.rootfs; ubifsmount ubi:rootfs;\0" \ @@ -104,14 +94,11 @@ DEFAULT_FIT_TI_ARGS \ EXTRA_ENV_AM65X_BOARD_SETTINGS \ EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ - EXTRA_ENV_AM65X_BOARD_SETTINGS_MTD \ EXTRA_ENV_AM65X_BOARD_SETTINGS_UBI \ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ BOOTENV -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 4a3e51d19e..c9f876f5da 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -63,8 +63,6 @@ /* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 19e6a1e04e..6a4092a83e 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -19,12 +19,6 @@ #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" -/* PCI host support */ -#undef CONFIG_PCI_SCAN_SHOW - -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - /* * Custom Distro Boot configuration: * 1. 8bit SD port (MMC1) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 2864405147..4922b06330 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -25,20 +25,11 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_LBA48 -#endif - /* Network */ #define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ /* USB Configs */ /* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Client */ @@ -56,7 +47,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -66,9 +56,6 @@ #include <config_distro_bootcmd.h> #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START "" -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 104c4135e2..84bd88f835 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -23,9 +23,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ "uboot_blk=0\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index de4f4407ab..8997c6a0ea 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -110,9 +110,6 @@ "splashpos=m,m\0" \ "console=" CONSOLE_DEV "\0" \ "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ - "mtdids=nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor)\0" \ "mk_fitfile_path=setenv fit_file /${sysnum}/system.itb\0" \ "mk_rescue_fitfile_path=setenv rescue_fit_file /${rescue_sysnum}/system.itb\0" \ "mk_uboot_path=setenv uboot /${sysnum}/u-boot.imx\0" \ @@ -420,7 +417,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 5ebba0cda2..7a244769e3 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -14,13 +14,9 @@ #include "exynos5250-common.h" #include <configs/exynos5-common.h> -/* MMC SPL */ -#define CONFIG_EXYNOS_SPL - /* Miscellaneous configurable options */ -#define CONFIG_S5P_PA_SYSRAM 0x02020000 -#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM +#define CONFIG_SMP_PEN_ADDR 0x02020000 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 9bf6968e8a..a8265e961a 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -65,8 +65,6 @@ #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 #define CONFIG_SYS_CORE_SRAM 0x80000000 -#define CONFIG_SYS_UNIFY_CACHE - /* * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud @@ -133,7 +131,6 @@ * it needs non-blocking CFI routines. */ -#define CONFIG_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 2c4f229d34..ef9335c523 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -53,12 +53,6 @@ #endif /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 563fff531d..12726c10bd 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -51,16 +51,6 @@ #define CONFIG_DM9000_NO_SROM /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ -#ifdef CONFIG_AT91SAM9G10EK -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" -#else -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" -#endif -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index c100a411b2..9497f05503 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -173,12 +173,6 @@ #endif /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index abcddc3cc9..4d492988eb 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -36,21 +36,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" -/* USB host */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - /* SPL */ #define CONFIG_SYS_MONITOR_LEN (512 << 10) diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index e3350282bc..e418edddfb 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -22,8 +22,6 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -/* Let board_init_f handle the framebuffer allocation */ -#undef CONFIG_FB_ADDR /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 6857f2e3c4..0e7665843d 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -38,19 +38,6 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#ifndef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#endif -#endif - /* SPL */ #define CONFIG_SYS_MONITOR_LEN (512 << 10) diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 754e909619..daa5cdf5b2 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -73,7 +73,6 @@ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Increase max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Support autoboot from RAM (kernel image is loaded via debug port) */ #define KERNEL_IMAGE_ADDR "0x2000000 " diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 7e25846e40..f2357b5785 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -23,8 +23,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_512M -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -39,8 +37,6 @@ /* * USB 1.1 configuration */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 /* * Environment settings diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 7b43741fde..266b2ae04b 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -24,13 +24,10 @@ #define V_SCLK (V_OSCK) /* FIT support */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "${mtdparts} " \ @@ -52,7 +49,6 @@ #define NANDARGS "" #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "boot_fdt=try\0" \ @@ -183,7 +179,6 @@ "findfdt=setenv fdtfile am335x-baltos.dtb\0" \ NANDARGS /*DFUARGS*/ -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h index 3a02806878..d0c46a2c82 100644 --- a/include/configs/bcm947622.h +++ b/include/configs/bcm947622.h @@ -6,8 +6,6 @@ #ifndef __BCM947622_H #define __BCM947622_H -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define COUNTER_FREQUENCY 50000000 diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 97e1a88f27..795de46938 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -32,7 +32,6 @@ * Increase max uncompressed/gunzip size, keeping size same as EMMC linux * partition. */ -#define CONFIG_SYS_BOOTM_LEN 0x01800000 /* Access eMMC Boot_1 and Boot_2 partitions */ diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index ed78b73212..134a3ec289 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -91,7 +91,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * Large kernel image bootm configuration. */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* * NS16550 configuration. diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 2bcd0e1a98..829e816ad6 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "pxefile_addr_r=0x2000000\0" \ "scriptaddr=0x3000000\0" \ "kernel_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 2069d51d2f..925a68787c 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -67,7 +67,6 @@ /* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ BK4_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "blimg_file=u-boot.vyb\0" \ @@ -81,7 +80,6 @@ "nfs_root=/path/to/nfs/root\0" \ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "ipaddr=192.168.0.60\0" \ "serverip=192.168.0.1\0" \ "bootargs_base=setenv bootargs rw " \ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 412471a4aa..55c1d439d5 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index 8caddf3846..f046b7e662 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 892a3e2c41..7e488072ed 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index af1c3673fb..f704fe26ca 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -14,13 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 6cb09492aa..9aaa694cad 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 92ab0ba7a2..34e542544c 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 8a22dc1a3c..0319124a0e 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -14,15 +14,6 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#if defined(CONFIG_USB_OHCI_HCD) -#define CONFIG_USB_OHCI_NEW -#endif /* CONFIG_USB_OHCI_HCD */ - /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) diff --git a/include/configs/boston.h b/include/configs/boston.h index 3bf85b6c28..8b04492753 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -9,7 +9,6 @@ /* * General board configuration */ -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* * CPU diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h index 493114836c..0c8d352be9 100644 --- a/include/configs/broadcom_bcm963158.h +++ b/include/configs/broadcom_bcm963158.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } /* Memory usage */ -#define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) /* * 63158 diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 12a4048a51..789e6a4c9d 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -16,7 +16,6 @@ #include <linux/stringify.h> /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ @@ -39,8 +38,6 @@ #ifdef CONFIG_MTD_RAW_NAND #define NANDTGTS \ -"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ -"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \ " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ "nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \ @@ -99,11 +96,9 @@ MMCSPI_TGTS \ #define LOAD_OFFSET(x) 0x8##x -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "verify=no\0" \ -"autoload=0\0" \ "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ "cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \ "dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \ @@ -123,7 +118,6 @@ NANDTGTS \ "b_default=run b_deftgts; for target in ${b_tgts};"\ " do echo \"### booting ${target} ###\"; run b_${target};" \ " if test ${b_break} = 1; then; exit; fi; done\0" -#endif /* !CONFIG_SPL_BUILD*/ #ifdef CONFIG_MTD_RAW_NAND /* diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 7b110f05ca..adaba410ce 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -29,7 +29,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "cfgaddr=0x106F0000\0" \ "scraddr=0x10700000\0" \ "loadaddr=0x10800000\0" \ @@ -86,7 +85,6 @@ BUR_COMMON_ENV \ #define CONFIG_FEC_FIXED_SPEED _1000BASET /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* SPL */ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index f1e6dbf613..f9908352b0 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -18,18 +18,14 @@ /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "cfgscr=mw ${dtbaddr} 0;" \ " sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \ @@ -56,7 +52,6 @@ BUR_COMMON_ENV \ " fdt boardsetup\0" \ "startsys=run vxargs && mw 0x80001100 0 && run vxfdt &&" \ " bootm ${loadaddr} - ${dtbaddr}\0" -#endif /* !CONFIG_SPL_BUILD*/ /* SPI Flash */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index d34d69778f..4d91a776ba 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -23,12 +23,9 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD - /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ -"autoload=0\0" \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootaddr=0x80001100\0" \ "bootdev=cpsw(0,0)\0" \ @@ -51,7 +48,6 @@ BUR_COMMON_ENV \ "b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}\0" \ "b_default=run b_deftgts; for target in ${b_tgts};"\ " do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" -#endif /* !CONFIG_SPL_BUILD*/ /* Environment */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 0bbfe0c217..6b1e82ad3b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -19,25 +19,18 @@ #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - #endif /* CONFIG_SPL_BUILD */ -#define CONFIG_FACTORYSET - /* ENET1 connects to base board and MUX with ESAI */ #define CONFIG_FEC_ENET_DEV 1 #define CONFIG_FEC_MXC_PHYADDR 0x0 -/* I2C Configuration */ -#ifndef CONFIG_SPL_BUILD /* EEPROM */ #define EEPROM_I2C_BUS 0 /* I2C0 */ #define EEPROM_I2C_ADDR 0x50 /* PCA9552 */ #define PCA9552_1_I2C_BUS 1 /* I2C1 */ #define PCA9552_1_I2C_ADDR 0x60 -#endif /* !CONFIG_SPL_BUILD */ /* AHAB */ #ifdef CONFIG_AHAB_BOOT diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index a8ff0a1317..6ac8487851 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -17,8 +17,6 @@ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - #endif /* Flat Device Tree Definitions */ diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 8bad0f9ac4..965eba58b3 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -13,8 +13,6 @@ #define V_SCLK (V_OSCK) #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} ${optargs} " \ "${mtdparts} " \ "root=${nandroot} " \ @@ -107,8 +105,6 @@ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* SPL */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE /* NAND: device related configs */ /* NAND: driver related configs */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 01f6364905..192da015e1 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -28,6 +28,5 @@ #define DM9000_DATA (CONFIG_DM9000_BASE + 2) /* Miscellaneous configuration options */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) #endif /* __CONFIG_CI20_H__ */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index b19b3ef541..1043eb7506 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -26,13 +26,9 @@ #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } -#undef CONFIG_SYS_AUTOLOAD #undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_SYS_AUTOLOAD "no" - #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=off\0" \ "script=boot.scr\0" \ "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ @@ -102,10 +98,8 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* SPL */ #include "imx7_spl.h" diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 8497fe28ef..9c9e9506dc 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -18,8 +18,6 @@ * U-Boot into it. */ -#define CONFIG_ENV_MIN_ENTRIES 128 - /* Environment in MMC */ /* * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC @@ -30,11 +28,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ @@ -47,8 +40,6 @@ #include "mv-common.h" /* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) #else @@ -125,6 +116,4 @@ "console=ttyS0,115200\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif /* _CONFIG_CLEARFOG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index cb4cd925d9..cbba726440 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -30,7 +30,6 @@ /* Environment */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -44,7 +43,6 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ "panel=HDMI\0" \ - "autoload=no\0" \ "uImage=uImage-cm-fx6\0" \ "zImage=zImage-cm-fx6\0" \ "kernel=uImage-cm-fx6\0" \ @@ -55,8 +53,6 @@ "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ "doboot=bootm ${kernel_addr_r}\0" \ "doloadfdt=false\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setboottypez=setenv kernel ${zImage};" \ "setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \ "setenv doloadfdt true;\0" \ @@ -130,16 +126,11 @@ func(SATA, sata, 0) #include <config_distro_bootcmd.h> -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* NAND */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* APBH DMA is required for NAND support */ -#endif /* Ethernet */ #define CONFIG_FEC_MXC_PHYADDR 0 @@ -147,13 +138,6 @@ /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ - -/* SATA */ -#define CONFIG_LBA48 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR /* Boot */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index b3ccc3cac3..4baf7f7e24 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -19,7 +19,6 @@ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#ifndef CONFIG_SPL_BUILD #define MMCARGS \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ @@ -32,8 +31,6 @@ "bootm ${loadaddr}\0" #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:rootfs rw\0" \ "nandrootfstype=ubifs\0" \ "nandargs=setenv bootargs console=${console} " \ @@ -55,9 +52,6 @@ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ MMCARGS \ NANDARGS -#endif /* CONFIG_SPL_BUILD */ - -#define CONFIG_SYS_AUTOLOAD "no" /* Serial console configuration */ @@ -95,7 +89,6 @@ /* EEPROM */ -#ifndef CONFIG_SPL_BUILD /* * Enable PCA9555 at I2C0-0x26. * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. @@ -103,6 +96,5 @@ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } -#endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_CM_T335_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index ec1355b8a3..07c5cb8ded 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -56,7 +56,6 @@ "loadaddr=0x80200000\0" \ "fdtaddr=0x81200000\0" \ "bootm_size=0x8000000\0" \ - "autoload=no\0" \ "console=ttyO0,115200n8\0" \ "fdtfile=am437x-sb-som-t43.dtb\0" \ "kernel=zImage-cm-t43\0" \ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index c926e6ac8c..dd7b6c0873 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -85,15 +85,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text); -#ifdef CONFIG_MCFFEC -# define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - /* *----------------------------------------------------------------------------- * Define user parameters that have to be customized most likely @@ -157,7 +148,6 @@ enter a valid image address in flash */ * --- */ -#define CONFIG_SYS_DISCOVER_PHY #define CONFIG_SYS_ENET_BD_BASE 0x780000 /*----------------------------------------------------------------------- diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 0459cb0286..04cde9530a 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -65,7 +65,6 @@ #define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" #define MODULE_EXTRA_ENV_SETTINGS \ "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBI_BOOTCMD #else #define MODULE_EXTRA_ENV_SETTINGS "" @@ -91,7 +90,6 @@ UBI_BOOTCMD \ UBOOT_UPDATE \ "boot_script_dhcp=boot.scr\0" \ - "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=user_debug=30\0" \ "fdt_board=eval-v3\0" \ @@ -122,11 +120,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* environment organization */ -#if defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SIZE) -#endif - #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -135,11 +128,9 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index fb7de896b7..5d6449c7f7 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -96,8 +96,6 @@ /* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index d7d5c2ddee..3c220e0d6e 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -27,8 +27,6 @@ /* USB Configs */ /* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Client */ @@ -46,7 +44,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ @@ -55,9 +52,6 @@ #include <config_distro_bootcmd.h> #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START "" -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 180142a648..9543e0233e 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -102,7 +102,6 @@ #if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) #define MODULE_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBI_BOOTCMD #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define MODULE_EXTRA_ENV_SETTINGS \ @@ -131,7 +130,6 @@ UBOOT_UPDATE \ "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ - "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=\0" \ "fdt_board=eval-v3\0" \ @@ -166,11 +164,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* environment organization */ -#if defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SIZE) -#endif - #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -179,11 +172,9 @@ #endif /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 1e6561dc28..73d1844421 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -25,7 +25,6 @@ /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ #define BOARD_EXTRA_ENV_SETTINGS \ "boot_script_dhcp=boot.scr\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBOOT_UPDATE #include "tegra-common-post.h" diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 32e2aabc67..268afbb7fa 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -68,7 +68,6 @@ "fdt_board=eval-v3\0" \ "fdt_fixup=;\0" \ "kernel_image=zImage\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setsdupdate=mmc rescan && set interface mmc && " \ "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ @@ -91,14 +90,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* Environment organization */ -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_RANGE (4 * 64 * 2048) -#endif - /* USB Host Support */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* USB DFU */ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index d1bea54b20..5da2778b67 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -17,11 +17,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* * Environment Configuration */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 9291b81ac2..f20f4e35e9 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -15,17 +15,8 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL -#ifdef CONFIG_NXP_ESBC #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_RAMBOOT_NAND -#endif -#define CONFIG_BOOTSCRIPT_COPY_RAM -#else -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -37,21 +28,12 @@ #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif /* * These can be toggled for performance analysis, otherwise use default. @@ -62,8 +44,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -94,7 +74,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -139,10 +118,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 @@ -333,22 +308,6 @@ #define CONFIG_SYS_DPAA_PME #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d @@ -371,16 +330,6 @@ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT @@ -396,7 +345,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h index 07769c9e0e..25bcc2a684 100644 --- a/include/configs/crs3xx-98dx3236.h +++ b/include/configs/crs3xx-98dx3236.h @@ -10,8 +10,6 @@ * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */ - /* Environment in SPI NOR flash */ /* Keep device tree and initrd in lower memory so the kernel can access them */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 71ebca587d..3db97205da 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -101,9 +101,7 @@ /* * I2C Configuration */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 -#endif /* * Flash & Environment @@ -172,10 +170,6 @@ "console=ttyS2,115200n8\0" \ "hwconfig=dsp:wake=yes" -/* USB Configs */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - #ifdef CONFIG_SPL_BUILD /* defines for SPL */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index d502e98dea..36052fe7d8 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -50,10 +50,8 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 7357f9800f..ef9c457e10 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -20,7 +20,6 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 3c442018ab..b9d03d253d 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -14,11 +14,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 6b2edbb1e0..bba2b607aa 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -17,11 +17,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 808debc6f5..7b305955c9 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -16,20 +16,11 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* SATA support */ -#define CONFIG_LBA48 - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ /* diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 15160db276..328e4958f8 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -55,7 +55,6 @@ /* * USB */ -#define CONFIG_USB_OHCI_LPC32XX #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d /* @@ -71,7 +70,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "ethaddr=00:01:90:00:C0:81\0" \ "dtbaddr=0x81000000\0" \ "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index b495826301..79424647f6 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -26,25 +26,17 @@ /* Miscellaneous configurable options */ -/* Bootcounter */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* SATA Configs */ -#define CONFIG_LBA48 - /* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) @@ -56,7 +48,6 @@ #endif #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ @@ -81,7 +72,6 @@ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 0590704000..015bc78648 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -40,9 +40,7 @@ "stdout=serial\0" \ "stderr=serial\0" \ "loadaddr=0x800000\0" \ - "autoload=no\0" \ "console=ttyS0,115200\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "optargs=\0" \ "bootenv=uEnv.txt\0" \ "importbootenv=echo Importing environment ...; " \ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 381a189149..33ae7d654b 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -24,8 +24,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "initrd=/boot/uInitrd\0" \ "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0" diff --git a/include/configs/draco.h b/include/configs/draco.h index d305608101..4869008da4 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -27,13 +27,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=draco\0" \ @@ -45,8 +38,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index ed46f26628..c37b4c635b 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -18,14 +18,8 @@ /* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */ #define PHYS_SDRAM_1_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* UART */ - -/* Fixup - in init code we switch from device to host mode, - * it has to be done after each HCD reset */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +/* Environment */ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 1) \ @@ -34,43 +28,6 @@ #include <config_distro_bootcmd.h> -/* Does what recovery does */ -#define REFLASH(file, part) \ -"part start mmc 0 "#part" start && "\ -"part size mmc 0 "#part" size && "\ -"tftp $loadaddr "#file" && " \ -"mmc write $loadaddr $start $size && " - -#define CONFIG_ENV_REFLASH \ -"mmc dev 0 && "\ -"usb start && "\ -"dhcp && "\ -"tftp $loadaddr dragonboard/rescue/gpt_both0.bin && "\ -"mmc write $loadaddr 0 43 && " \ -"mmc rescan && "\ -REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)\ -REFLASH(dragonboard/rescue/sbl1.mbn, 2)\ -REFLASH(dragonboard/rescue/rpm.mbn, 3)\ -REFLASH(dragonboard/rescue/tz.mbn, 4)\ -REFLASH(dragonboard/rescue/hyp.mbn, 5)\ -REFLASH(dragonboard/rescue/sec.dat, 6)\ -REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)\ -REFLASH(dragonboard/u-boot.img, 8)\ -"usb stop &&"\ -"echo Reflash completed" - -/* Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "reflash="CONFIG_ENV_REFLASH"\0"\ - "loadaddr=0x81000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "linux_image=Image\0" \ - "kernel_addr_r=0x81000000\0"\ - "fdtfile=qcom/apq8016-sbc.dtb\0" \ - "fdt_addr_r=0x83000000\0"\ - "ramdisk_addr_r=0x84000000\0"\ - "scriptaddr=0x90000000\0"\ - "pxefile_addr_r=0x90100000\0"\ - BOOTENV +#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV #endif diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index e3940dc321..1fa5d05e7b 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -20,11 +20,8 @@ #define PHYS_SDRAM_2_SIZE 0x5ea4ffff #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#ifndef CONFIG_SPL_BUILD #include <config_distro_bootcmd.h> -#endif #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 07e2b8781f..fbd83d629c 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -30,9 +30,4 @@ #define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_PHY_BASE_ADR 0 -/* - * SATA Driver configuration - */ -#define CONFIG_LBA48 - #endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 7fa1a4ebf0..f8273a92f1 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -19,11 +19,6 @@ /* I2C */ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/durian.h b/include/configs/durian.h index c224511832..8f0e8be433 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -13,11 +13,7 @@ #define PHYS_SDRAM_1_SIZE 0x7B000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* PCI CONFIG */ -#define CONFIG_PCI_SCAN_SHOW - /* BOOT */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #define CONFIG_EXTRA_ENV_SETTINGS \ "load_kernel=ext4load scsi 0:1 0x90100000 uImage-2004\0" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 6157157508..6e444c4789 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -47,7 +47,6 @@ *----------------------------------------------------------------------*/ #ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY #define CONFIG_OVERWRITE_ETHADDR_ONCE #endif diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 1d6e6bcc43..8625701682 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -101,8 +101,6 @@ #define __io /* Data, registers and alternate blocks are at the same offset */ /* Each 8-bit ATA register is aligned to a 4-bytes address */ -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 /* A single bus, a single device */ /* ATA registers base is at SATA controller base */ /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 00996f5cb7..7526d3b0f5 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -18,7 +18,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h index 660d1a0804..2f067a4424 100644 --- a/include/configs/espresso7420.h +++ b/include/configs/espresso7420.h @@ -10,8 +10,6 @@ #include <configs/exynos7420-common.h> -#define CONFIG_ESPRESSO7420 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 654faedf33..3acc62d9e1 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -75,14 +75,8 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - /* nedded by compliance test in read mode */ -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - - #undef COMMON_ENV_DFU_ARGS #define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ "setenv bootargs ${bootargs};" \ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 8e7bfadf64..88a702f1af 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -32,7 +32,6 @@ /* 512kB on-chip NOR flash */ # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ # define CONFIG_SYS_MAX_FLASH_SECT 32 -# define CONFIG_EFLASH_PROTSECTORS 1 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -60,17 +59,6 @@ #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* RTC */ #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) #define CONFIG_SYS_I2C_RTC_ADDR 0x51 @@ -99,11 +87,6 @@ #define I2C_DELAY udelay(100) #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) -/* DHCP/BOOTP options */ -#ifdef CONFIG_CMD_DHCP -#define CONFIG_SYS_AUTOLOAD "n" -#endif - /* File systems */ /* Boot command */ diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index 492b7b4df1..b7e850370b 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -15,7 +15,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index cbcef261f4..246aa9b7ab 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -8,10 +8,6 @@ #ifndef __EXYNOS_COMMON_H #define __EXYNOS_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ - #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> #include <linux/stringify.h> @@ -22,9 +18,6 @@ /* select serial console configuration */ -/* PWM */ -#define CONFIG_PWM - /* Miscellaneous configurable options */ #endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 4202c62612..054cb5309e 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_EXYNOS4_COMMON_H #define __CONFIG_EXYNOS4_COMMON_H -#define CONFIG_EXYNOS4 /* Exynos4 Family */ - #include "exynos-common.h" /* SD/MMC configuration */ @@ -25,8 +23,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - /* Common environment variables */ #define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 7ab821d08c..44f5cb1e83 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -8,15 +8,8 @@ #ifndef __CONFIG_EXYNOS5_COMMON_H #define __CONFIG_EXYNOS5_COMMON_H -#define CONFIG_EXYNOS5 /* Exynos5 Family */ - #include "exynos-common.h" -#define CONFIG_EXYNOS_SPL - -/* Enable ACE acceleration for SHA1 and SHA256 */ -#define CONFIG_EXYNOS_ACE_SHA - /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 @@ -31,9 +24,6 @@ /* select serial console configuration */ #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -/* Thermal Management Unit */ -#define CONFIG_EXYNOS_TMU - /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index bcbdfa7ae3..a94f5a15f0 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -15,17 +15,8 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#define CONFIG_EXYNOS5_DT - #define CONFIG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) #define CONFIG_SPI_BOOTING -/* Display */ -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - #endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 82cb8aff7b..8e2f135f93 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -9,15 +9,8 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H -#define CONFIG_EXYNOS5250 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - -#define CONFIG_USB_XHCI_EXYNOS - /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 5e1aba7692..7a9307ccc3 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -8,25 +8,16 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H -#define CONFIG_EXYNOS5420 - -#define CONFIG_EXYNOS5_DT - #define CONFIG_VAR_SIZE_SPL #define CONFIG_IRAM_TOP 0x02074000 #define CONFIG_PHY_IRAM_BASE 0x02020000 -/* Address for relocating helper code (Last 4 KB of IRAM) */ -#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) - /* * Low Power settings */ #define CONFIG_LOWPOWER_FLAG 0x02020028 #define CONFIG_LOWPOWER_ADDR 0x0202002C -#define CONFIG_USB_XHCI_EXYNOS - #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index e8aed56710..a8bef860c2 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -8,10 +8,6 @@ #ifndef __CONFIG_EXYNOS7420_COMMON_H #define __CONFIG_EXYNOS7420_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P - #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index 4a2e56b635..b05846d0b9 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -11,10 +11,6 @@ #ifndef __CONFIG_EXYNOS78x0_COMMON_H #define __CONFIG_EXYNOS78x0_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P - #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> @@ -26,7 +22,6 @@ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/galileo.h b/include/configs/galileo.h index c50ecf27e4..49f57dda58 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -21,9 +21,6 @@ "stdout=serial\0" \ "stderr=serial\0" -/* 10/100M Ethernet support */ -#define CONFIG_DW_ALTDESCRIPTOR - /* Environment configuration */ #endif /* __CONFIG_H */ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 252ab5e747..95ba20c686 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -29,10 +29,8 @@ #endif /* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #define CONFIG_USBD_HS /* Video */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 74a2eaa789..ad00769bde 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -17,13 +17,6 @@ #include "mx6_common.h" #include <linux/sizes.h> -/* SATA Configs */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - #ifdef CONFIG_CMD_NFS #define NETWORKBOOT \ "setnetworkboot=" \ @@ -116,7 +109,4 @@ #define CONFIG_IMX6_PWM_PER_CLK 66000000 -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 832441a7b7..66eed9e14f 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -33,8 +33,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" @@ -44,7 +42,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* SATA driver configuration */ -#define CONFIG_LBA48 - #endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/gru.h b/include/configs/gru.h index b1084bb21d..be2dc79968 100644 --- a/include/configs/gru.h +++ b/include/configs/gru.h @@ -13,7 +13,4 @@ #include <configs/rk3399_common.h> -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index d5655e4ada..4954c5ca08 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -26,7 +26,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/guruplug-server-plus.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 26d171daae..82076ff74f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -22,27 +22,12 @@ /* NAND */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#undef CONFIG_SYS_BOOTM_LEN -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR - #define CONFIG_LBA48 -#endif - -/* * PCI express */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX -#endif /* * PMIC @@ -55,7 +40,6 @@ /* Various command support */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS @@ -86,154 +70,4 @@ #define CONFIG_IPADDR 192.168.1.1 #define CONFIG_SERVERIP 192.168.1.146 -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "usb_pgood_delay=2000\0" \ - "console=ttymxc1\0" \ - "bootdevs=usb mmc sata flash\0" \ - "hwconfig=_UNKNOWN_\0" \ - "video=\0" \ - \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "disk=0\0" \ - "part=1\0" \ - \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x18000000\0" \ - "initrd_high=0xffffffff\0" \ - "fixfdt=" \ - "fdt addr ${fdt_addr}\0" \ - "bootdir=boot\0" \ - "loadfdt=" \ - "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ - "run fixfdt; " \ - "fi\0" \ - \ - "fs=ext4\0" \ - "script=6x_bootscript-ventana\0" \ - "loadscript=" \ - "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ - "source ${loadaddr}; " \ - "fi\0" \ - \ - "uimage=uImage\0" \ - "mmc_root=mmcblk0p1\0" \ - "mmc_boot=" \ - "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \ - "mmc dev ${disk} && mmc rescan && " \ - "setenv dtype mmc; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${mmc_root} rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - \ - "sata_boot=" \ - "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \ - "sata init && " \ - "setenv dtype sata; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - "usb_boot=" \ - "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \ - "usb start && usb dev ${disk} && " \ - "setenv dtype usb; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" - -#ifdef CONFIG_SPI_FLASH - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ - "image_uboot=ventana/u-boot_spi.imx\0" \ - \ - "spi_koffset=0x90000\0" \ - "spi_klen=0x200000\0" \ - \ - "spi_updateuboot=echo Updating uboot from " \ - "${serverip}:${image_uboot}...; " \ - "tftpboot ${loadaddr} ${image_uboot} && " \ - "sf probe && sf erase 0 80000 && " \ - "sf write ${loadaddr} 400 ${filesize}\0" \ - "spi_update=echo Updating OS from ${serverip}:${image_os} " \ - "to ${spi_koffset} ...; " \ - "tftp ${loadaddr} ${image_os} && " \ - "sf probe && " \ - "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ - \ - "flash_boot=" \ - "if sf probe && " \ - "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mtdblock3 " \ - "rootfstype=squashfs,jffs2 " \ - "${video} ${extra}; " \ - "bootm; " \ - "fi\0" -#else - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - \ - "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ - "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ - "tftp ${loadaddr} ${image_rootfs} && " \ - "nand erase.part rootfs && " \ - "nand write ${loadaddr} rootfs ${filesize}\0" \ - \ - "flash_boot=" \ - "setenv fsload 'ubifsload'; " \ - "ubi part rootfs; " \ - "if ubi check boot; then " \ - "ubifsmount ubi0:boot; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=squashfs,ubifs; " \ - "setenv bootdir; " \ - "elif ubi check rootfs; then " \ - "ubifsmount ubi0:rootfs; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=ubifs; " \ - "fi; " \ - "setenv dtype nand; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=${root} ${video} ${extra}; " \ - "if run loadfdt; then " \ - "ubifsumount; " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "ubifsumount; bootm; " \ - "fi; " \ - "fi\0" -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/helios4.h b/include/configs/helios4.h index 23eb0d4375..fc32487e1c 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -18,8 +18,6 @@ * U-Boot into it. */ -#define CONFIG_ENV_MIN_ENTRIES 128 - /* Environment in MMC */ /* * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC @@ -30,11 +28,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ @@ -47,8 +40,6 @@ #include "mv-common.h" /* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) #else @@ -126,6 +117,4 @@ "console=ttyS0,115200\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif /* _CONFIG_HELIOS4_H */ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index d8e7126936..bb6cc95726 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,14 +14,10 @@ #define CONFIG_PL011_CLOCK 150000000 -#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_64BIT_LBA - /* Environment data setup */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 33e9aa5ffb..5be6eb4e76 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -15,8 +15,6 @@ #define CONFIG_POWER_HI6553 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Physical Memory Map */ /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index caa6abb9d9..ad070439d0 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -9,8 +9,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Physical Memory Map */ /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 7785bab714..4af845ea9c 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -39,12 +37,6 @@ */ /* - * USB 1.1 configuration - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -/* * Environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 6dd69ca38b..0ce65e7755 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_BOOTM_LEN SZ_128M - /* * UART configuration */ @@ -38,12 +36,6 @@ */ /* - * USB 1.1 configuration - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -/* * Environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index aff948cfe7..05192218d2 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -20,8 +20,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/ib62x0.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index cb4cf9beb7..f2e3608d3a 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -13,8 +13,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/uImage\0" \ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 39a36779bc..a8bb2090ec 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -164,7 +164,6 @@ #ifdef CONFIG_TSEC2 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define TSEC2_PHY_ADDR 0x3 #define TSEC2_FLAGS TSEC_GIGABIT #define TSEC2_PHYIDX 0 @@ -182,7 +181,6 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) -#define CONFIG_HAS_FSL_DR_USB #define CONFIG_SYS_SCCR_USBDRCM 3 /* @@ -245,8 +243,6 @@ "${netmask}:${hostname}:${netdev}:off " \ "console=${console},${baudrate} ${othbootargs}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "\0" /* UBI Support */ diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 40c0f1fe36..17430f15d1 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -132,8 +132,6 @@ " +${filesize};cp.b ${fileaddr} " \ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 592c62ab8a..2913549c88 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -122,10 +122,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif /* Falcon Mode */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index c4eebb5aea..909453cd66 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -20,7 +20,6 @@ /* Environment in MMC */ #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x14000000\0" \ "fdt_addr_r=0x13000000\0" \ @@ -34,7 +33,6 @@ func(MMC, mmc, 2) #include <config_distro_bootcmd.h> -#endif /* UART */ #define CONFIG_MXC_UART_BASE UART3_BASE @@ -45,10 +43,8 @@ #define CONFIG_FEC_MXC_PHYADDR 1 /* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Falcon */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 785ac7c501..201684ba80 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -111,9 +111,7 @@ #endif #endif -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif /* __IMX6Q_ACC_H */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 2f00198e40..f0f800b840 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -12,7 +12,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -#undef CONFIG_SYS_AUTOLOAD #undef CONFIG_EXTRA_ENV_SETTINGS /* diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 7135a83e04..c69f2fa19f 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -11,7 +11,6 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) @@ -141,8 +140,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /*__IMX8MM_CL_IOT_GATE_H*/ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 282b295497..fb05958bdc 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN SZ_128M - #define CONFIG_SYS_MONITOR_LEN SZ_1M #ifdef CONFIG_SPL_BUILD @@ -38,8 +36,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#if !defined(CONFIG_SPL_BUILD) - #define CONFIG_EXTRA_ENV_SETTINGS \ "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ "bootlimit=3\0" \ @@ -105,5 +101,3 @@ "fi" #endif - -#endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index e4b2544410..5e9e3e800d 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -10,7 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) @@ -22,14 +21,12 @@ #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index dfe6966c46..6b7f3af53a 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -20,14 +20,10 @@ /* For RAW image gives a error info not panic */ #endif /* CONFIG_SPL_BUILD */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x44000000\0" \ @@ -51,7 +47,6 @@ /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -#define CONFIG_SYS_BOOTM_LEN SZ_256M /* USDHC */ #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 8a6cc69b5e..1301560450 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -28,7 +28,6 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -36,9 +35,6 @@ func(USB, usb, 1) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -87,7 +83,6 @@ /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M /* FEC */ #define CONFIG_FEC_MXC_PHYADDR 0 diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index f752978369..84c19824bd 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -14,8 +14,6 @@ #include <config_distro_bootcmd.h> #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 63f7da740e..a371c5b383 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 1396ae1422..ae7fcb1027 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,25 +10,16 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* For RAW image gives a error info not panic */ - -#endif - -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ /* see include/configs/ti_armv7_common.h */ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index ccf83128f2..c8604e0de5 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 8ef55aa6eb..c43c4da6fb 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -25,16 +25,12 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -83,7 +79,6 @@ /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M /* FEC */ #define CONFIG_FEC_MXC_PHYADDR 0 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 1ad90e5bdb..4b4731c303 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -10,16 +10,8 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN SZ_128M - #define CONFIG_SYS_MONITOR_LEN SZ_1M -#ifdef CONFIG_SPL_BUILD -/* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#endif - /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -38,8 +30,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#if !defined(CONFIG_SPL_BUILD) - #define CONFIG_EXTRA_ENV_SETTINGS \ "altbootcmd=run bootcmd ; reset\0" \ "bootlimit=3\0" \ @@ -91,5 +81,3 @@ #include <config_distro_bootcmd.h> #endif - -#endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 618010db9f..5581c0fac0 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) @@ -32,13 +30,11 @@ #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 1d4c057ccc..17e00f958b 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -12,8 +12,6 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index fce87b1657..9f4c1b161f 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -25,16 +25,12 @@ "kernel_comp_addr_r=0x40200000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -83,7 +79,6 @@ /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_4G -#define CONFIG_SYS_BOOTM_LEN SZ_256M /* FEC */ #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index a5d6adfaa4..ab74d5b26b 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD @@ -26,14 +24,12 @@ /* ENET Config */ /* ENET1 */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 182f45bb74..ea4305667f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) - #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #ifdef CONFIG_SPL_BUILD @@ -32,14 +30,12 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #endif -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index b59502e589..5f9d06e0f6 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -10,16 +10,12 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - #endif #ifdef CONFIG_AHAB_BOOT diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 88d38a1dcb..308f17fd59 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -16,8 +16,6 @@ #define USDHC2_BASE_ADDR 0x5B020000 #define USDHC3_BASE_ADDR 0x5B030000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* FUSE command */ /* Boot M4 */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 511f6c8d9b..f8ec16ebb1 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -16,8 +16,6 @@ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000 -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - #endif #ifdef CONFIG_AHAB_BOOT diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index f9080216f1..ebfc166b4d 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -9,7 +9,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (SZ_64M) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 296bcd4c7b..0f6150fc9c 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -15,14 +15,10 @@ /* SPL Loader Configuration */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* U-Boot general configuration */ #define EXTRA_ENV_IOT2050_BOARD_SETTINGS \ "usb_pgood_delay=900\0" -#ifndef CONFIG_SPL_BUILD - #if CONFIG_IS_ENABLED(CMD_USB) # define BOOT_TARGET_USB(func) \ func(USB, usb, 0) \ @@ -44,8 +40,6 @@ #include <config_distro_bootcmd.h> -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ BOOTENV \ diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index 0ebb1b526e..a2e50c3b8d 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -53,8 +53,6 @@ #define CONFIG_SYS_SDRAM_BASE DCCM_BASE #define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE -#define CONFIG_SYS_BOOTM_LEN SZ_128K - #define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index c0b52558d8..9f54f25999 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -28,8 +28,6 @@ #define CONFIG_SYS_UBOOT_BASE 0x50080000 #endif -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* HyperFlash related configuration */ /* U-Boot general configuration */ @@ -151,14 +149,6 @@ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_OSPI -#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD -#endif - #if CONFIG_IS_ENABLED(CMD_PXE) # define BOOT_TARGET_PXE(func) func(PXE, pxe, na) #else @@ -189,7 +179,6 @@ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS \ - EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ BOOTENV diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 8e3ea670d0..932d7d3c8c 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -27,8 +27,6 @@ #define CONFIG_SYS_UBOOT_BASE 0x50080000 #endif -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* U-Boot general configuration */ #define EXTRA_ENV_J721S2_BOARD_SETTINGS \ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ @@ -128,14 +126,6 @@ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_OSPI -#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD -#endif - /* Incorporate settings into the U-Boot environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -146,7 +136,6 @@ EXTRA_ENV_RPROC_SETTINGS \ EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS \ - EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \ EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY /* Now for the remaining common defines */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 4bca1a7830..1bfc89bf44 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -171,8 +171,6 @@ "init=/sbin/init-overlay.sh\0" \ "load_addr_r=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "" #endif /* CONFIG_KM_DEF_ENV */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index c8929814aa..9f76f48a5c 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -25,10 +25,6 @@ */ #define CONFIG_SYS_FLASH_BASE 0xF0000000 -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - /* Reserve 768 kB for Mon */ #define CONFIG_SYS_MONITOR_LEN (768 * 1024) @@ -81,10 +77,6 @@ * Environment */ -#ifndef CONFIG_SYS_RAMBOOT -/* Address and size of Redundant Environment Sector */ -#endif /* CFG_SYS_RAMBOOT */ - /* * Environment Configuration */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index a9a6a41f6b..6becd7cd31 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE /* Increase max size of compressed kernel */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ /****************************************************************************** * (PRAM usage) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index a485c3ac6d..eee71db37c 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -25,7 +25,6 @@ #include "keymile-common.h" /* Increase max size of compressed kernel */ -#define CONFIG_SYS_BOOTM_LEN (32 << 20) #include "asm/arch/config.h" diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7430185666..f837390135 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ @@ -174,7 +173,6 @@ {1, {I2C_NULL_HOP} }, \ } -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -189,8 +187,6 @@ #define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* * Environment */ @@ -253,7 +249,6 @@ "ethrotate=no\0" \ "" -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ #endif diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index e58a69501b..01482d5319 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -23,7 +23,6 @@ /* KM_KIRKWOOD */ #if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_HOSTNAME "km_kirkwood" -#define CONFIG_KM_DISABLE_PCIE /* KM_KIRKWOOD_PCI */ #elif defined(CONFIG_KM_KIRKWOOD_PCI) @@ -34,7 +33,6 @@ /* KM_KIRKWOOD_128M16 */ #elif defined(CONFIG_KM_KIRKWOOD_128M16) #define CONFIG_HOSTNAME "km_kirkwood_128m16" -#define CONFIG_KM_DISABLE_PCIE /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) @@ -44,7 +42,6 @@ /* KMCOGE5UN */ #elif defined(CONFIG_KM_COGE5UN) #define CONFIG_HOSTNAME "kmcoge5un" -#define CONFIG_KM_DISABLE_PCIE /* KM_SUSE2 */ #elif defined(CONFIG_KM_SUSE2) @@ -118,8 +115,4 @@ MVGBE_SET_MII_SPEED_TO_100) #endif -#ifdef CONFIG_KM_DISABLE_PCIE -#undef CONFIG_KIRKWOOD_PCIE_INIT -#endif - #endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 4de5736d8c..3f22ddc6dd 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -133,14 +133,11 @@ #define KM_I2C_DEBLOCK_SDA 21 /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ /* Environment in parallel NOR-Flash */ #define CONFIG_ENV_TOTAL_SIZE 0x040000 @@ -152,8 +149,6 @@ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - /* POST memory regions test */ #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS @@ -173,7 +168,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -415,7 +409,6 @@ int get_scl(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 8f4685c271..b9d20c9c8e 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -35,12 +35,6 @@ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -/* - * BFTIC3 on the local bus CS4 - */ -#define CONFIG_SYS_BFTIC3_BASE 0xB0000000 -#define CONFIG_SYS_BFTIC3_SIZE 256 - /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index b6e68f8f41..7aac5d3f5a 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -29,25 +29,19 @@ #define CONFIG_HOSTNAME "kontron-mx6ul" #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* Boot order for distro boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index c4be62c372..622ab59762 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -26,10 +26,8 @@ #define CONFIG_HOSTNAME "kontron-mx8mm" #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* GUID for capsule updatable firmware image */ @@ -37,7 +35,6 @@ EFI_GUID(0xd488e45a, 0x4929, 0x4b55, 0x8c, 0x14, \ 0x86, 0xce, 0xa2, 0xcd, 0x66, 0x29) -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ @@ -47,11 +44,6 @@ /* Do not try to probe USB net adapters for net boot */ #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START -#else -#define BOOTENV -#endif - -#define CONFIG_SYS_BOOTM_LEN SZ_64M #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index bf336b99d6..d77e4b4e10 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -7,8 +7,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) - #define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K) /* GUID for capsule updatable firmware image */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 5b25be5c92..1823a79398 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -21,13 +21,10 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ @@ -88,7 +85,6 @@ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h index 75fc03f147..fea7c835fd 100644 --- a/include/configs/kylin_rk3036.h +++ b/include/configs/kylin_rk3036.h @@ -9,10 +9,4 @@ #include <linux/sizes.h> #include <configs/rk3036_common.h> -#ifndef CONFIG_SPL_BUILD - -/* Store env in emmc */ - -#endif - #endif diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 0a988e2fad..9b70eed46f 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -22,18 +22,6 @@ #endif /* - * SATA Driver configuration - */ - -#ifdef CONFIG_SATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 -#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ - defined(CONFIG_NET2BIG_V2) -#endif -#endif /* CONFIG_SATA */ - -/* * Enable GPI0 support */ @@ -69,7 +57,6 @@ "stderr=serial\0" \ "bootfile=uImage\0" \ "loadaddr=0x800000\0" \ - "autoload=no\0" \ "netconsole=" \ "set stdin $stdin,nc; " \ "set stdout $stdout,nc; " \ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 3c03368b5c..a1fc056c30 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -98,10 +98,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 1d8d9485e7..87eb10db19 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -15,9 +15,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL -/* CSU */ -#define CONFIG_LAYERSCAPE_NS_ACCESS - /*SPI device */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 @@ -36,14 +33,12 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -62,8 +57,6 @@ "bootm $kernel_load" #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include <asm/arch/soc.h> #endif /* __LS1012A_COMMON_H */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index cb79d6362f..674bcbeb75 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -12,11 +12,9 @@ /* DDR */ #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) -#endif #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index a1d23b6463..a0ff3b8979 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -19,17 +19,11 @@ /* ENV */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index b5992366cf..b124ce5262 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -82,10 +82,6 @@ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ DSPI_CTAR_DT(0)) -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index c57b598d70..4f77acdaed 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -36,10 +36,6 @@ #define __PHY_ETH2_MASK 0xFB #define __PHY_ETH1_MASK 0xFD -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 6a0ccbf836..ec688741a0 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -97,18 +97,9 @@ #define TSEC2_PHYIDX 0 #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ - #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e17bdcad6d..517ade383b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -23,11 +23,6 @@ #endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE @@ -306,16 +301,7 @@ #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -347,6 +333,5 @@ */ #include <asm/fsl_secure_boot.h> -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 905c63d4dd..2fbd495e11 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* XHCI Support - enabled by default */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -81,14 +80,7 @@ #define FSL_QSPI_FLASH_NUM 2 /* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 @@ -170,6 +162,4 @@ /* Environment */ -#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ - #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index d85a776daa..1aa29e541e 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -171,16 +171,7 @@ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -333,6 +324,5 @@ */ #include <asm/fsl_secure_boot.h> -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 5b0b86b39b..b104524bec 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -57,8 +57,6 @@ "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \ "env exists secureboot && esbc_halt;" -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #define OCRAM_NONSECURE_SIZE 0x00010000 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 35363ccda1..2539115186 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -60,7 +60,6 @@ /* SATA */ -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 #ifndef SPL_NO_ENV #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -88,7 +87,6 @@ "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1028aqds_boot.scr\0" \ "boot_script_hdr=hdr_ls1028aqds_bs.out\0" \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 91223789b8..e7b2543b73 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -53,7 +53,6 @@ #define SCSI_VEND_ID 0x1b4b #define SCSI_DEV_ID 0x9170 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 /* Initial environment variables */ #ifndef SPL_NO_ENV @@ -83,7 +82,6 @@ "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x20\0" \ "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1028ardb_boot.scr\0" \ "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index fe9a8fd375..95cbcb036e 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -108,17 +108,6 @@ /* I2C */ -/* PCIe */ -#ifndef SPL_NO_PCIE -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif -#endif - /* DSPI */ /* FMan ucode */ @@ -137,13 +126,11 @@ #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_MISC -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -169,7 +156,6 @@ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "boot_os=y\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ "boot_scripts=ls1043ardb_boot.scr\0" \ "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ @@ -231,8 +217,6 @@ #endif #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include <asm/arch/soc.h> #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 75d655c50d..15c3ff53fe 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -8,12 +8,9 @@ #include "ls1043a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index edb4e64ee4..6c33847b27 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -8,14 +8,9 @@ #include "ls1043a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - #ifndef CONFIG_SPL -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 8e9103562e..2e48ea0f8a 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -76,15 +76,6 @@ /* I2C */ -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* SATA */ #ifndef SPL_NO_SATA #define CONFIG_SYS_SATA AHCI_BASE_ADDR @@ -104,14 +95,12 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(SCSI, scsi, 0) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#endif #if defined(CONFIG_TARGET_LS1046AFRWY) #define LS1046A_BOOT_SRC_AND_HDR\ @@ -202,8 +191,6 @@ #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include <asm/arch/soc.h> #endif /* __LS1046A_COMMON_H */ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index d56d0c0294..43717cdd4e 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -8,8 +8,6 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - #define CONFIG_SYS_UBOOT_BASE 0x40100000 /* @@ -80,13 +78,11 @@ */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#endif /* FMan */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 6271135db9..36c64db8f5 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -8,12 +8,9 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 4ad62b43f8..382d5c7646 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -9,12 +9,9 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 9a29bb6ca1..4b8462da7b 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -115,11 +115,6 @@ unsigned long long get_qixis_addr(void); /* Miscellaneous configurable options */ -/* SATA */ -#ifdef CONFIG_SCSI -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#endif - /* Physical Memory Map */ #define CONFIG_HWCONFIG @@ -158,6 +153,5 @@ unsigned long long get_qixis_addr(void); #endif /* ifdef CONFIG_NXP_ESBC */ #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif /* __LS1088_COMMON_H */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index e532c343f4..debb60d25c 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -16,7 +16,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* @@ -306,10 +305,6 @@ #define CONFIG_FSL_MEMAC -/* MMC */ -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) - #define COMMON_ENV \ "kernelheader_addr_r=0x80200000\0" \ "fdtheader_addr_r=0x80100000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index c69003018b..c0567c3fe5 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -15,13 +15,8 @@ #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ -#ifdef CONFIG_EMU -#define CONFIG_SYS_FSL_DDR_EMU -#else #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index f9eb829cda..3e86d1bff2 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -16,10 +16,6 @@ /* Link Definitions */ -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif - #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ #define CONFIG_VERY_BIG_RAM @@ -143,8 +139,6 @@ unsigned long long get_qixis_addr(void); #endif #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - #include <asm/arch/soc.h> #endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 9ce48a0960..9ba7258572 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -24,15 +24,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) @@ -248,14 +239,6 @@ #define FSL_QIXIS_BRDCFG9_QSPI 0x1 /* - * MMC - */ -#ifdef CONFIG_MMC -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) -#endif - -/* * RTC configuration */ #define RTC @@ -268,10 +251,6 @@ #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #ifdef CONFIG_NXP_ESBC @@ -415,7 +394,7 @@ "env exists secureboot && esbc_halt;" #endif -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) #define CONFIG_FSL_MEMAC #define SGMII_CARD_PORT1_PHY_ADDR 0x1C #define SGMII_CARD_PORT2_PHY_ADDR 0x1d diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index cdfc9fd82e..a504a0ea46 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -29,15 +29,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) @@ -247,10 +238,6 @@ #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 19fd702ab2..81c93375e2 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -94,9 +94,4 @@ #define CONFIG_PHY_BASE_ADR 7 #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_SATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 -#endif - #endif /* _CONFIG_LSXL_H */ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 56096682c0..b754373169 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -31,7 +31,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_SYS_MONITOR_LEN (936 * 1024) /* Miscellaneous configurable options */ @@ -90,32 +89,13 @@ /* Qixis */ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* SATA */ - -#ifdef CONFIG_SCSI -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 -#endif - /* USB */ -#ifdef CONFIG_USB_HOST -#ifndef CONFIG_TARGET_LX2162AQDS -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif -#endif #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - /* Initial environment variables */ #define XSPI_MC_INIT_CMD \ "sf probe 0:0 && " \ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index e7aec6bc59..585aab26bf 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -11,16 +11,6 @@ /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - /* MAC/PHY configuration */ /* EEPROM */ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 126d226ebc..d1ae403473 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -9,22 +9,10 @@ #include "lx2160a_common.h" /* USB */ -#undef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - /* EEPROM */ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index ed44f355da..b3348bc63b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -51,9 +51,6 @@ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC - -/* Environment is in NAND */ -#define CONFIG_ENV_RANGE (0x00080000) /* 512 KiB */ #endif /* @@ -83,15 +80,6 @@ #endif /* - * SATA - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* * LCD */ #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) @@ -124,8 +112,6 @@ "mmcpart=1\0" \ "rootpath=/srv/\0" \ "kernel_addr_r=0x72000000\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "netdev=eth0\0" \ "splashsource=mmc_fs\0" \ "splashfile=boot/usplash.bmp.gz\0" \ diff --git a/include/configs/malta.h b/include/configs/malta.h index 225ed7cd5c..c8b230ab21 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -13,9 +13,6 @@ #define CONFIG_MEMSIZE_IN_BYTES -#define CONFIG_PCI_GT64120 -#define CONFIG_PCI_MSC01 - #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 /* @@ -37,8 +34,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - /* * Serial driver */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 2c862e9ddc..02a2235187 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -109,7 +109,6 @@ "fi;" \ "fi;" \ "fi\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "bootdev=1\0" \ "bootpart=1\0" \ "netdev=eth0\0" \ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 0ccfe7db5a..c6ce883747 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -24,7 +24,6 @@ /* Environment configs */ /* USB configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 51dd4d706e..40803ee9da 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -30,7 +30,6 @@ #endif #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index af6c728790..73f8492228 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -11,8 +11,6 @@ /* Microblaze is microblaze_0 */ #define XILINX_FSL_NUMBER 3 -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - /* uart */ /* The following table includes the supported baudrates */ # define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 236db537db..4c7cfac8af 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -11,8 +11,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index db4d68d750..049d9a1b55 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -14,8 +14,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* SPL */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index 6c681a3c30..78d79b7780 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -11,7 +11,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Uboot definition */ diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 06367221eb..0cd8b08552 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -13,8 +13,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 4dcfa39350..3680c0fe44 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -14,8 +14,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 87e2251777..22d11d0147 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -13,8 +13,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index 665a4e44f3..c93d70ddf1 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -18,8 +18,6 @@ #define CONFIG_SYS_NS16550_COM1 0x11005200 #define CONFIG_SYS_NS16550_CLK 26000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Environment settings */ #include <config_distro_bootcmd.h> diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index d4aa279b55..964c957813 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -13,9 +13,6 @@ #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Uboot definition */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 928f4b0dc7..7228f3e428 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -18,8 +18,6 @@ #define CONFIG_SYS_NS16550_COM1 0x11005000 #define CONFIG_SYS_NS16550_CLK 26000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Environment settings */ #include <config_distro_bootcmd.h> diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index e313f6f6af..6d4704644e 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -18,8 +18,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* Uboot definition */ #define ENV_BOOT_READ_IMAGE \ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index cae70760bc..51f7e16ece 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -15,8 +15,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ @@ -34,14 +32,6 @@ */ #define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 7d7c218bc6..5a956f0a3e 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -27,17 +27,9 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - /* USB ethernet */ /* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -/* * PCI configuration */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index ab466b65ac..dd303a17d6 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -15,10 +15,6 @@ /* Status LED */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Ethernet */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 3fb0003107..3507e83fb3 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -20,10 +20,6 @@ /* Environment is in MMC */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Framebuffer support */ #ifdef CONFIG_DM_VIDEO diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index fe096d424c..9f3ac48b70 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -15,17 +15,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Environment */ - -/* Environment is in MMC */ - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_RANGE (512 * 1024) -#endif - -/* Environment is in SPI flash */ - /* UBI and NAND partitioning */ /* RTC */ @@ -34,10 +23,6 @@ #endif /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* Framebuffer support */ #ifdef CONFIG_DM_VIDEO diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 1e5df3f7d7..f1d751f15a 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -16,8 +16,6 @@ #define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_FPGA_COUNT 1 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 2 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 0268a48c86..9ceed12e48 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -100,12 +100,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR - #define CONFIG_LBA48 -#endif - /* Framebuffer and LCD */ #endif /* __CONFIG_H */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 75bc27d179..e416f81e43 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -19,8 +19,6 @@ #endif #define CONFIG_MXC_GPT_HCLK -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - #include <linux/sizes.h> #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h> diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 76fbbf42da..cffbb64bcd 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -16,13 +16,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* SATA Configuration */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - /* Framebuffer */ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP @@ -34,7 +27,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "som_rev=undefined\0" \ "has_emmc=undefined\0" \ @@ -94,10 +86,6 @@ #include <config_distro_bootcmd.h> -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* CONFIG_SPL_BUILD */ - /* Physical Memory Map */ #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index d120c7c7a3..bc4aa52f5b 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -16,8 +16,6 @@ #define CONSOLE_DEV "ttymxc3" /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 2f4332a4b1..16f8858abb 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif @@ -36,10 +34,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index e03226d418..9f890938f9 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -94,10 +94,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #define CONFIG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 272492466d..c878041400 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -97,10 +97,8 @@ #define CONFIG_FEC_MXC_PHYADDR 0x0 #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index fda5b03b60..570e2ce687 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -19,8 +19,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI2 B flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ @@ -35,7 +33,7 @@ "sf write ${loadaddr} 0x0 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 1:0; bootaux 0x78000000\0" #else #define UPDATE_M4_ENV "" #endif @@ -124,23 +122,15 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1 #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_DM_VIDEO #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR -#endif -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 44e6fd0156..ab56ea0205 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -119,10 +119,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_NET @@ -135,10 +133,6 @@ #endif #endif -#ifndef CONFIG_SPL_BUILD -#if defined(CONFIG_DM_VIDEO) #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif -#endif #endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index db09db44d5..00cc547b90 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -21,14 +21,8 @@ /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 9f4dbec070..4704276a74 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -17,8 +17,6 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Enable iomux-lpsr support */ #define CONFIG_IOMUX_LPSR diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index a6b8c275fe..b96341a587 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -12,10 +12,7 @@ #define PHYS_SDRAM_SIZE SZ_1G - #ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI1 A flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ @@ -30,7 +27,7 @@ "sf write ${loadaddr} 0x0 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 0:0; bootaux 0x60000000\0" #else #define UPDATE_M4_ENV "" #endif diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index c6c3695e5d..62e8e62991 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -15,8 +15,6 @@ #include "imx7ulp_spl.h" #endif -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 57fed4ed69..e93824928b 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -11,8 +11,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index fb685ec963..4162ee8caa 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -34,15 +34,11 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -54,7 +50,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 815f81f649..1b7eb34334 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -37,13 +37,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=console=ttyS0,115200\0" \ - "mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\ - "0x010000@0xa0000(env),"\ - "0x500000@0xc0000(uimage),"\ - "0x1a40000@0x5c0000(rootfs)\0" \ - "mtdids=nand0=orion_nand\0"\ - "autostart=no\0"\ - "autoload=no\0" + "autostart=no\0" /* * Ethernet Driver configuration diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 3aa21a28d1..2007b48868 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -19,21 +19,10 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 6 /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -108,12 +97,4 @@ /* Environment organization */ -/* - * PCI express - */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 327dde5697..1696aa2852 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -39,7 +39,6 @@ /* I2C */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C EEPROM */ @@ -49,8 +48,6 @@ /* PCI express */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) #endif @@ -59,15 +56,11 @@ #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -/* SATA Configs */ -#define CONFIG_LBA48 - /* UART */ #define CONFIG_MXC_UART_BASE UART2_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 /* Gadget part */ @@ -79,7 +72,6 @@ #define CONFIG_IMX_VIDEO_SKIP /* Extra U-Boot environment. */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -150,8 +142,4 @@ #include <config_distro_bootcmd.h> -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* CONFIG_SPL_BUILD */ - #endif /* __CONFIG_H */ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 1fc4b87cab..217427a302 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -35,10 +35,8 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #ifdef CONFIG_CMD_NET #define CONFIG_FEC_MXC_PHYADDR 0x1 @@ -50,8 +48,6 @@ "console=ttymxc0,115200n8\0" \ "image=zImage\0" \ "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "kernel_addr_r=0x81000000\0" \ "pxefile_addr_r=0x87100000\0" \ @@ -62,7 +58,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 1e6b8d8b0e..027a47b5a3 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -15,8 +15,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ "kernel=/boot/zImage\0" \ "fdt=/boot/nsa310s.dtb\0" \ "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" @@ -25,8 +23,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 1 -/* Support large HDDs for USB and SATA */ -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - #endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nsim.h b/include/configs/nsim.h index 586ac3ebca..d469ef83c2 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_BOOTM_LEN SZ_32M - /* * Console configuration */ diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 7e71c83887..0fa7490e7d 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -16,6 +16,4 @@ #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeon_nic23.h b/include/configs/octeon_nic23.h index 0a7b4d8f93..7d99fd1b01 100644 --- a/include/configs/octeon_nic23.h +++ b/include/configs/octeon_nic23.h @@ -7,15 +7,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -/* - * SATA/SCSI/AHCI configuration - */ -/* AHCI support Definitions */ -/** Enable 48-bit SATA addressing */ -#define CONFIG_LBA48 -/** Enable 64-bit addressing */ -#define CONFIG_SYS_64BIT_LBA - #include "octeon_common.h" #endif /* __CONFIG_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 5c75f23a0b..2c430e8d37 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -8,7 +8,6 @@ #define __OCTEONTX2_COMMON_H__ /** Maximum size of image supported for bootm (and bootable FIT images) */ -#define CONFIG_SYS_BOOTM_LEN (256 << 20) /** Memory base address */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE @@ -18,8 +17,7 @@ /** Extra environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=20080000\0" \ - "ethrotate=yes\0" \ - "autoload=0\0" + "ethrotate=yes\0" #define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 22d3858878..e7a6bd41db 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -18,7 +18,6 @@ #include <config_distro_bootcmd.h> /* Extra environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=0\0" \ "loadaddr=0x20080000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x03000000\0" \ @@ -35,7 +34,6 @@ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ /** Maximum size of image supported for bootm (and bootable FIT images) */ -#define CONFIG_SYS_BOOTM_LEN (256 << 20) /** Memory base address */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE @@ -44,14 +42,6 @@ /** Heap size for U-Boot */ -/* AHCI support Definitions */ -#ifdef CONFIG_DM_SCSI -/** Enable 48-bit SATA addressing */ -# define CONFIG_LBA48 -/** Enable 64-bit addressing */ -# define CONFIG_SYS_64BIT_LBA -#endif - #define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 /** EMMC specific defines */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index dec658dd13..7448cc9520 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -144,14 +144,6 @@ "kernel_addr_r=0x41000000\0" \ BOOTENV -/* GPT */ - -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - /* * Supported Odroid boards: X3, U3 * TODO: Add Odroid X support diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index ed3cf212ac..1564629742 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -16,9 +16,6 @@ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - /* DFU */ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_MANIFEST_POLL_TIMEOUT 25000 @@ -31,9 +28,6 @@ #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 -/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ -#undef CONFIG_EXYNOS_TMU - #define CONFIG_DFU_ALT_SYSTEM \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index ab742798b9..2cd42e5a1d 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -62,7 +62,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(LEGACY_MMC, legacy_mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, rootfs, rootfs) \ func(NAND, nand, 0) #else /* !CONFIG_MTD_RAW_NAND */ @@ -84,8 +84,6 @@ "bootenv=uEnv.txt\0" \ "bootfile=zImage\0" \ "bootpart=0:2\0" \ - "bootubivol=rootfs\0" \ - "bootubipart=rootfs\0" \ "usbtty=cdc_acm\0" \ "mpurate=auto\0" \ "buddy=none\0" \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 9c4e172d03..2683d4c7ea 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -56,7 +56,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(LEGACY_MMC, legacy_mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, rootfs, rootfs) \ func(NAND, nand, 0) #else /* !CONFIG_MTD_RAW_NAND */ @@ -76,16 +76,12 @@ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_high=0xffffffff\0" \ "console=ttyO0,115200n8\0" \ "bootdir=/boot\0" \ "bootenv=uEnv.txt\0" \ "bootfile=zImage\0" \ "bootpart=0:2\0" \ - "bootubivol=rootfs\0" \ - "bootubipart=rootfs\0" \ "optargs=\0" \ "nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \ "nandrootfstype=ubifs rootwait\0" \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index c1ef040ce3..97f47ea5b7 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -28,8 +28,6 @@ #define GPIO_IGEP00X0_BOARD_DETECTION 28 #define GPIO_IGEP00X0_REVISION_DETECTION 129 -#ifndef CONFIG_SPL_BUILD - /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial\0" \ @@ -67,10 +65,7 @@ MEM_LAYOUT_SETTINGS \ BOOTENV -#endif - /* OneNAND config */ -#define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 12e502cd36..38dc7ea88f 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -35,8 +35,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "mmcrootfstype=ext4 rootwait\0" \ @@ -87,7 +85,6 @@ "nfsroot=${nfsrootpath} " \ "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \ "nfsrootpath=/opt/nfs-exports/omap\0" \ - "autoload=no\0" \ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "loadfdt=mmc rescan; " \ "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 75e84c35ee..cce5556fe2 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -40,9 +40,6 @@ #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 -/* USB UHH support options */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - /* Enabled commands */ /* USB Networking options */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index a344a46a3e..c9f5004117 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -138,12 +138,6 @@ */ /* - * USB Configs - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 12bd8fb99c..3ff8187b5d 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -15,7 +15,6 @@ /* Environment options */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_BOOTM_LEN SZ_256M /* --------------------------------------------------------------------- * Board boot configuration diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 8624d24b6e..3e551e13aa 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -24,151 +24,13 @@ /* USB */ #ifdef CONFIG_USB_EHCI_MX6 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* LCD */ -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_DM_VIDEO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif -#endif -/* Environment is stored in the eMMC boot partition */ - -#define CONFIG_ENV_VERSION 100 -#define ACFG_CONSOLE_DEV ttymxc0 -#define CONFIG_SYS_AUTOLOAD "no" #define CONFIG_ROOTPATH "/tftpboot/opos6ul-root" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ - "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ - "board_name=opos6ul\0" \ - "fdt_addr=0x88000000\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_name=opos6uldev\0" \ - "initrd_high=0xffffffff\0" \ - "ip_dyn=yes\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "kernelimg=opos6ul-linux.bin\0" \ - "splashpos=0,0\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ - "check_env=if test -n ${flash_env_version}; " \ - "then env default env_version; " \ - "else env set flash_env_version ${env_version}; env save; " \ - "fi; " \ - "if itest ${flash_env_version} != ${env_version}; then " \ - "echo \"*** Warning - Environment version" \ - " change suggests: run flash_reset_env; reset\"; " \ - "env default flash_reset_env; " \ - "else exit; fi; \0" \ - "flash_reset_env=env default -f -a && saveenv && " \ - "echo Environment variables erased!\0" \ - "download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl\0" \ - "flash_uboot_spl=" \ - "if mmc dev 0 1; then " \ - "setexpr sz ${filesize} / 0x200; " \ - "setexpr sz ${sz} + 1; " \ - "if mmc write ${loadaddr} 0x2 ${sz}; then " \ - "echo Flashing of U-boot SPL succeed; " \ - "else echo Flashing of U-boot SPL failed; " \ - "fi; " \ - "fi;\0" \ - "download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img\0" \ - "flash_uboot_img=" \ - "if mmc dev 0 1; then " \ - "setexpr sz ${filesize} / 0x200; " \ - "setexpr sz ${sz} + 1; " \ - "if mmc write ${loadaddr} 0x8a ${sz}; then " \ - "echo Flashing of U-boot image succeed; " \ - "else echo Flashing of U-boot image failed; " \ - "fi; " \ - "fi;\0" \ - "update_uboot=run download_uboot_spl flash_uboot_spl " \ - "download_uboot_img flash_uboot_img\0" \ - "download_kernel=tftpboot ${loadaddr} ${kernelimg}\0" \ - "flash_kernel=" \ - "if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then " \ - "echo kernel update succeed; " \ - "else echo kernel update failed; " \ - "fi;\0" \ - "update_kernel=run download_kernel flash_kernel\0" \ - "download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb\0" \ - "flash_dtb=" \ - "if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then " \ - "echo dtb update succeed; " \ - "else echo dtb update in failed; " \ - "fi;\0" \ - "update_dtb=run download_dtb flash_dtb\0" \ - "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4\0" \ - "flash_rootfs=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0x40800 ${nbblocks}; then " \ - "echo Flashing of rootfs image succeed; " \ - "else echo Flashing of rootfs image failed; " \ - "fi; " \ - "fi;\0" \ - "update_rootfs=run download_rootfs flash_rootfs\0" \ - "flash_failsafe=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0x800 ${nbblocks}; then " \ - "echo Flashing of rootfs image in failsafe partition succeed; " \ - "else echo Flashing of rootfs image in failsafe partition failed; " \ - "fi; " \ - "fi;\0" \ - "update_failsafe=run download_rootfs flash_failsafe\0" \ - "download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4\0" \ - "flash_userdata=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0 ${nbblocks}; then " \ - "echo Flashing of user_data image succeed; " \ - "else echo Flashing of user_data image failed; " \ - "fi; " \ - "fi;\0" \ - "update_userdata=run download_userdata flash_userdata; mmc rescan\0" \ - "erase_userdata=" \ - "if mmc dev 0 0; then " \ - "echo Erasing eMMC User Data partition, no way out...; " \ - "mw ${loadaddr} 0 0x200000; " \ - "mmc write ${loadaddr} 0 0x1000; " \ - "mmc write ${loadaddr} 0x800 0x1000; " \ - "mmc write ${loadaddr} 0x40800 0x1000; " \ - "mmc write ${loadaddr} 0x440800 0x1000; " \ - "fi;" \ - "mmc rescan\0" \ - "update_all=run update_rootfs update_uboot\0" \ - "initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}\0" \ - "addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ - "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ - "addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "emmcboot=run initargs; run addmmcargs; " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && " \ - "bootz ${loadaddr} - ${fdt_addr};\0" \ - "emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;\0" \ - "addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "nfsboot=run initargs; run addnfsargs addipargs; " \ - "nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && " \ - "nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && " \ - "bootz ${loadaddr} - ${fdt_addr};\0" - #endif /* __OPOS6ULDEV_CONFIG_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index 4d296b7a03..36aaa7c14f 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -10,10 +10,6 @@ #include <configs/exynos4-common.h> -/* High Level Configuration Options */ -#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ -#define CONFIG_ORIGEN 1 /* working with ORIGEN*/ - /* ORIGEN has 4 bank of DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 56a16502dc..e9217394e0 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -81,16 +81,13 @@ #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #elif defined(CONFIG_SPIFLASH) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) @@ -98,10 +95,6 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#else -#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif #endif /* not CONFIG_TPL_BUILD */ #endif @@ -109,25 +102,16 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - -#define CONFIG_LBA48 - #define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_L2_CACHE -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #if defined(CONFIG_TARGET_P1020RDB_PD) @@ -182,7 +166,6 @@ * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable * (early boot only) * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 - * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable @@ -289,14 +272,6 @@ #endif /* CPLD config size: 1Mb */ -#define CONFIG_SYS_PMC_BASE 0xff980000 -#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE -#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ - BR_PS_8 | BR_V) -#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) - /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" @@ -366,8 +341,6 @@ #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } #endif -#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ - /* * I2C2 EEPROM */ @@ -411,8 +384,6 @@ #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -439,15 +410,10 @@ /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #endif -#elif defined(CONFIG_SYS_RAMBOOT) -#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #endif #define CONFIG_LOADS_ECHO /* echo on for serial download */ @@ -456,17 +422,6 @@ /* * USB */ -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -#if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR @@ -482,7 +437,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 659f20e63a..6e593da936 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -46,15 +46,11 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -66,7 +62,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ + func(UBIFS, ubifs, 0, UBI, boot) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 0d099fa14c..ae81b8e214 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -48,10 +48,8 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index e360b166f5..a8cfec9659 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -33,7 +33,6 @@ /* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ PCM052_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "blimg_file=u-boot.vyb\0" \ @@ -50,7 +49,6 @@ "nfs_root=/path/to/nfs/root\0" \ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "bootargs_base=setenv bootargs rw " \ " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ "console=ttyLP1,115200n8\0" \ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index e87b6409ba..cff71df1c9 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -37,8 +37,6 @@ "mmcboot=run mmcloadfit;run mmcargs;bootm ${loadaddr}\0" #define ENV_NAND \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandroot=ubi0:root ubi.mtd=rootfs\0" \ "nandrootfstype=ubifs\0" \ "nandargs=setenv bootargs root=${nandroot} " \ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 7ab6a89604..ed3201aa3c 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -32,7 +32,6 @@ #define CONSOLE_DEV "ttyO5" #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=am335x-pdu001.dtb\0" \ @@ -49,7 +48,6 @@ "reset;" \ "fi;" \ "\0" -#endif /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 UART0_BASE diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index ff4180a833..7a8d3c63d4 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -22,13 +22,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 -/* Display */ -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - #define CONFIG_POWER_TPS65090_EC /* DRAM Memory Banks */ diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index 7fa911620e..f69d8adb91 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -16,8 +16,6 @@ #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${nandroot} " \ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index f8c3e1f10d..049d1d7434 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -11,7 +11,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index dd0b108a89..df1716106f 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -10,8 +10,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index ea30fbc4cf..2ac48c40c9 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -30,10 +30,8 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USBD_HS diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 5a6f224420..7fbf2c3f55 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -116,9 +116,7 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index a587570ea1..d1cc1b9d63 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -78,6 +78,4 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_BOOTM_LEN SZ_128M - #endif diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h index d478b19917..241dc39be0 100644 --- a/include/configs/pinebook-pro-rk3399.h +++ b/include/configs/pinebook-pro-rk3399.h @@ -16,7 +16,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 921f92bd01..7374514698 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -152,17 +152,9 @@ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index c6b106c64c..7a6d817926 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -175,17 +175,9 @@ AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index cb221501e2..085732214e 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -19,9 +19,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \ - "32M(rootfs),-(data)\0"\ - "mtdids=nand0=orion_nand\0"\ "bootargs_console=console=ttyS0,115200\0" \ "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ "ext2load usb 0:1 0x01100000 /uInitrd\0" diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h index 3365ebe3d2..7fff78b7b5 100644 --- a/include/configs/pogo_v4.h +++ b/include/configs/pogo_v4.h @@ -26,8 +26,6 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ "dtb_file=/boot/dts/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"\ - "mtdids=nand0=orion_nand\0"\ "bootargs_console=console=ttyS0,115200\0" \ "bootcmd_usb=usb start; load usb 0:1 0x00800000 /boot/uImage; " \ "load usb 0:1 0x01100000 /boot/uInitrd; " \ @@ -39,10 +37,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* - * Support large disk for SATA and USB - */ -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 - #endif /* _CONFIG_POGO_V4_H */ diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index 11d408f190..2e206542f8 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -14,14 +14,11 @@ /* SIZE of malloc pool */ /*BOOT*/ -#define CONFIG_SYS_BOOTM_LEN 0x3c00000 -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(SCSI, scsi, 0) \ #include <config_distro_bootcmd.h> -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/poplar.h b/include/configs/poplar.h index 6def369110..c58105597e 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -16,12 +16,10 @@ /* DRAM banks */ /* SYS */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* ATF bl33.bin load address (must match) */ /* USB configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /***************************************************************************** * Initial environment variables @@ -31,9 +29,7 @@ func(USB, usb, 0) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) -#ifndef CONFIG_SPL_BUILD #include <config_distro_bootcmd.h> -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "loader_mmc_blknum=0x0\0" \ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 48c0584d5b..90f548cc6c 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -8,8 +8,6 @@ #ifndef __PRESIDIO_ASIC_H #define __PRESIDIO_ASIC_H -#define CONFIG_SYS_BOOTM_LEN 0x00c00000 - /* Generic Timer Definitions */ #define CONFIG_SYS_TIMER_RATE 25000000 #define CONFIG_SYS_TIMER_COUNTER 0xf4321008 diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 96dcfb420f..49d1878ebd 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -13,19 +13,13 @@ /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ #define CONFIG_IRAM_BASE 0xff020000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -43,5 +37,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 7272470d12..4f24b13f50 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -30,10 +30,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ -#define CONFIG_FACTORYSET - -#ifndef CONFIG_SPL_BUILD - /* Use common default */ /* Default env settings */ @@ -69,9 +65,4 @@ "bootm ${kloadaddr}\0" \ "" -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ - #endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 14cae43db3..e9f756b13e 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -12,8 +12,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - /* GUIDs for capsule updatable firmware images */ #define QEMU_ARM_UBOOT_IMAGE_GUID \ EFI_GUID(0xf885b085, 0x99f8, 0x45af, 0x84, 0x7d, \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 60a17dbcdc..31e94df84d 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -9,12 +9,6 @@ #ifndef __QEMU_PPCE500_H #define __QEMU_PPCE500_H -#define CONFIG_SYS_MPC85XX_NO_RESETVEC - -#define CONFIG_SYS_RAMBOOT - -#define CONFIG_ENABLE_36BIT_PHYS - /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ @@ -29,10 +23,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #endif -/* Virtual address range for PCI region maps */ -#define CONFIG_SYS_PCI_MAP_START 0x80000000 -#define CONFIG_SYS_PCI_MAP_END 0xe0000000 - /* Virtual address to a temporary map if we need it (max 128MB) */ #define CONFIG_SYS_TMPVIRT 0xe8000000 @@ -60,8 +50,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_LBA48 - /* RTC */ #define CONFIG_RTC_PT7C4338 @@ -81,7 +69,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index f3e16e5596..d81e5d6c86 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -10,8 +10,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 #define RISCV_MMODE_TIMERBASE 0x2000000 @@ -21,7 +19,6 @@ /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ @@ -50,6 +47,5 @@ "pxefile_addr_r=0x8c200000\0" \ "ramdisk_addr_r=0x8c300000\0" \ BOOTENV -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index ae712629df..409d5af024 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -25,9 +25,4 @@ */ #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ -/* - * SuperH PCI Bridge Configration - */ -#define CONFIG_SH7751_PCI - #endif /* __CONFIG_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 8e20a448d2..49cd11c17b 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -37,13 +37,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=rastaban\0" \ @@ -55,8 +48,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_RASTABAN_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index e80e45dcbd..9efda3eeea 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -32,7 +32,6 @@ #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* ENV setting */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 2f3260e449..ac57721f02 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -17,8 +17,6 @@ #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -36,6 +34,5 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index 41e0d18f88..9297184bde 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -15,8 +15,6 @@ #define SDRAM_BANK_SIZE (1024UL << 20UL) #define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -34,6 +32,4 @@ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 5c60d119f9..12d4bc65d7 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -12,18 +12,11 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* RAW SD card / eMMC locations. */ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000 -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -#ifndef CONFIG_SPL_BUILD - /* usb mass storage */ #define ENV_MEM_LAYOUT_SETTINGS \ @@ -41,5 +34,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index c1d6684541..56fba3ff25 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -19,7 +19,6 @@ #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 -#ifndef CONFIG_SPL_BUILD /* usb otg */ /* usb host support */ @@ -43,6 +42,4 @@ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ - #endif diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index dd1a207aed..ec9e9ca1e3 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,8 +8,6 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) @@ -20,8 +18,6 @@ #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000 -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ @@ -39,6 +35,5 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 844c154217..f4b3481115 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,8 +9,6 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */ - #define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0xff700000 @@ -23,8 +21,6 @@ #define CONFIG_SYS_MONITOR_LEN (600 * 1024) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ @@ -44,6 +40,5 @@ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 169cf2ac9c..200b34b35b 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -11,17 +11,11 @@ #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_IRAM_BASE 0xfff80000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -37,5 +31,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 9cdc9004a9..1e214e4ebe 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,14 +10,10 @@ #define CONFIG_IRAM_BASE 0xff090000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* FAT sd card locations. */ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -33,9 +29,3 @@ BOOTENV #endif - -/* rockchip ohci host driver */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -#endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index ac88188682..37e0c1d936 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -16,9 +16,6 @@ #define CONFIG_IRAM_BASE 0xff8c0000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ @@ -34,5 +31,3 @@ BOOTENV #endif - -#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 3ca80c8c7c..2f9aee5819 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -15,8 +15,6 @@ /* BSS setup */ #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - /* MMC/SD IP block */ #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index f9c7c23cd9..15e8152340 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -10,12 +10,9 @@ #define CONFIG_IRAM_BASE 0xfdcc0000 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ "pxefile_addr_r=0x00e00000\0" \ @@ -30,6 +27,5 @@ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV -#endif #endif diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index 2edad71028..6099d2fa55 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -14,7 +14,4 @@ #include <configs/rk3399_common.h> #define SDRAM_BANK_SIZE (2UL << 30) - -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h index 903e9df527..9195b9b99e 100644 --- a/include/configs/rockpro64_rk3399.h +++ b/include/configs/rockpro64_rk3399.h @@ -14,7 +14,4 @@ #include <configs/rk3399_common.h> #define SDRAM_BANK_SIZE (2UL << 30) - -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 27738ab193..4f5025d0da 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -33,10 +33,6 @@ */ #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#ifdef CONFIG_ARM64 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#endif - /* Devices */ /* LCD */ diff --git a/include/configs/rut.h b/include/configs/rut.h index b30b12af52..ac48372b6c 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -21,13 +21,9 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ -#define CONFIG_FACTORYSET - /* Watchdog */ #define WATCHDOG_TRIGGER_GPIO 14 -#ifndef CONFIG_SPL_BUILD - /* Use common default */ /* Default env settings */ @@ -61,10 +57,4 @@ "bootm ${kloadaddr}\0" \ "" -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif - -#endif /* CONFIG_SPL_BUILD */ - #endif /* ! __CONFIG_RUT_H */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index f088f0e7a0..83c3167f38 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -18,11 +18,7 @@ #define CONFIG_SYS_SDRAM_BASE 0x60000000 /* rockchip ohci host driver */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif -#ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "fdt_addr_r=0x61f00000\0" \ @@ -35,4 +31,5 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ BOOTENV + #endif diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index d27116ad11..712a47a495 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -10,11 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_S5PC110 1 /* which is in a S5PC110 */ - #include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ @@ -26,9 +21,6 @@ /* MMC */ #define SDHCI_MAX_HOSTS 4 -/* PWM */ -#define CONFIG_PWM 1 - /* USB Composite download gadget - g_dnl */ #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -134,10 +126,6 @@ /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 #define CONFIG_SYS_ONENAND_BASE 0xB0000000 -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 8df7377a0f..137537d65f 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -11,8 +11,6 @@ #include <configs/exynos4-common.h> -#define CONFIG_TIZEN /* TIZEN lib */ - /* Keep L2 Cache Disabled */ /* Universal has 2 banks of DRAM */ @@ -77,7 +75,6 @@ "verify=n\0" \ "rootfstype=ext4\0" \ "console=console=ttySAC1,115200n8\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "mbrparts=" MBRPARTS_DEFAULT \ "meminfo=crashkernel=32M@0x50000000\0" \ "nfsroot=/nfsroot/arm\0" \ @@ -90,12 +87,8 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND #define CONFIG_SYS_ONENAND_BASE 0x0C000000 -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); void universal_spi_sda(int bit); diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index a10057452f..fad65cb112 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -37,17 +37,6 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* SPL */ /* size of u-boot.bin to load */ diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index f61b6e0dab..7bc3f91e77 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -50,16 +50,6 @@ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#endif - /* SPL */ #define CONFIG_SYS_MONITOR_LEN (512 << 10) diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 78347373fc..3f905bf2d7 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index c22b74f707..5168e2fa35 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,9 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifndef CONFIG_SPL_BUILD #define CONFIG_IO_TRACE -#endif #define CONFIG_MALLOC_F_ADDR 0x0010000 diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index e1b8c61d07..af5fe27e68 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -22,6 +22,5 @@ "bootcmd=source $prevbl_initrd_start_addr:bootscript\0" /* Size of malloc() pool */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M #endif diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 58345e4e1b..19701ccce2 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -27,10 +27,4 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -/* - * Support large disk for SATA and USB - */ -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 - #endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 941e02c5c6..d2d4296eed 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -17,11 +17,7 @@ /* commands to include */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_ROOTPATH "/opt/eldk" -#endif - -#define CONFIG_SYS_AUTOLOAD "yes" /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ @@ -81,16 +77,12 @@ * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD - /* USB DRACO ID as default */ #define CONFIG_USBD_HS /* USB Device Firmware Update support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#endif /* CONFIG_SPL_BUILD */ - /* * Default to using SPI for environment, etc. We have multiple copies * of SPL as the ROM will check these locations. diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 4442fc29e3..2e5592cf94 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 #define RISCV_MMODE_TIMERBASE 0x2000000 @@ -24,7 +22,6 @@ /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(SF, sf, 0) \ @@ -61,6 +58,5 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV \ BOOTENV_SF -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index f5a341c844..9923f3d9c3 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -13,13 +13,10 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(NVME, nvme, 0) \ func(USB, usb, 0) \ @@ -53,7 +50,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV -#endif /* CONFIG_SPL_BUILD */ #define CONFIG_SYS_EEPROM_BUS_NUM 0 diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index cde6abc626..1a3ac817fb 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -41,9 +41,6 @@ /* misc settings */ -/* setting board specific options */ -#define CONFIG_SYS_AUTOLOAD "yes" - /* * SDRAM: 1 bank, 64 MB, base address 0x20000000 * Already initialized before u-boot gets started. @@ -69,32 +66,16 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#if !defined(CONFIG_SPL_BUILD) -/* USB configuration */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* USB DFU support */ #define CONFIG_USB_GADGET_AT91 /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#endif /* General Boot Parameter */ /* - * The NAND Flash partitions: - */ -#define CONFIG_ENV_RANGE (SZ_512K) - -/* * Predefined environment variables. * Usefull to define some easy to use boot commands. */ @@ -102,7 +83,6 @@ \ "basicargs=console=ttyS0,115200\0" \ \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 1ea3b650cd..c6d2b23197 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -12,7 +12,4 @@ #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h> -#undef CONFIG_EXYNOS_FB -#undef CONFIG_EXYNOS_DP - #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index f8d2fafd27..12c2e1f615 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -12,16 +12,10 @@ #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h> -#undef CONFIG_EXYNOS_FB -#undef CONFIG_EXYNOS_DP - #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 -/* USB */ -#define CONFIG_USB_XHCI_EXYNOS - /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 2f04b077ad..1395b8dfe3 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -11,14 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_S5PC100 1 /* which is in a S5PC100 */ - #include <asm/arch/cpu.h> /* get chip and board defs */ /* input clock of PLL: SMDKC100 has 12MHz input clock */ @@ -32,9 +24,6 @@ * select serial console configuration */ -/* PWM */ -#define CONFIG_PWM 1 - #define COMMON_BOOT "console=ttySAC0,115200n8" \ " mem=128M " \ " " CONFIG_MTDPARTS_DEFAULT @@ -77,7 +66,6 @@ " console=ttySAC0,115200n8 mem=128M" \ " initrd=0x33000000,8M ramdisk=8192\0" \ "rootfstype=cramfs\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "meminfo=mem=128M\0" \ "nfsroot=/nfsroot/arm\0" \ "bootblock=5\0" \ @@ -98,22 +86,10 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ -#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) -#define CONFIG_ENABLE_MMU -#endif - -#ifdef CONFIG_ENABLE_MMU -#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 -#else -#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE -#endif - /*----------------------------------------------------------------------- * Boot configuration */ -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 #define CONFIG_SYS_ONENAND_BASE 0xE7100000 /* diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 1367b7d060..0b1f0c5f54 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -10,11 +10,7 @@ #include "exynos4-common.h" -#undef CONFIG_USB_GADGET_DWC2_OTG_PHY - /* High Level Configuration Options */ -#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ - #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* Handling Sleep Mode*/ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 6ff21b9216..7adb349f9a 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -37,15 +37,6 @@ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* GPIOs and IO expander */ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 3a77c71874..261ae56c1d 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -23,8 +23,6 @@ */ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - /* Environment settings */ /* @@ -66,8 +64,6 @@ "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \ "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \ "userload=ubi part nand.ubi &&" \ "ubi check rootfs$bootnum &&" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 6453ab7952..4a7da76e51 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -52,20 +52,6 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* - * Ethernet on SoC (EMAC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_DW_ALTDESCRIPTOR -#endif - -/* - * FPGA Driver - */ -#ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA_COUNT 1 -#endif - -/* * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER @@ -80,7 +66,6 @@ /* * L4 Watchdog */ -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 /* diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index 468a35d4ff..ad27179120 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -16,9 +16,4 @@ /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> -/* - * Bootcounter - */ -#define CONFIG_SYS_BOOTCOUNT_BE - #endif /* __CONFIG_SOCFPGA_IS1_H__ */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index b71f8bab15..06198ddd82 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -22,7 +22,6 @@ */ /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) /* * U-Boot run time memory configurations @@ -35,21 +34,6 @@ */ /* - * QSPI support - */ - #ifdef CONFIG_CADENCE_QSPI -/* Enable it if you want to use dual-stacked mode */ -/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ - -/* Flash device info */ - -#ifndef CONFIG_SPL_BUILD -#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" -#endif /* CONFIG_SPL_BUILD */ - -#endif /* CONFIG_CADENCE_QSPI */ - -/* * Environment variable */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -104,15 +88,9 @@ * Flash configurations */ -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_DW_ALTDESCRIPTOR -#endif /* CONFIG_CMD_NET */ - /* * L4 Watchdog */ -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 62c1bc7408..432144cb40 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -18,11 +18,6 @@ /* Enable SPI NOR flash reset, needed for SPI booting */ #define CONFIG_SPI_N25Q256A_RESET -/* - * Bootcounter - */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* Environment setting for SPI flash */ /* The rest of the configuration is shared */ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index c333c931ab..70d9f3607a 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -11,7 +11,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ /* Booting Linux */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 3309779118..5dc8d85598 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -22,7 +22,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 /* * sysclk for MPC85xx @@ -119,15 +118,11 @@ #define CONFIG_SYS_LIME_BASE 0xc8000000 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - /* * General PCI * Memory space is mapped 1-1. */ -/* PCI is clocked by the external source at 33 MHz */ -#define CONFIG_PCI_CLK_FREQ 33000000 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ @@ -227,11 +222,4 @@ /* pass open firmware flat tree */ -/* USB support */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_PCI_OHCI 1 -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index f1886cb214..eeee587baf 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -65,10 +65,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 4ad55afad8..71b25c23b1 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -13,7 +13,6 @@ * low-level initialization and rely on configuration provided by the Samsung * bootloader. New images are loaded at the same address for compatibility. */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* FIXME: This should be loaded from device tree... */ #define CONFIG_SYS_L2_PL310 diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index a425dad692..b1a011bacb 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -24,8 +24,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -#define CONFIG_SYS_BOOTM_LEN SZ_16M - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ @@ -43,8 +41,6 @@ /* Extra Commands */ /* USB Configs */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 /* NET Configs */ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 05ac900f3c..df05ee4892 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -20,9 +20,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 8 -#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) -#define CONFIG_DW_ALTDESCRIPTOR - #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index beb56fcb5a..3ca65ea2a3 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_256M /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 2 diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index fc636beb3f..c5412ffeb3 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_BOOTMAPSZ SZ_256M /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 @@ -33,7 +32,6 @@ /* Ethernet need */ #ifdef CONFIG_DWC_ETH_QOS #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_SYS_AUTOLOAD "no" #endif /*****************************************************************************/ @@ -59,7 +57,7 @@ #endif #ifdef CONFIG_CMD_UBIFS -#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0) +#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) #else #define BOOT_TARGET_UBIFS(func) #endif diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 2195feeb65..d8a334868f 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_SBFHDR_SIZE 0x7 /* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK #define CONFIG_PRAM 2048 /* 2048 KB */ @@ -107,12 +106,4 @@ #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 12) -#ifdef CONFIG_MCFFEC -#define CONFIG_SYS_DISCOVER_PHY -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif #endif /* __STMARK2_CONFIG_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index c57b1ad8a0..567aa1ffe4 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -20,10 +20,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 /* U-Boot Load Address */ -/* GMAC related configs */ - -#define CONFIG_DW_ALTDESCRIPTOR - /* Misc configuration */ #endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5b543fd2db..0f0ef4f64b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -15,10 +15,6 @@ #include <asm/arch/cpu.h> #include <linux/stringify.h> -#ifdef CONFIG_ARM64 -#define CONFIG_SYS_BOOTM_LEN (32 << 20) -#endif - /* Serial & console */ #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ @@ -75,10 +71,6 @@ #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -#ifdef CONFIG_AHCI -#define CONFIG_SYS_64BIT_LBA -#endif - #ifdef CONFIG_NAND_SUNXI #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #define CONFIG_SYS_MAX_NAND_DEVICE 8 @@ -124,13 +116,6 @@ /* Ethernet support */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - -#ifndef CONFIG_SPL_BUILD - #ifdef CONFIG_ARM64 /* * Boards seem to come with at least 512MB of DRAM. @@ -323,20 +308,6 @@ "stderr=serial\0" #endif -#ifdef CONFIG_MTDIDS_DEFAULT -#define SUNXI_MTDIDS_DEFAULT \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" -#else -#define SUNXI_MTDIDS_DEFAULT -#endif - -#ifdef CONFIG_MTDPARTS_DEFAULT -#define SUNXI_MTDPARTS_DEFAULT \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define SUNXI_MTDPARTS_DEFAULT -#endif - #define PARTS_DEFAULT \ "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ @@ -368,16 +339,10 @@ DFU_ALT_INFO_RAM \ "fdtfile=" FDTFILE "\0" \ "console=ttyS0,115200\0" \ - SUNXI_MTDIDS_DEFAULT \ - SUNXI_MTDPARTS_DEFAULT \ "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ "partitions=" PARTS_DEFAULT "\0" \ BOOTCMD_SUNXI_COMPAT \ BOOTENV -#else /* ifndef CONFIG_SPL_BUILD */ -#define CONFIG_EXTRA_ENV_SETTINGS -#endif - #endif /* _SUNXI_COMMON_CONFIG_H */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 5b862f4f2e..63d897d090 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -60,7 +60,6 @@ 0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30) /* Distro boot settings */ -#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB #define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) #else @@ -92,9 +91,6 @@ BOOT_TARGET_DEVICE_NVME(func) \ #include <config_distro_bootcmd.h> -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x9fe00000\0" \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index b9285e8cab..4758e23f55 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -63,16 +63,7 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif -/* USB */ #if defined(CONFIG_BOARD_TAURUS) -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - /* USB DFU support */ #define CONFIG_USB_GADGET_AT91 @@ -84,13 +75,8 @@ /* SPI EEPROM */ #define TAURUS_SPI_MASK (1 << 4) -#if defined(CONFIG_SPL_BUILD) -/* SPL related */ -#endif - /* bootstrap in spi flash , u-boot + env + linux in nandflash */ -#ifndef CONFIG_SPL_BUILD #if defined(CONFIG_BOARD_AXM) #define CONFIG_EXTRA_ENV_SETTINGS \ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ @@ -139,7 +125,6 @@ "stdout=serial\0" \ "upgrade_available=0\0" #endif -#endif /* #ifndef CONFIG_SPL_BUILD */ /* Defines for SPL */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 03aeb4f5d2..16bdc39b75 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_BOOTM_LEN SZ_32M - /* * UART configuration */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index c355083519..c93df00d58 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -26,22 +26,11 @@ /* PCI */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #endif -/* SATA */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA -#endif - /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #ifdef CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USBD_HS diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 755a41fef7..c8f9d7cb17 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -9,8 +9,6 @@ #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#ifndef CONFIG_SPL_BUILD - #if CONFIG_IS_ENABLED(CMD_USB) # define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -26,9 +24,6 @@ func(DHCP, dhcp, na) #endif #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif #ifdef CONFIG_TEGRA_KEYBOARD #define STDIN_KBD_KBC ",tegra-kbc" diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 7420831589..87ec1f5a99 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -55,7 +55,4 @@ /* Defines for SPL */ -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 314486a1bc..0485fea6cc 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -57,10 +57,4 @@ /* Defines for SPL */ -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -/* GPU needs setup */ -#define CONFIG_TEGRA_GPU - #endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index a2b14d8ead..71867bb6ba 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -69,12 +69,4 @@ #define TEGRA_LP0_VEC #endif -/* - * This parameter affects a TXFILLTUNING field that controls how much data is - * sent to the latency fifo before it is sent to the wire. Without this - * parameter, the default (2) causes occasional Data Buffer Errors in OUT - * packets depending on the buffer address and size. - */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - #endif /* _TEGRA20_COMMON_H_ */ diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 3ba12bec0e..7f361d874a 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,10 +46,4 @@ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83420000\0" -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -/* GPU needs setup */ -#define CONFIG_TEGRA_GPU - #endif /* _TEGRA210_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index a68da5ddfc..04fcf11ed8 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -52,7 +52,4 @@ /* Defines for SPL */ -/* For USB EHCI controller */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - #endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index c81e89eed8..655fcb0011 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -29,7 +29,6 @@ #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ @@ -40,12 +39,6 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -/* SATA support */ -#define CONFIG_LBA48 - -/* FPGA programming support */ -#define CONFIG_FPGA_STRATIX_V - /* * Bootcounter */ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 3b120073fe..696306e465 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -30,13 +30,6 @@ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=thuban\0" \ @@ -48,8 +41,4 @@ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ -#endif -#endif /* CONFIG_SPL_BUILD */ #endif /* ! __CONFIG_THUBAN_H */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index cc3891fd6d..cf2efdbe23 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -6,10 +6,6 @@ #ifndef __THUNDERX_88XX_H__ #define __THUNDERX_88XX_H__ -#define CONFIG_THUNDERX - -#define CONFIG_SYS_64BIT - #define MEM_BASE 0x00500000 #define CONFIG_SYS_LOWMEM_BASE MEM_BASE diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index fa5d91099e..1aca83a9bc 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -13,9 +13,7 @@ #include <asm/arch/omap.h> #define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + DEFAULT_LINUX_BOOT_ENV /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 6952cc6371..bf76afaede 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -184,9 +184,7 @@ "args_ramfs=setenv bootargs ${bootargs} " \ "rdinit=/sbin/init rw root=/dev/ram0 " \ "initrd=0x808080000,80M\0" \ - "no_post=1\0" \ - "mtdparts=mtdparts=davinci_nand.0:" \ - "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" + "no_post=1\0" /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 5d8c45af2f..3d78972bfe 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -23,17 +23,6 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - #include <configs/ti_armv7_omap.h> /* @@ -47,9 +36,7 @@ #endif /* TWL6030 */ -#ifndef CONFIG_SPL_BUILD #define CONFIG_TWL6030_POWER 1 -#endif /* * Environment setup diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index f7f17d0f50..24bbf9e7c2 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -19,19 +19,6 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#define CONFIG_PALMAS_POWER - #include <linux/stringify.h> #include <asm/arch/cpu.h> diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index 41297b693c..4fb3d731c6 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -11,8 +11,6 @@ /* Link Definitions */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - #define UART0_BASE 0x7ff80000 /* PL011 Serial Configuration */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 3866a43332..f5466fd509 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -24,10 +24,6 @@ */ /* Miscellaneous configurable options */ -/* USB, USB storage, USB ethernet */ -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_EHCI_DESC_BIG_ENDIAN - /* * Diagnostics */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 3290ec021f..a782e3d02b 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -52,9 +52,6 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ - #if defined(CONFIG_TQMA6X_MMC_BOOT) diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 90db96599c..999130600c 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -24,9 +24,6 @@ /* LED */ -/* Bootcounter */ -#define CONFIG_SYS_BOOTCOUNT_BE - /* I2C */ #endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index db33560f0d..53f5a6996b 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -11,10 +11,6 @@ #include <configs/exynos4-common.h> -#define CONFIG_TRATS - -#define CONFIG_TIZEN /* TIZEN lib */ - #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 @@ -130,9 +126,6 @@ /* GPT */ -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - /* Common misc for Samsung */ #define CONFIG_MISC_COMMON @@ -156,8 +149,6 @@ #define LCD_BPP LCD_COLOR16 /* LCD */ -#define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index a4d598d085..b7449dab8b 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -12,8 +12,6 @@ #include <configs/exynos4-common.h> -#define CONFIG_TIZEN /* TIZEN lib */ - #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 @@ -118,9 +116,6 @@ /* GPT */ -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - /* Common misc for Samsung */ #define CONFIG_MISC_COMMON @@ -144,8 +139,6 @@ #define LCD_BPP LCD_COLOR16 /* LCD */ -#define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 7fa30d04f3..401627a47a 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -8,7 +8,6 @@ #ifndef _CONFIG_TURRIS_MOX_H #define _CONFIG_TURRIS_MOX_H -#define CONFIG_SYS_BOOTM_LEN (64 << 20) #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ @@ -18,8 +17,6 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -#define CONFIG_USB_MAX_CONTROLLER_COUNT 6 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(NVME, nvme, 0) \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index c8d1ed4da6..03e5c04af6 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -14,9 +14,6 @@ #define CONFIG_MXC_UART_BASE UART2_BASE -/* SATA Configs */ -#define CONFIG_LBA48 - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 2bb9e59b94..15ae0844c1 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_UNIPHIER_H__ #define __CONFIG_UNIPHIER_H__ -#ifndef CONFIG_SPL_BUILD #include <config_distro_bootcmd.h> #ifdef CONFIG_CMD_MMC @@ -20,7 +19,7 @@ #endif #ifdef CONFIG_CMD_UBIFS -#define BOOT_TARGET_DEVICE_UBIFS(func) func(UBIFS, ubifs, 0) +#define BOOT_TARGET_DEVICE_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) #else #define BOOT_TARGET_DEVICE_UBIFS(func) #endif @@ -35,9 +34,6 @@ BOOT_TARGET_DEVICE_MMC(func) \ BOOT_TARGET_DEVICE_UBIFS(func) \ BOOT_TARGET_DEVICE_USB(func) -#else -#define BOOTENV -#endif #define CONFIG_SYS_MONITOR_LEN 0x00200000 /* 2MB */ @@ -58,8 +54,6 @@ #define CONFIG_GATEWAYIP 192.168.11.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SYS_BOOTM_LEN (32 << 20) - #if defined(CONFIG_ARM64) /* ARM Trusted Firmware */ #define BOOT_IMAGES \ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 32e8f6be0d..e0dde1cc83 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -43,18 +43,7 @@ #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - /* bootstrap + u-boot + env + linux in dataflash on CS0 */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ #endif diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 88c3061db6..78a62a8b02 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -32,18 +32,7 @@ #error Unknown DDR size - please add! #endif -#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) -#define VCOREIII_DEFAULT_MTD_ENV \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ - "mtdids="CONFIG_MTDIDS_DEFAULT"\0" -#else -#define VCOREIII_DEFAULT_MTD_ENV /* Go away */ -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - #define CONFIG_EXTRA_ENV_SETTINGS \ - VCOREIII_DEFAULT_MTD_ENV \ "loadaddr=0x81000000\0" \ "spi_image_off=0x00100000\0" \ "console=ttyS0,115200\0" \ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 19c16df488..5b5fce9bda 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_SYS_BOOTM_LEN SZ_64M - #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 @@ -28,15 +26,11 @@ "scriptaddr=0x46000000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -75,8 +69,6 @@ #define CONFIG_FEC_MXC_PHYADDR 7 /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* __VERDIN_IMX8MM_H */ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 9ad24e82db..fca40beba1 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -40,15 +40,11 @@ "scriptaddr=0x46000000\0" /* Enable Distro Boot */ -#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#else -#define BOOTENV -#endif #if defined(CONFIG_TDX_EASY_INSTALLER) # define BOOT_SCRIPT "boot-tezi.scr" @@ -79,8 +75,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 14b92c095a..3705313aec 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -15,8 +15,6 @@ /* ATF loads u-boot here for BASE_FVP model */ #endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - /* CS register bases for the original memory map. */ #ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP #define V2M_DRAM_BASE 0x00000000 @@ -274,11 +272,6 @@ /* Store environment at top of flash */ #endif -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ #define FLASH_MAX_SECTOR_SIZE 0x00040000 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 6ad1ba9e02..32d9df0a00 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -26,7 +26,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* I2C Configs */ -#define CONFIG_SYS_SPD_BUS_NUM 0 /* * We do have 128MB of memory on the Vybrid Tower board. Leave the last @@ -130,8 +129,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_RANGE (512 * 1024) -#endif - #endif diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a447ec8c34..6eb022f26c 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -41,14 +41,10 @@ /* Network */ #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index d422412714..899b8ca470 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -14,14 +14,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -/* SATA Configs */ - -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/warp.h b/include/configs/warp.h index 74fa03b53d..7cb9743fdd 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -34,10 +34,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */ #endif #define CONFIG_USBD_HS diff --git a/include/configs/x530.h b/include/configs/x530.h index d8fc3c13d0..cb126837b9 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -47,11 +47,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - /* NAND */ #include <asm/arch/config.h> diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index b45d2bbd62..4109af7d85 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -12,18 +12,6 @@ #define CONFIG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 -#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff - #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 48091b95ca..42b2cb2fc8 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -14,14 +14,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/* SATA AHCI storage */ -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -#endif /* Generic TPM interfaced through LPC bus */ #define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 @@ -52,11 +44,6 @@ */ /*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI_CONFIG_HOST_BRIDGE - -/*----------------------------------------------------------------------- * USB configuration */ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 55837e1c56..971bd69dec 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -37,8 +37,6 @@ # define PHY_ANEG_TIMEOUT 20000 #endif -#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024) - #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ "fdt_size_r=0x400000\0" \ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index bfd622bb02..f72f3e6447 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -37,13 +37,11 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_THOR_RESET_OFF -#ifndef CONFIG_SPL_BUILD # define PARTS_DEFAULT \ "partitions=uuid_disk=${uuid_gpt_disk};" \ "name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \ "name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0" #endif -#endif #if !defined(PARTS_DEFAULT) # define PARTS_DEFAULT @@ -56,8 +54,6 @@ # define PHY_ANEG_TIMEOUT 20000 #endif -#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024) - #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_addr_r=0x40000000\0" \ "fdt_size_r=0x400000\0" \ @@ -209,11 +205,6 @@ /* ATF is my kernel image */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) -# define CONFIG_SPL_HASH -# define CONFIG_ENV_MAX_ENTRIES 10 -#endif - #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" #endif diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index 37750d3d15..b6bc402a7e 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -19,6 +19,5 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 8e36d1c4c3..0e43b37364 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -31,10 +31,8 @@ /* Environment is in stored in the eMMC boot partition */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 7392582b5e..f1ea476546 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -16,12 +16,6 @@ * differences. */ -/*=====================*/ -/* Board and Processor */ -/*=====================*/ - -#define CONFIG_XTFPGA - /*===================*/ /* RAM Layout */ /*===================*/ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 6a045ec60a..1fdde90654 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -204,7 +204,6 @@ /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) /* Boot FreeBSD/vxWorks from an ELF image */ #define CONFIG_SYS_MMC_MAX_DEVICE 1 diff --git a/include/dm/platform_data/pxa_mmc_gen.h b/include/dm/platform_data/pxa_mmc_gen.h deleted file mode 100644 index d15c1551f4..0000000000 --- a/include/dm/platform_data/pxa_mmc_gen.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Marcel Ziswiler <marcel.ziswiler@toradex.com> - */ - -#ifndef __PXA_MMC_GEN_H -#define __PXA_MMC_GEN_H - -#include <mmc.h> - -/* - * struct pxa_mmc_plat - information about a PXA MMC controller - * - * @base: MMC controller base register address - */ -struct pxa_mmc_plat { - struct mmc_config cfg; - struct mmc mmc; - struct pxa_mmc_regs *base; -}; - -#endif /* __PXA_MMC_GEN_H */ diff --git a/include/dm/platform_data/serial_pxa.h b/include/dm/platform_data/serial_pxa.h deleted file mode 100644 index e1a02aed28..0000000000 --- a/include/dm/platform_data/serial_pxa.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com> - */ - -#ifndef __SERIAL_PXA_H -#define __SERIAL_PXA_H - -/* - * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can - * easily handle enabling of clock. - */ -#ifdef CONFIG_CPU_MONAHANS -#define UART_CLK_BASE CKENA_21_BTUART -#define UART_CLK_REG CKENA -#define BTUART_INDEX 0 -#define FFUART_INDEX 1 -#define STUART_INDEX 2 -#else /* PXA27x */ -#define UART_CLK_BASE CKEN5_STUART -#define UART_CLK_REG CKEN -#define STUART_INDEX 0 -#define FFUART_INDEX 1 -#define BTUART_INDEX 2 -#endif - -/* - * struct pxa_serial_plat - information about a PXA port - * - * @base: Uart port base register address - * @port: Uart port index, for cpu with pinmux for uart / gpio - * baudrtatre: Uart port baudrate - */ -struct pxa_serial_plat { - struct pxa_uart_regs *base; - int port; - int baudrate; -}; - -#endif /* __SERIAL_PXA_H */ diff --git a/include/dt-bindings/sound/microchip,pdmc.h b/include/dt-bindings/sound/microchip,pdmc.h new file mode 100644 index 0000000000..96cde94ce7 --- /dev/null +++ b/include/dt-bindings/sound/microchip,pdmc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_MICROCHIP_PDMC_H__ +#define __DT_BINDINGS_MICROCHIP_PDMC_H__ + +/* PDM microphone's pin placement */ +#define MCHP_PDMC_DS0 0 +#define MCHP_PDMC_DS1 1 + +/* PDM microphone clock edge sampling */ +#define MCHP_PDMC_CLK_POSITIVE 0 +#define MCHP_PDMC_CLK_NEGATIVE 1 + +#endif /* __DT_BINDINGS_MICROCHIP_PDMC_H__ */ diff --git a/include/env_default.h b/include/env_default.h index 7004a6fef2..4e461c815a 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -59,8 +59,8 @@ const char default_environment[] = { #ifdef CONFIG_SERVERIP "serverip=" __stringify(CONFIG_SERVERIP) "\0" #endif -#ifdef CONFIG_SYS_AUTOLOAD - "autoload=" CONFIG_SYS_AUTOLOAD "\0" +#ifdef CONFIG_SYS_DISABLE_AUTOLOAD + "autoload=0\0" #endif #ifdef CONFIG_PREBOOT "preboot=" CONFIG_PREBOOT "\0" @@ -108,10 +108,13 @@ const char default_environment[] = { #if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0) "bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0" #endif +#ifdef CONFIG_MTDIDS_DEFAULT + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" +#endif +#ifdef CONFIG_MTDPARTS_DEFAULT + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" +#endif #ifdef CONFIG_EXTRA_ENV_TEXT -# ifdef CONFIG_EXTRA_ENV_SETTINGS -# error "Your board uses a text-file environment, so must not define CONFIG_EXTRA_ENV_SETTINGS" -# endif /* This is created in the Makefile */ CONFIG_EXTRA_ENV_TEXT #endif diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index fb838db0b5..3092a0ea62 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -23,8 +23,6 @@ #define sec_mon_in16(a) in_be16(a) #define sec_mon_clrbits32 clrbits_be32 #define sec_mon_setbits32 setbits_be32 -#else -#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined #endif struct ccsr_sec_mon_regs { diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 613814d905..e7674c1bff 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -24,8 +24,6 @@ #define sfp_in32(a) in_be32(a) #define sfp_out32(a, v) out_be32(a, v) #define sfp_in16(a) in_be16(a) -#else -#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined #endif /* Number of SRKH registers */ diff --git a/include/i2c.h b/include/i2c.h index 22add0b528..e0ee94e550 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -647,9 +647,6 @@ void i2c_early_init_f(void); #if !defined(CONFIG_SYS_RTC_BUS_NUM) #define CONFIG_SYS_RTC_BUS_NUM 0 #endif -#if !defined(CONFIG_SYS_SPD_BUS_NUM) -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif struct i2c_adapter { void (*init)(struct i2c_adapter *adap, int speed, diff --git a/include/ide.h b/include/ide.h index 2994b7a762..426cef4e39 100644 --- a/include/ide.h +++ b/include/ide.h @@ -33,10 +33,6 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer); #endif -#ifdef CONFIG_IDE_PREINIT -int ide_preinit(void); -#endif - #if defined(CONFIG_OF_IDE_FIXUP) int ide_device_present(int dev); #endif diff --git a/include/lcd.h b/include/lcd.h index 7570e7ac60..4f18069278 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -40,9 +40,7 @@ ulong lcd_setmem(ulong addr); */ void lcd_set_flush_dcache(int flush); -#if defined(CONFIG_CPU_PXA27X) || defined CONFIG_CPU_MONAHANS -#include <pxa_lcd.h> -#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) +#if defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) #include <atmel_lcd.h> #elif defined(CONFIG_EXYNOS_FB) #include <exynos_lcd.h> diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 1367149c4b..40979f72fc 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -53,21 +53,4 @@ struct fsl_xhci { struct dwc3 *dwc3_reg; }; -#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR -#endif - -#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ - CONFIG_SYS_FSL_XHCI_USB2_ADDR, \ - CONFIG_SYS_FSL_XHCI_USB3_ADDR} #endif /* _ASM_ARCH_XHCI_FSL_H_ */ diff --git a/include/power/fg_battery_cell_params.h b/include/power/fg_battery_cell_params.h index b8c895bbab..500c8ea717 100644 --- a/include/power/fg_battery_cell_params.h +++ b/include/power/fg_battery_cell_params.h @@ -7,7 +7,7 @@ #ifndef __FG_BATTERY_CELL_PARAMS_H_ #define __FG_BATTERY_CELL_PARAMS_H_ -#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TRATS) +#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TARGET_TRATS) /* Cell characteristics - Exynos4 TRATS development board */ /* Shall be written to addr 0x80h */ diff --git a/include/pxa_lcd.h b/include/pxa_lcd.h deleted file mode 100644 index 11a22abca6..0000000000 --- a/include/pxa_lcd.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * pxa_lcd.h - PXA LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#ifndef _PXA_LCD_H_ -#define _PXA_LCD_H_ - -/* - * PXA LCD DMA descriptor - */ -struct pxafb_dma_descriptor { - u_long fdadr; /* Frame descriptor address register */ - u_long fsadr; /* Frame source address register */ - u_long fidr; /* Frame ID register */ - u_long ldcmd; /* Command register */ -}; - -/* - * PXA LCD info - */ -struct pxafb_info { - /* Misc registers */ - u_long reg_lccr3; - u_long reg_lccr2; - u_long reg_lccr1; - u_long reg_lccr0; - u_long fdadr0; - u_long fdadr1; - - /* DMA descriptors */ - struct pxafb_dma_descriptor *dmadesc_fblow; - struct pxafb_dma_descriptor *dmadesc_fbhigh; - struct pxafb_dma_descriptor *dmadesc_palette; - - u_long screen; /* physical address of frame buffer */ - u_long palette; /* physical address of palette memory */ - u_int palette_size; -}; - -/* - * LCD controller stucture for PXA CPU - */ -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ - u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ - u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */ - u_char vl_clor; /* Color, 0 = mono, 1 = color */ - u_char vl_tft; /* 0 = passive, 1 = TFT */ - - /* Horizontal control register. Timing from data sheet */ - ushort vl_hpw; /* Horz sync pulse width */ - u_char vl_blw; /* Wait before of line */ - u_char vl_elw; /* Wait end of line */ - - /* Vertical control register. */ - u_char vl_vpw; /* Vertical sync pulse width */ - u_char vl_bfw; /* Wait before of frame */ - u_char vl_efw; /* Wait end of frame */ - - /* PXA LCD controller params */ - struct pxafb_info pxa; -} vidinfo_t; - -#endif diff --git a/include/regmap.h b/include/regmap.h index 8216de015d..e81a3602ae 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -460,7 +460,7 @@ struct reg_field { struct regmap_field; /** - * REG_FIELD() - A convenient way to initialize a 'struct reg_feild'. + * REG_FIELD() - A convenient way to initialize a 'struct reg_field'. * * @_reg: Offset of the register within the regmap bank * @_lsb: lsb of the register field. @@ -519,9 +519,9 @@ void devm_regmap_field_free(struct udevice *dev, struct regmap_field *field); int regmap_field_write(struct regmap_field *field, unsigned int val); /** - * regmap_read() - Read a 32-bit value from a regmap + * regmap_field_read() - Read a 32-bit value from a regmap * - * @field: Regmap field to write to + * @field: Regmap field to read from * @valp: Pointer to the buffer to receive the data read from the regmap * field * diff --git a/include/spl.h b/include/spl.h index 1778e0f536..aac6648f94 100644 --- a/include/spl.h +++ b/include/spl.h @@ -380,6 +380,22 @@ void preloader_console_init(void); u32 spl_boot_device(void); /** + * spl_spi_boot_bus() - Lookup function for the SPI boot bus source. + * + * This function returns the SF bus to load from. + * If not overridden, it is weakly defined in common/spl/spl_spi.c. + */ +u32 spl_spi_boot_bus(void); + +/** + * spl_spi_boot_cs() - Lookup function for the SPI boot CS source. + * + * This function returns the SF CS to load from. + * If not overridden, it is weakly defined in common/spl/spl_spi.c. + */ +u32 spl_spi_boot_cs(void); + +/** * spl_mmc_boot_mode() - Lookup function for the mode of an MMC boot source. * @boot_device: ID of the device which the MMC driver wants to read * from. Common values are e.g. BOOT_DEVICE_MMC1, diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 2cdb3146e8..bc98093458 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -146,21 +146,6 @@ #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 -#if defined(CONFIG_MPC83xx) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR -#if defined(CONFIG_ARCH_MPC834X) -#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR -#else -#define CONFIG_SYS_FSL_USB2_ADDR 0 -#endif -#elif defined(CONFIG_MPC85xx) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR 0 -#endif - /* * Increasing TX FIFO threshold value from 2 to 4 decreases * data burst rate with which data packets are posted from the TX diff --git a/include/usb/pxa27x_udc.h b/include/usb/pxa27x_udc.h deleted file mode 100644 index 07d14821c3..0000000000 --- a/include/usb/pxa27x_udc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA27x register declarations and HCD data structures - * - * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it> - * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it> - */ - - -#ifndef __PXA270X_UDC_H__ -#define __PXA270X_UDC_H__ - -#include <asm/byteorder.h> - -/* Endpoint 0 states */ -#define EP0_IDLE 0 -#define EP0_IN_DATA 1 -#define EP0_OUT_DATA 2 -#define EP0_XFER_COMPLETE 3 - - -/* Endpoint parameters */ -#define MAX_ENDPOINTS 4 - -#define EP0_MAX_PACKET_SIZE 16 - -#define UDC_OUT_ENDPOINT 0x02 -#define UDC_IN_ENDPOINT 0x01 -#define UDC_INT_ENDPOINT 0x05 - -#endif diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 76ec2141ff..6c4fd9a6c5 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -160,6 +160,12 @@ enum dll_reset_type { PM_DLL_RESET_PULSE = 2, }; +enum ospi_mux_select_type { + PM_OSPI_MUX_SEL_DMA, + PM_OSPI_MUX_SEL_LINEAR, + PM_OSPI_MUX_GET_MODE, +}; + enum pm_query_id { PM_QID_INVALID = 0, PM_QID_CLOCK_GET_NAME = 1, @@ -427,6 +433,9 @@ enum pm_gem_config_type { #define ZYNQMP_PM_VERSION_INVALID ~0 #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) +#define PMIO_NODE_ID_BASE 0x1410801B + +#define PMIO_NODE_ID_BASE 0x1410801B /* * Return payload size diff --git a/lib/Kconfig b/lib/Kconfig index 884569f9b1..7dd777b56a 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -239,6 +239,7 @@ config GENERATE_ACPI_TABLE config SPL_TINY_MEMSET bool "Use a very small memset() in SPL" + depends on SPL help The faster memset() is the arch-specific one (if available) enabled by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get @@ -248,6 +249,7 @@ config SPL_TINY_MEMSET config TPL_TINY_MEMSET bool "Use a very small memset() in TPL" + depends on TPL help The faster memset() is the arch-specific one (if available) enabled by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get @@ -556,6 +558,7 @@ config MD5 config SPL_MD5 bool "Support MD5 algorithm in SPL" + depends on SPL help This option enables MD5 support in SPL. MD5 is an algorithm designed in 1991 that produces a 16-byte digest (or checksum) from its input @@ -642,6 +645,7 @@ config ZSTD config SPL_LZ4 bool "Enable LZ4 decompression support in SPL" + depends on SPL help This enables support for the LZ4 decompression algorithm in SPL. LZ4 is a lossless data compression algorithm that is focused on @@ -650,6 +654,7 @@ config SPL_LZ4 config SPL_LZMA bool "Enable LZMA decompression support for SPL build" + depends on SPL help This enables support for LZMA compression algorithm for SPL boot. @@ -661,6 +666,7 @@ config VPL_LZMA config SPL_LZO bool "Enable LZO decompression support in SPL" + depends on SPL help This enables support for LZO compression algorithm in the SPL. @@ -677,6 +683,7 @@ config SPL_ZLIB config SPL_ZSTD bool "Enable Zstandard decompression support in SPL" + depends on SPL select XXHASH help This enables Zstandard decompression library in the SPL. @@ -749,7 +756,7 @@ config SPL_OF_LIBFDT config SPL_OF_LIBFDT_ASSUME_MASK hex "Mask of conditions to assume for libfdt" - depends on SPL_OF_LIBFDT || FIT + depends on SPL_OF_LIBFDT || (FIT && SPL) default 0xff help Use this to change the assumptions made by libfdt in SPL about the @@ -771,7 +778,7 @@ config TPL_OF_LIBFDT config TPL_OF_LIBFDT_ASSUME_MASK hex "Mask of conditions to assume for libfdt" - depends on TPL_OF_LIBFDT || FIT + depends on TPL_OF_LIBFDT || (FIT && TPL) default 0xff help Use this to change the assumptions made by libfdt in TPL about the @@ -782,6 +789,7 @@ config TPL_OF_LIBFDT_ASSUME_MASK config VPL_OF_LIBFDT bool "Enable the FDT library for VPL" + depends on VPL default y if VPL_OF_CONTROL && !VPL_OF_PLATDATA help This enables the FDT library (libfdt). It provides functions for @@ -792,7 +800,7 @@ config VPL_OF_LIBFDT config VPL_OF_LIBFDT_ASSUME_MASK hex "Mask of conditions to assume for libfdt" - depends on VPL_OF_LIBFDT || FIT + depends on VPL_OF_LIBFDT || (FIT && VPL) default 0xff help Use this to change the assumptions made by libfdt in SPL about the diff --git a/lib/Makefile b/lib/Makefile index d9b1811f75..e3deb15287 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_EFI_LOADER) += efi_loader/ obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += efi_selftest/ obj-$(CONFIG_LZMA) += lzma/ obj-$(CONFIG_BZIP2) += bzip2/ -obj-$(CONFIG_TIZEN) += tizen/ obj-$(CONFIG_FIT) += libfdt/ obj-$(CONFIG_OF_LIVE) += of_live.o obj-$(CONFIG_CMD_DHRYSTONE) += dhry/ diff --git a/lib/crypto/Kconfig b/lib/crypto/Kconfig index 1c04a7ec5f..152eb2a9ca 100644 --- a/lib/crypto/Kconfig +++ b/lib/crypto/Kconfig @@ -28,7 +28,7 @@ config ASYMMETRIC_PUBLIC_KEY_SUBTYPE config SPL_ASYMMETRIC_PUBLIC_KEY_SUBTYPE bool "Asymmetric public-key crypto algorithm subtype within SPL" - depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE + depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE && SPL help This option provides support for asymmetric public key type handling in the SPL. If signature generation and/or verification are to be used, @@ -48,7 +48,7 @@ config RSA_PUBLIC_KEY_PARSER config SPL_RSA_PUBLIC_KEY_PARSER bool "RSA public key parser within SPL" - depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE + depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE && SPL select SPL_ASN1_DECODER select ASN1_COMPILER select SPL_OID_REGISTRY diff --git a/lib/ecdsa/Kconfig b/lib/ecdsa/Kconfig index a95c4ff581..5c3d67d814 100644 --- a/lib/ecdsa/Kconfig +++ b/lib/ecdsa/Kconfig @@ -17,6 +17,7 @@ config ECDSA_VERIFY config SPL_ECDSA_VERIFY bool "Enable ECDSA verification support in SPL" + depends on SPL help Allow ECDSA signatures to be recognized and verified in SPL. diff --git a/lib/hashtable.c b/lib/hashtable.c index ff5ff72639..90c8465611 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -35,13 +35,6 @@ # include <linux/ctype.h> #endif -#ifndef CONFIG_ENV_MIN_ENTRIES /* minimum number of entries */ -#define CONFIG_ENV_MIN_ENTRIES 64 -#endif -#ifndef CONFIG_ENV_MAX_ENTRIES /* maximum number of entries */ -#define CONFIG_ENV_MAX_ENTRIES 512 -#endif - #define USED_FREE 0 #define USED_DELETED -1 diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig index b773f17c26..9033384e60 100644 --- a/lib/rsa/Kconfig +++ b/lib/rsa/Kconfig @@ -18,6 +18,7 @@ if RSA config SPL_RSA bool "Use RSA Library within SPL" + depends on SPL config SPL_RSA_VERIFY bool diff --git a/lib/tizen/Makefile b/lib/tizen/Makefile deleted file mode 100644 index 3651ea21fb..0000000000 --- a/lib/tizen/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2012 Samsung Electronics -# Donghwa Lee <dh09.lee@samsung.com> - -obj-$(CONFIG_TIZEN) += tizen.o diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c deleted file mode 100644 index 916b259756..0000000000 --- a/lib/tizen/tizen.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee <dh09.lee@samsung.com> - */ - -#include <common.h> -#include <lcd.h> -#include <libtizen.h> - -#include "tizen_logo_16bpp.h" -#include "tizen_logo_16bpp_gzip.h" - -#ifdef CONFIG_LCD -void get_tizen_logo_info(vidinfo_t *vid) -{ - switch (vid->vl_bpix) { - case 4: - vid->logo_width = TIZEN_LOGO_16BPP_WIDTH; - vid->logo_height = TIZEN_LOGO_16BPP_HEIGHT; - vid->logo_x_offset = TIZEN_LOGO_16BPP_X_OFFSET; - vid->logo_y_offset = TIZEN_LOGO_16BPP_Y_OFFSET; -#if defined(CONFIG_VIDEO_BMP_GZIP) - vid->logo_addr = (ulong)tizen_logo_16bpp_gzip; -#else - vid->logo_addr = (ulong)tizen_logo_16bpp; -#endif - break; - default: - vid->logo_addr = 0; - break; - } -} -#endif diff --git a/lib/tizen/tizen_logo_16bpp.h b/lib/tizen/tizen_logo_16bpp.h deleted file mode 100644 index 12e86269c4..0000000000 --- a/lib/tizen/tizen_logo_16bpp.h +++ /dev/null @@ -1,7934 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Samsung Electronics - * Przemyslaw Marczak <p.marczak@samsung.com> - */ - -#ifndef __TIZEN_LOGO_16BPP__ -#define __TIZEN_LOGO_16BPP__ - -#define TIZEN_LOGO_16BPP_WIDTH 452 -#define TIZEN_LOGO_16BPP_HEIGHT 140 - -/* Center align offsets for word "TIZEN" */ -#define TIZEN_LOGO_16BPP_X_OFFSET (16) -#define TIZEN_LOGO_16BPP_Y_OFFSET (-20) - -/* Format: BMP RGB565 16BPP 452x140 */ -unsigned char tizen_logo_16bpp[] = { -0x42,0x4d,0xa6,0xee,0x01,0x00,0x00,0x00,0x00,0x00,0x46,0x00,0x00,0x00,0x38,0x00, -0x00,0x00,0xc4,0x01,0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x10,0x00,0x03,0x00, -0x00,0x00,0x60,0xee,0x01,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x00,0x00,0xe0,0x07,0x00,0x00,0x1f,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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--- a/lib/tizen/tizen_logo_16bpp_gzip.h +++ /dev/null @@ -1,647 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Samsung Electronics - * Przemyslaw Marczak <p.marczak@samsung.com> - */ - -#ifndef __TIZEN_LOGO_16BPP_GZIP__ -#define __TIZEN_LOGO_16BPP_GZIP__ - -/* Format: GZIP: BMP RGB565 16BPP 452x140 */ -unsigned char tizen_logo_16bpp_gzip[] = { -0x1f,0x8b,0x08,0x08,0xd9,0x76,0x29,0x53,0x00,0x03,0x74,0x69,0x7a,0x65,0x6e,0x5f, -0x6c,0x6f,0x67,0x6f,0x2e,0x62,0x6d,0x70,0x00,0xed,0x9d,0x6f,0x6c,0x1b,0x67,0x7e, -0xe7,0xa9,0x4d,0x80,0x65,0xbb,0x2e,0x56,0xb1,0xd8,0x25,0xcf,0x0a,0x70,0x52,0xa4, -0x2d,0xc2,0x5a,0x39,0x58,0x35,0xf7,0x42,0x35,0x7a,0x63,0xd5,0x6a,0x1b,0x9d,0x5c, -0xd4,0x0a,0x85,0xca,0xde,0x35,0x70,0x1b,0xc7,0x29,0xbc,0xaa,0xbb,0x50,0x14,0x0a, -0xd6,0x79,0xdf,0x9c,0x2b,0x07,0x88,0xa1,0xb8,0x88,0x4a,0x11,0x2b,0x83,0x7a,0x71, -0xc9,0xd2,0x6e,0x1d,0x4c,0x76,0xa1,0x60,0x28,0x44,0xc5,0xe8,0x8d,0x6b,0xba,0xbd, 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-0x43,0x17,0x12,0xda,0x37,0x7a,0x6b,0xf6,0x8b,0xc5,0xe8,0x81,0x95,0xe3,0x8c,0xc3, -0xc7,0xa9,0x8f,0x2d,0x19,0x11,0x8f,0x85,0x3f,0xeb,0x79,0x63,0x30,0x3c,0xf2,0xe0, -0xf4,0xdf,0x4e,0x8c,0xff,0xc6,0x89,0x43,0x07,0x0e,0xfd,0x73,0x73,0x0e,0x56,0x48, -0x68,0x9f,0xea,0xfc,0xc4,0xe4,0x2b,0xe5,0x27,0xe6,0x87,0x77,0xc7,0xc9,0x28,0xf0, -0x47,0xc6,0xd8,0x53,0x21,0x21,0xa1,0x46,0x69,0x34,0xfe,0xff,0xfe,0x4b,0xf9,0x89, -0xa9,0x04,0xa9,0x1f,0x3e,0x72,0xf0,0x43,0x21,0x21,0xa1,0xfa,0xea,0x58,0x78,0xe2, -0xa8,0xfa,0x8d,0xe4,0xc0,0xc6,0x38,0x99,0x8f,0xf1,0x58,0xf8,0xa1,0x90,0x50,0xc3, -0xf5,0xf3,0x5f,0x57,0xbb,0x62,0xfd,0x2b,0x7a,0x1e,0xb7,0xc7,0xc2,0x0f,0x85,0x84, -0x9a,0xa2,0x37,0x9f,0x52,0xfb,0xa2,0x4f,0xcf,0x0f,0x3f,0x4a,0x61,0x12,0xbb,0x27, -0xaf,0x09,0x0e,0x85,0x84,0x1a,0xae,0x9f,0x3d,0x13,0x7b,0x7a,0x3e,0xb1,0x4b,0x38, -0x3c,0xf3,0x96,0x18,0x21,0x23,0x24,0xd4,0x04,0x1d,0xec,0x3e,0x35,0xb0,0x3b,0x4e, -0xfc,0x50,0x70,0x28,0x24,0xd4,0x1c,0xfd,0xdd,0xa1,0xdd,0xf1,0xee,0x49,0x94,0x41, -0xa3,0xfb,0xcc,0x1f,0x09,0x0e,0x85,0x84,0x9a,0xa4,0x0b,0x87,0x76,0x53,0x28,0xa3, -0x54,0xf7,0x99,0xc3,0x82,0x43,0x21,0xa1,0xa6,0xe9,0x0f,0x7f,0xe9,0xe2,0xf8,0xf0, -0x99,0xa7,0x05,0x87,0x42,0x42,0x4d,0x55,0x47,0x68,0xf6,0xe8,0xb0,0xe0,0x50,0x48, -0xa8,0xed,0xf5,0xff,0x01,0xd1,0x0a,0xff,0xc9,0xa6,0xee,0x01,0x00}; -#endif diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index c1d32f5879..1cfb8115e3 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -253,7 +253,7 @@ endif INPUTS-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).sym -ifdef CONFIG_SAMSUNG +ifneq ($(CONFIG_ARCH_EXYNOS)$(CONFIG_ARCH_S5PC1XX),) INPUTS-y += $(obj)/$(BOARD)-spl.bin endif @@ -367,8 +367,8 @@ $(platdata-hdr) $(u-boot-spl-platdata_c) &: $(obj)/$(SPL_BIN).dtb @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata) $(call if_changed,dtoc) -ifdef CONFIG_SAMSUNG -ifdef CONFIG_VAR_SIZE_SPL +ifneq ($(CONFIG_ARCH_EXYNOS)$(CONFIG_ARCH_S5PC1XX),) +ifeq ($(CONFIG_EXYNOS5420),y) VAR_SIZE_PARAM = --vs else VAR_SIZE_PARAM = diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 726973b26e..0a2b8179d4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,18 +1,6 @@ CONFIG_ARM_GIC_BASE_ADDRESS CONFIG_AUTO_ZRELADDR CONFIG_BOARDDIR -CONFIG_BOOTSCRIPT_ADDR -CONFIG_BOOTSCRIPT_COPY_RAM -CONFIG_BOOTSCRIPT_HDR_ADDR -CONFIG_BS_ADDR_DEVICE -CONFIG_BS_ADDR_RAM -CONFIG_BS_COPY_CMD -CONFIG_BS_COPY_ENV -CONFIG_BS_HDR_ADDR_DEVICE -CONFIG_BS_HDR_ADDR_RAM -CONFIG_BS_HDR_SIZE -CONFIG_BS_SIZE -CONFIG_CHAIN_BOOT_CMD CONFIG_DEFAULT CONFIG_DFU_ALT CONFIG_DFU_ALT_BOOT_EMMC @@ -24,30 +12,9 @@ CONFIG_DM9000_BYTE_SWAPPED CONFIG_DM9000_DEBUG CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT -CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR -CONFIG_DSP_CLUSTER_START -CONFIG_DWC_AHSATA_BASE_ADDR -CONFIG_DWC_AHSATA_PORT_ID -CONFIG_DW_ALTDESCRIPTOR -CONFIG_DW_GMAC_DEFAULT_DMA_PBL -CONFIG_DW_WDT_BASE CONFIG_DW_WDT_CLOCK_KHZ -CONFIG_E1000_NO_NVM -CONFIG_EFLASH_PROTSECTORS -CONFIG_EHCI_DESC_BIG_ENDIAN -CONFIG_EHCI_HCD_INIT_AFTER_RESET -CONFIG_EHCI_MMIO_BIG_ENDIAN -CONFIG_EHCI_MXS_PORT0 -CONFIG_EHCI_MXS_PORT1 -CONFIG_EMU -CONFIG_ENABLE_36BIT_PHYS -CONFIG_ENABLE_MMU CONFIG_ENV_FLAGS_LIST_STATIC CONFIG_ENV_IS_EMBEDDED -CONFIG_ENV_MAX_ENTRIES -CONFIG_ENV_MIN_ENTRIES -CONFIG_ENV_RANGE -CONFIG_ENV_REFLASH CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS CONFIG_ENV_SETTINGS_NAND_V1 CONFIG_ENV_SETTINGS_NAND_V2 @@ -55,32 +22,9 @@ CONFIG_ENV_SETTINGS_V1 CONFIG_ENV_SETTINGS_V2 CONFIG_ENV_SROM_BANK CONFIG_ENV_TOTAL_SIZE -CONFIG_ENV_VERSION -CONFIG_ESBC_ADDR_64BIT -CONFIG_ESBC_HDR_LS -CONFIG_ESDHC_DETECT_QUIRK -CONFIG_ESDHC_HC_BLK_ADDR -CONFIG_ESPRESSO7420 CONFIG_ET1100_BASE CONFIG_ETHBASE -CONFIG_EXTRA_CLOCK -CONFIG_EXTRA_ENV CONFIG_EXTRA_ENV_SETTINGS -CONFIG_EXTRA_ENV_SETTINGS_COMMON -CONFIG_EXYNOS4 -CONFIG_EXYNOS4210 -CONFIG_EXYNOS5 -CONFIG_EXYNOS5250 -CONFIG_EXYNOS5420 -CONFIG_EXYNOS5_DT -CONFIG_EXYNOS_ACE_SHA -CONFIG_EXYNOS_DP -CONFIG_EXYNOS_FB -CONFIG_EXYNOS_MIPI_DSIM -CONFIG_EXYNOS_RELOCATE_CODE_BASE -CONFIG_EXYNOS_SPL -CONFIG_EXYNOS_TMU -CONFIG_FACTORYSET CONFIG_FB_ADDR CONFIG_FDTADDR CONFIG_FDTFILE @@ -95,15 +39,12 @@ CONFIG_FLASH_SHOW_PROGRESS CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FM_PLAT_CLK_DIV -CONFIG_FPGA_COUNT -CONFIG_FPGA_STRATIX_V CONFIG_FSL_CADMUS CONFIG_FSL_CORENET CONFIG_FSL_CPLD CONFIG_FSL_DEVICE_DISABLE CONFIG_FSL_DSPI1 CONFIG_FSL_ESDHC_PIN_MUX -CONFIG_FSL_FIXED_MMC_LOCATION CONFIG_FSL_FM_10GEC_REGULAR_NOTATION CONFIG_FSL_IIM CONFIG_FSL_ISBC_KEY_EXT @@ -115,7 +56,6 @@ CONFIG_FSL_PMIC_BUS CONFIG_FSL_PMIC_CLK CONFIG_FSL_PMIC_CS CONFIG_FSL_PMIC_MODE -CONFIG_FSL_SATA_V2 CONFIG_FSL_SDHC_V2_3 CONFIG_FSL_SERDES CONFIG_FSL_SERDES1 @@ -131,10 +71,7 @@ CONFIG_G_DNL_THOR_PRODUCT_NUM CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_UMS_VENDOR_NUM -CONFIG_HAS_FSL_DR_USB -CONFIG_HAS_FSL_MPH_USB CONFIG_HDMI_ENCODER_I2C_ADDR -CONFIG_HETROGENOUS_CLUSTERS CONFIG_HIDE_LOGO_VERSION CONFIG_HIKEY_GPIO CONFIG_HOSTNAME @@ -291,7 +228,6 @@ CONFIG_I2C_MVTWSI_BASE0 CONFIG_I2C_MVTWSI_BASE1 CONFIG_I2C_RTC_ADDR CONFIG_ICS307_REFCLK_HZ -CONFIG_IDE_PREINIT CONFIG_IMX CONFIG_IMX6_PWM_PER_CLK CONFIG_IMX_HDMI @@ -306,10 +242,6 @@ CONFIG_IRAM_BASE CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_IRAM_TOP -CONFIG_KEY_REVOCATION -CONFIG_KIRKWOOD_EGIGA_INIT -CONFIG_KIRKWOOD_PCIE_INIT -CONFIG_KIRKWOOD_RGMII_PAD_1V8 CONFIG_KM_BOARD_EXTRA_ENV CONFIG_KM_DEF_ARCH CONFIG_KM_DEF_BOOT_ARGS_CPU @@ -321,7 +253,6 @@ CONFIG_KM_DEF_ENV_CONSTANTS CONFIG_KM_DEF_ENV_CPU CONFIG_KM_DEF_ENV_FLASH_BOOT CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI -CONFIG_KM_DISABLE_PCIE CONFIG_KM_ECC_MODE CONFIG_KM_NEW_ENV CONFIG_KM_ROOTFSSIZE @@ -342,8 +273,6 @@ CONFIG_KSNET_SERDES_SGMII2_BASE CONFIG_KSNET_SERDES_SGMII_BASE CONFIG_L1_INIT_RAM CONFIG_L2_CACHE -CONFIG_LAYERSCAPE_NS_ACCESS -CONFIG_LBA48 CONFIG_LCD_ALIGNMENT CONFIG_LCD_MENU CONFIG_LD9040 @@ -418,35 +347,11 @@ CONFIG_NORBOOT CONFIG_NS16550_MIN_FUNCTIONS CONFIG_NUM_DSP_CPUS CONFIG_ODROID_REV_AIN -CONFIG_ORIGEN CONFIG_OTHBOOTARGS CONFIG_OVERWRITE_ETHADDR_ONCE -CONFIG_PALMAS_POWER CONFIG_PCA953X -CONFIG_PCI1 -CONFIG_PCI2 -CONFIG_PCIE1 -CONFIG_PCIE2 -CONFIG_PCIE3 -CONFIG_PCIE4 -CONFIG_PCIE_IMX CONFIG_PCIE_IMX_PERST_GPIO CONFIG_PCIE_IMX_POWER_GPIO -CONFIG_PCI_CLK_FREQ -CONFIG_PCI_CONFIG_HOST_BRIDGE -CONFIG_PCI_GT64120 -CONFIG_PCI_IO_BUS -CONFIG_PCI_IO_PHYS -CONFIG_PCI_IO_SIZE -CONFIG_PCI_MEM_BUS -CONFIG_PCI_MEM_PHYS -CONFIG_PCI_MEM_SIZE -CONFIG_PCI_MSC01 -CONFIG_PCI_OHCI -CONFIG_PCI_PREF_BUS -CONFIG_PCI_PREF_PHYS -CONFIG_PCI_PREF_SIZE -CONFIG_PCI_SCAN_SHOW CONFIG_PEN_ADDR_BIG_ENDIAN CONFIG_PHY_BASE_ADR CONFIG_PHY_ET1011C_TX_CLK_FIX @@ -456,8 +361,6 @@ CONFIG_PHY_IRAM_BASE CONFIG_PL011_CLOCK CONFIG_PL01x_PORTS CONFIG_PM -CONFIG_PMC_BR_PRELIM -CONFIG_PMC_OR_PRELIM CONFIG_PME_PLAT_CLK_DIV CONFIG_POST CONFIG_POSTBOOTMENU @@ -477,20 +380,15 @@ CONFIG_POWER_TPS62362 CONFIG_POWER_TPS65090_EC CONFIG_POWER_TPS65218 CONFIG_POWER_TPS65910 -CONFIG_PPC_CLUSTER_START CONFIG_PPC_SPINTABLE_COMPATIBLE CONFIG_PRAM CONFIG_PSRAM_SCFG -CONFIG_PWM -CONFIG_PXA_VGA CONFIG_QBMAN_CLK_DIV -CONFIG_RAMBOOT_NAND CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RAMDISK_ADDR CONFIG_RD_LVL CONFIG_RESET_VECTOR_ADDRESS -CONFIG_RESTORE_FLASH CONFIG_ROCKCHIP_CHIP_TAG CONFIG_ROCKCHIP_MAX_INIT_SIZE CONFIG_ROCKCHIP_SDHCI_MAX_FREQ @@ -504,34 +402,23 @@ CONFIG_RTC_MC13XXX CONFIG_RTC_MCFRRTC CONFIG_RTC_MXS CONFIG_RTC_PT7C4338 -CONFIG_S5P -CONFIG_S5PC100 -CONFIG_S5PC110 -CONFIG_S5P_PA_SYSRAM CONFIG_SAMA5D3_LCD_BASE -CONFIG_SAMSUNG -CONFIG_SAMSUNG_ONENAND CONFIG_SANDBOX_ARCH CONFIG_SANDBOX_SDL CONFIG_SANDBOX_SPI_MAX_BUS CONFIG_SANDBOX_SPI_MAX_CS CONFIG_SAR2_REG CONFIG_SAR_REG -CONFIG_SATA1 -CONFIG_SATA2 CONFIG_SCIF_A CONFIG_SCSI_DEV_LIST CONFIG_SC_TIMER_CLK CONFIG_SDRAM_OFFSET_FOR_RT -CONFIG_SECBOOT CONFIG_SERIAL_BOOT CONFIG_SERIAL_SOFTWARE_FIFO CONFIG_SERVERIP CONFIG_SETUP_INITRD_TAG -CONFIG_SET_BOOTARGS CONFIG_SET_DFU_ALT_BUF_LEN CONFIG_SH73A0 -CONFIG_SH7751_PCI CONFIG_SH_ETHER_ALIGNE_SIZE CONFIG_SH_ETHER_BASE_ADDR CONFIG_SH_ETHER_CACHE_INVALIDATE @@ -576,9 +463,6 @@ CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE CONFIG_STACKBASE CONFIG_STANDALONE_LOAD_ADDR CONFIG_STD_DEVICES_SETTINGS -CONFIG_SYS_64BIT -CONFIG_SYS_64BIT_LBA -CONFIG_SYS_83XX_DDR_USES_CS0 CONFIG_SYS_AMASK0 CONFIG_SYS_AMASK1 CONFIG_SYS_AMASK1_FINAL @@ -592,12 +476,7 @@ CONFIG_SYS_AT91_MAIN_CLOCK CONFIG_SYS_AT91_PLLA CONFIG_SYS_AT91_PLLB CONFIG_SYS_AT91_SLOW_CLOCK -CONFIG_SYS_AUTOLOAD -CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -CONFIG_SYS_AUXCORE_BOOTDATA CONFIG_SYS_BAUDRATE_TABLE -CONFIG_SYS_BFTIC3_BASE -CONFIG_SYS_BFTIC3_SIZE CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_CENA_SIZE CONFIG_SYS_BMAN_CINH_BASE @@ -609,13 +488,8 @@ CONFIG_SYS_BMAN_NUM_PORTALS CONFIG_SYS_BMAN_SP_CENA_SIZE CONFIG_SYS_BMAN_SP_CINH_SIZE CONFIG_SYS_BMAN_SWP_ISDR_REG -CONFIG_SYS_BOOK3E_HV -CONFIG_SYS_BOOTCOUNT_BE -CONFIG_SYS_BOOTCOUNT_LE CONFIG_SYS_BOOTMAPSZ -CONFIG_SYS_BOOTM_LEN CONFIG_SYS_BOOT_BLOCK -CONFIG_SYS_BOOT_RAMDISK_HIGH CONFIG_SYS_CACHE_ACR0 CONFIG_SYS_CACHE_ACR1 CONFIG_SYS_CACHE_ACR2 @@ -630,7 +504,6 @@ CONFIG_SYS_CLK CONFIG_SYS_CLKTL_CBCDR CONFIG_SYS_CORE_SRAM CONFIG_SYS_CORE_SRAM_SIZE -CONFIG_SYS_CPC_REINIT_F CONFIG_SYS_CPLD_AMASK CONFIG_SYS_CPLD_BASE CONFIG_SYS_CPLD_BASE_PHYS @@ -642,8 +515,6 @@ CONFIG_SYS_CPLD_FTIM1 CONFIG_SYS_CPLD_FTIM2 CONFIG_SYS_CPLD_FTIM3 CONFIG_SYS_CPLD_SIZE -CONFIG_SYS_CPRI -CONFIG_SYS_CPRI_CLK CONFIG_SYS_CPUSPEED CONFIG_SYS_CPU_CLK CONFIG_SYS_CS0_BASE @@ -731,10 +602,8 @@ CONFIG_SYS_DAVINCI_I2C_SPEED2 CONFIG_SYS_DCACHE_INV CONFIG_SYS_DCSRBAR CONFIG_SYS_DCSRBAR_PHYS -CONFIG_SYS_DCSR_COP_CCP_ADDR CONFIG_SYS_DCSR_DCFG_ADDR CONFIG_SYS_DCSR_DCFG_OFFSET -CONFIG_SYS_DCU_ADDR CONFIG_SYS_DDRCDR CONFIG_SYS_DDRCDR_VALUE CONFIG_SYS_DDRUA @@ -772,7 +641,6 @@ CONFIG_SYS_DDR_MODE_2 CONFIG_SYS_DDR_MODE_2_667 CONFIG_SYS_DDR_MODE_2_800 CONFIG_SYS_DDR_MODE_CONTROL -CONFIG_SYS_DDR_RAW_TIMING CONFIG_SYS_DDR_RCW_1 CONFIG_SYS_DDR_RCW_2 CONFIG_SYS_DDR_SDRAM_BASE @@ -802,10 +670,8 @@ CONFIG_SYS_DDR_ZQ_CONTROL CONFIG_SYS_DEBUG CONFIG_SYS_DEBUG_SERVER_FW_ADDR CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DIALOG_PMIC_I2C_ADDR CONFIG_SYS_DIRECT_FLASH_TFTP -CONFIG_SYS_DISCOVER_PHY CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME @@ -820,13 +686,10 @@ CONFIG_SYS_DV_NOR_BOOT_CFG CONFIG_SYS_EEPROM_BUS_NUM CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE CONFIG_SYS_EEPROM_WREN -CONFIG_SYS_EHCI_USB1_ADDR -CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS CONFIG_SYS_ENET_BD_BASE CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_ETHOC_BASE CONFIG_SYS_ETHOC_BUFFER_ADDR -CONFIG_SYS_ETVPE_CLK CONFIG_SYS_EXCEPTION_VECTORS_HIGH CONFIG_SYS_FAST_CLK CONFIG_SYS_FDT_PAD @@ -932,19 +795,15 @@ CONFIG_SYS_FSL_CORENET_SERDES_ADDR CONFIG_SYS_FSL_CORENET_SERDES_OFFSET CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY CONFIG_SYS_FSL_CORES_PER_CLUSTER -CONFIG_SYS_FSL_CPC CONFIG_SYS_FSL_CPC_ADDR CONFIG_SYS_FSL_CPC_OFFSET CONFIG_SYS_FSL_CSU_ADDR -CONFIG_SYS_FSL_DCFG_ADDR CONFIG_SYS_FSL_DCSR_DDR2_ADDR CONFIG_SYS_FSL_DCSR_DDR3_ADDR -CONFIG_SYS_FSL_DCSR_DDR4_ADDR CONFIG_SYS_FSL_DCSR_DDR_ADDR CONFIG_SYS_FSL_DDR2_ADDR CONFIG_SYS_FSL_DDR3_ADDR CONFIG_SYS_FSL_DDR_ADDR -CONFIG_SYS_FSL_DDR_EMU CONFIG_SYS_FSL_DDR_INTLV_256B CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY @@ -986,7 +845,6 @@ CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET -CONFIG_SYS_FSL_FMAN_ADDR CONFIG_SYS_FSL_GUTS_ADDR CONFIG_SYS_FSL_IFC_BE CONFIG_SYS_FSL_IFC_LE @@ -1003,7 +861,6 @@ CONFIG_SYS_FSL_OCRAM_SIZE CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS CONFIG_SYS_FSL_PAMU_OFFSET CONFIG_SYS_FSL_PCIE_COMPAT -CONFIG_SYS_FSL_PCI_VER_3_X CONFIG_SYS_FSL_PEX_LUT_BE CONFIG_SYS_FSL_PEX_LUT_LE CONFIG_SYS_FSL_PMIC_I2C_ADDR @@ -1028,16 +885,9 @@ CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SEC_ADDR CONFIG_SYS_FSL_SEC_IDX_OFFSET -CONFIG_SYS_FSL_SEC_MON_BE -CONFIG_SYS_FSL_SEC_MON_LE CONFIG_SYS_FSL_SEC_OFFSET CONFIG_SYS_FSL_SERDES CONFIG_SYS_FSL_SERDES_ADDR -CONFIG_SYS_FSL_SFP_BE -CONFIG_SYS_FSL_SFP_LE -CONFIG_SYS_FSL_SFP_VER_3_0 -CONFIG_SYS_FSL_SFP_VER_3_2 -CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SINGLE_SOURCE_CLK CONFIG_SYS_FSL_SRDS_3 CONFIG_SYS_FSL_SRDS_4 @@ -1049,7 +899,6 @@ CONFIG_SYS_FSL_SRIO_MAX_PORTS CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM CONFIG_SYS_FSL_SRIO_OB_WIN_NUM CONFIG_SYS_FSL_SRIO_OFFSET -CONFIG_SYS_FSL_SRK_LE CONFIG_SYS_FSL_TBCLK_DIV CONFIG_SYS_FSL_TIMER_ADDR CONFIG_SYS_FSL_USB1_PHY_ENABLE @@ -1061,7 +910,6 @@ CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_FSL_WRIOP1_ADDR CONFIG_SYS_FSL_WRIOP1_MDIO1 CONFIG_SYS_FSL_WRIOP1_MDIO2 -CONFIG_SYS_GIC400_ADDR CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR @@ -1154,7 +1002,6 @@ CONFIG_SYS_LOADS_BAUD_CHANGE CONFIG_SYS_LOW CONFIG_SYS_LOWMEM_BASE CONFIG_SYS_LPAE_SDRAM_BASE -CONFIG_SYS_LS1_DDR_BLOCK1_SIZE CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS CONFIG_SYS_LS_MC_DPC_MAX_LENGTH @@ -1166,8 +1013,6 @@ CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET CONFIG_SYS_M41T11_BASE_YEAR CONFIG_SYS_MAIN_PWR_ON CONFIG_SYS_MAMR -CONFIG_SYS_MAPLE -CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_MASTER_CLOCK CONFIG_SYS_MATRIX_EBI0CSA_VAL CONFIG_SYS_MATRIX_EBICSA_VAL @@ -1182,9 +1027,7 @@ CONFIG_SYS_MCKR CONFIG_SYS_MCKR1_VAL CONFIG_SYS_MCKR2_VAL CONFIG_SYS_MCKR_CSS -CONFIG_SYS_MDCNFG_VAL CONFIG_SYS_MDIO1_OFFSET -CONFIG_SYS_MDREFR_VAL CONFIG_SYS_MEMAC_LITTLE_ENDIAN CONFIG_SYS_MEMORY_BASE CONFIG_SYS_MEMORY_SIZE @@ -1208,9 +1051,6 @@ CONFIG_SYS_MPC83xx_DMA_ADDR CONFIG_SYS_MPC83xx_DMA_OFFSET CONFIG_SYS_MPC83xx_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_OFFSET -CONFIG_SYS_MPC83xx_USB1_ADDR -CONFIG_SYS_MPC83xx_USB1_OFFSET -CONFIG_SYS_MPC85XX_NO_RESETVEC CONFIG_SYS_MPC85xx_DMA CONFIG_SYS_MPC85xx_DMA1_OFFSET CONFIG_SYS_MPC85xx_DMA2_OFFSET @@ -1353,7 +1193,6 @@ CONFIG_SYS_NUM_I2C_BUSES CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_OBIR -CONFIG_SYS_OHCI_SWAP_REG_ACCESS CONFIG_SYS_OMAP_ABE_SYSCK CONFIG_SYS_ONENAND_BASE CONFIG_SYS_ONENAND_BLOCK_SIZE @@ -1391,31 +1230,21 @@ CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCIE CONFIG_SYS_PCIE1_ADDR -CONFIG_SYS_PCIE1_BASE CONFIG_SYS_PCIE1_CFG_BASE CONFIG_SYS_PCIE1_CFG_SIZE -CONFIG_SYS_PCIE1_IO_BASE CONFIG_SYS_PCIE1_IO_PHYS -CONFIG_SYS_PCIE1_IO_SIZE CONFIG_SYS_PCIE1_IO_VIRT -CONFIG_SYS_PCIE1_MEM_BASE CONFIG_SYS_PCIE1_MEM_PHYS -CONFIG_SYS_PCIE1_MEM_SIZE CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_PHYS_ADDR CONFIG_SYS_PCIE1_PHYS_BASE CONFIG_SYS_PCIE1_VIRT_ADDR CONFIG_SYS_PCIE2_ADDR -CONFIG_SYS_PCIE2_BASE CONFIG_SYS_PCIE2_CFG_BASE CONFIG_SYS_PCIE2_CFG_SIZE -CONFIG_SYS_PCIE2_IO_BASE CONFIG_SYS_PCIE2_IO_PHYS -CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE2_IO_VIRT -CONFIG_SYS_PCIE2_MEM_BASE CONFIG_SYS_PCIE2_MEM_PHYS -CONFIG_SYS_PCIE2_MEM_SIZE CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_PHYS_ADDR CONFIG_SYS_PCIE2_PHYS_BASE @@ -1435,20 +1264,6 @@ CONFIG_SYS_PCIE4_MEM_PHYS CONFIG_SYS_PCIE4_MEM_VIRT CONFIG_SYS_PCIE4_PHYS_ADDR CONFIG_SYS_PCIE_MMAP_SIZE -CONFIG_SYS_PCI_IO_BASE -CONFIG_SYS_PCI_IO_PHYS -CONFIG_SYS_PCI_IO_SIZE -CONFIG_SYS_PCI_MAP_END -CONFIG_SYS_PCI_MAP_START -CONFIG_SYS_PCI_MEM_BASE -CONFIG_SYS_PCI_MEM_PHYS -CONFIG_SYS_PCI_MEM_SIZE -CONFIG_SYS_PCI_MMIO_BASE -CONFIG_SYS_PCI_MMIO_PHYS -CONFIG_SYS_PCI_MMIO_SIZE -CONFIG_SYS_PCI_SLV_MEM_BUS -CONFIG_SYS_PCI_SLV_MEM_LOCAL -CONFIG_SYS_PCI_SLV_MEM_SIZE CONFIG_SYS_PDCNT CONFIG_SYS_PEHLPAR CONFIG_SYS_PIOC_PDR_VAL @@ -1465,8 +1280,6 @@ CONFIG_SYS_PLL_FDR CONFIG_SYS_PLL_ODR CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_PMAN -CONFIG_SYS_PMC_BASE -CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PME_CLK CONFIG_SYS_POST_MEMORY CONFIG_SYS_POST_MEM_REGIONS @@ -1484,7 +1297,6 @@ CONFIG_SYS_QMAN_SP_CINH_SIZE CONFIG_SYS_QMAN_SWP_ISDR_REG CONFIG_SYS_QRIO_BASE CONFIG_SYS_QRIO_BASE_PHYS -CONFIG_SYS_RAMBOOT CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE @@ -1498,12 +1310,6 @@ CONFIG_SYS_RTC_BUS_NUM CONFIG_SYS_RTC_CNT CONFIG_SYS_RTC_SETUP CONFIG_SYS_SATA -CONFIG_SYS_SATA1 -CONFIG_SYS_SATA1_FLAGS -CONFIG_SYS_SATA1_OFFSET -CONFIG_SYS_SATA2 -CONFIG_SYS_SATA2_FLAGS -CONFIG_SYS_SATA2_OFFSET CONFIG_SYS_SATA_FAT_BOOT_PARTITION CONFIG_SYS_SBFHDR_DATA_OFFSET CONFIG_SYS_SBFHDR_SIZE @@ -1576,7 +1382,6 @@ CONFIG_SYS_SMC0_CYCLE0_VAL CONFIG_SYS_SMC0_MODE0_VAL CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL -CONFIG_SYS_SPD_BUS_NUM CONFIG_SYS_SPI_ARGS_OFFS CONFIG_SYS_SPI_ARGS_SIZE CONFIG_SYS_SPI_BASE @@ -1613,8 +1418,6 @@ CONFIG_SYS_TIMER_COUNTS_DOWN CONFIG_SYS_TIMER_RATE CONFIG_SYS_TMPVIRT CONFIG_SYS_TSEC1_OFFSET -CONFIG_SYS_TSEC2_OFFSET -CONFIG_SYS_TSEC3_OFFSET CONFIG_SYS_TX_ETH_BUFFER CONFIG_SYS_UART2_ALT3_GPIO CONFIG_SYS_UART_PORT @@ -1628,15 +1431,7 @@ CONFIG_SYS_UEC2_PHY_ADDR CONFIG_SYS_UEC2_RX_CLK CONFIG_SYS_UEC2_TX_CLK CONFIG_SYS_UEC2_UCC_NUM -CONFIG_SYS_ULB_CLK -CONFIG_SYS_UNIFY_CACHE -CONFIG_SYS_USB_FAT_BOOT_PARTITION -CONFIG_SYS_USB_OHCI_BOARD_INIT -CONFIG_SYS_USB_OHCI_CPU_INIT -CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS CONFIG_SYS_USB_OHCI_REGS_BASE -CONFIG_SYS_USB_OHCI_SLOT_NAME -CONFIG_SYS_USE_NAND CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT @@ -1668,7 +1463,6 @@ CONFIG_TEGRA_BOARD_STRING CONFIG_TEGRA_CLOCK_SCALING CONFIG_TEGRA_ENABLE_UARTA CONFIG_TEGRA_ENABLE_UARTD -CONFIG_TEGRA_GPU CONFIG_TEGRA_LP0 CONFIG_TEGRA_PMU CONFIG_TEGRA_SLINK_CTRLS @@ -1680,12 +1474,9 @@ CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 CONFIG_TESTPIN_MASK CONFIG_TESTPIN_REG CONFIG_THOR_RESET_OFF -CONFIG_THUNDERX -CONFIG_TIZEN CONFIG_TMU_TIMER CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPS6586X_POWER -CONFIG_TRATS CONFIG_TSEC CONFIG_TSEC1 CONFIG_TSEC1_NAME @@ -1716,24 +1507,13 @@ CONFIG_USBD_PRODUCTID_GSERIAL CONFIG_USBD_PRODUCT_NAME CONFIG_USBD_VENDORID CONFIG_USBNET_DEV_ADDR -CONFIG_USB_ATMEL -CONFIG_USB_ATMEL_CLK_SEL_PLLB -CONFIG_USB_ATMEL_CLK_SEL_UPLL CONFIG_USB_BOOTING CONFIG_USB_DEVICE -CONFIG_USB_EHCI_EXYNOS -CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_EXT2_BOOT CONFIG_USB_FAT_BOOT CONFIG_USB_GADGET_AT91 -CONFIG_USB_GADGET_DWC2_OTG_PHY CONFIG_USB_ISP1301_I2C_ADDR -CONFIG_USB_MAX_CONTROLLER_COUNT -CONFIG_USB_OHCI_LPC32XX -CONFIG_USB_OHCI_NEW CONFIG_USB_TTY -CONFIG_USB_XHCI_EXYNOS -CONFIG_USE_ONENAND_BOARD_INIT CONFIG_U_BOOT_HDR_SIZE CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM @@ -1748,4 +1528,3 @@ CONFIG_X86EMU_RAW_IO CONFIG_X86_MRC_ADDR CONFIG_X86_REFCODE_ADDR CONFIG_X86_REFCODE_RUN_ADDR -CONFIG_XTFPGA diff --git a/test/Kconfig b/test/Kconfig index 7f3447ae5a..9b283a57ba 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -8,6 +8,7 @@ menuconfig UNIT_TEST config SPL_UNIT_TEST bool "Unit tests in SPL" + depends on SPL # We need to be able to unbind devices for tests to work select SPL_DM_DEVICE_REMOVE help diff --git a/test/dm/Makefile b/test/dm/Makefile index caea52f4e2..52fe178a82 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -18,9 +18,13 @@ obj-$(CONFIG_UT_DM) += core.o obj-$(CONFIG_UT_DM) += read.o obj-$(CONFIG_UT_DM) += phys2bus.o ifneq ($(CONFIG_SANDBOX),) -obj-$(CONFIG_ACPIGEN) += acpi.o -obj-$(CONFIG_ACPIGEN) += acpigen.o -obj-$(CONFIG_ACPIGEN) += acpi_dp.o +ifeq ($(CONFIG_ACPIGEN),y) +obj-y += acpi.o +obj-y += acpigen.o +obj-y += acpi_dp.o +obj-(CONFIG_DM_GPIO) += gpio.o +obj-y += irq.o +endif obj-$(CONFIG_ADC) += adc.o obj-$(CONFIG_SOUND) += audio.o obj-$(CONFIG_AXI) += axi.o @@ -43,11 +47,9 @@ ifneq ($(CONFIG_EFI_PARTITION),) obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o endif obj-$(CONFIG_FIRMWARE) += firmware.o -obj-$(CONFIG_DM_GPIO) += gpio.o obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_SOUND) += i2s.o -obj-y += irq.o obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o obj-$(CONFIG_IOMMU) += iommu.o obj-$(CONFIG_LED) += led.o diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 31afef6f3b..908a162202 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1713,6 +1713,67 @@ static int check_device_config(int dev) return rc; } +static int find_nvmem_device(void) +{ + const char *path = "/sys/bus/nvmem/devices"; + struct dirent *dent; + char *nvmem = NULL; + char comp[256]; + char buf[32]; + int bytes; + DIR *dir; + + dir = opendir(path); + if (!dir) { + return -EIO; + } + + while (!nvmem && (dent = readdir(dir))) { + FILE *fp; + + if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, "..")) { + continue; + } + + bytes = snprintf(comp, sizeof(comp), "%s/%s/of_node/compatible", path, dent->d_name); + if (bytes < 0 || bytes == sizeof(comp)) { + continue; + } + + fp = fopen(comp, "r"); + if (!fp) { + continue; + } + + fread(buf, sizeof(buf), 1, fp); + + if (!strcmp(buf, "u-boot,env")) { + bytes = asprintf(&nvmem, "%s/%s/nvmem", path, dent->d_name); + if (bytes < 0) { + nvmem = NULL; + } + } + + fclose(fp); + } + + closedir(dir); + + if (nvmem) { + struct stat s; + + stat(nvmem, &s); + + DEVNAME(0) = nvmem; + DEVOFFSET(0) = 0; + ENVSIZE(0) = s.st_size; + + return 0; + } + + return -ENOENT; +} + static int parse_config(struct env_opts *opts) { int rc; @@ -1723,9 +1784,12 @@ static int parse_config(struct env_opts *opts) #if defined(CONFIG_FILE) /* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */ if (get_config(opts->config_file)) { - fprintf(stderr, "Cannot parse config file '%s': %m\n", - opts->config_file); - return -1; + if (find_nvmem_device()) { + fprintf(stderr, "Cannot parse config file '%s': %m\n", + opts->config_file); + fprintf(stderr, "Failed to find NVMEM device\n"); + return -1; + } } #else DEVNAME(0) = DEVICE1_NAME; |