diff options
54 files changed, 3676 insertions, 150 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ad4d2357bb..7c806eee9e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -108,6 +108,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-khadas-edge.dtb \ + rk3399-khadas-edge-captain.dtb \ + rk3399-khadas-edge-v.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-nanopi-neo4.dtb \ diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi new file mode 100644 index 0000000000..58ebf52b4b --- /dev/null +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#include "rk3328-sdram-ddr3-666.dtsi" + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index b077436cbc..dbcce6ac64 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -4,6 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include "rk3328-sdram-lpddr3-1600.dtsi" + / { aliases { mmc0 = &emmc; @@ -25,10 +27,8 @@ &emmc { u-boot,dm-pre-reloc; - fifo-mode; }; &sdmmc { u-boot,dm-pre-reloc; - fifo-mode; }; diff --git a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi new file mode 100644 index 0000000000..d99e7e0352 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xC + 0x3 + 0x1 + 0x0 + 0x0 + 0x10 + 0x10 + 0 + + 0x9028b189 + 0x00000000 + 0x00000021 + 0x00000482 + 0x00000015 + 0x00000222 + 0x000000ff + + 333 + 3 + 0 + + 0x00000000 + 0x43041001 + 0x00000064 + 0x0028003b + 0x000000d0 + 0x00020053 + 0x000000d4 + 0x00020000 + 0x000000d8 + 0x00000100 + 0x000000dc + 0x03200000 + 0x000000e0 + 0x00000000 + 0x000000e4 + 0x00090000 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x07090b06 + 0x00000104 + 0x00050209 + 0x00000108 + 0x03030407 + 0x0000010c + 0x00202006 + 0x00000110 + 0x03020204 + 0x00000114 + 0x03030202 + 0x00000120 + 0x00000903 + 0x00000180 + 0x00800020 + 0x00000184 + 0x00000000 + 0x00000190 + 0x07010001 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x06000604 + 0x00000244 + 0x00000201 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000a + 0x00000028 + 0x00000006 + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000005 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi new file mode 100644 index 0000000000..cc0011cf7b --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi @@ -0,0 +1,215 @@ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xC + 0x3 + 0x1 + 0x0 + 0x0 + 0x10 + 0x10 + 0 + + 0x98899459 + 0x00000000 + 0x0000002e + 0x00000544 + 0x00000015 + 0x00000432 + 0x000000ff + + 800 + 6 + 1 + + 0x00000000 + 0x43041008 + 0x00000064 + 0x00300054 + 0x000000d0 + 0x00500002 + 0x000000d4 + 0x00010000 + 0x000000d8 + 0x00000e03 + 0x000000dc + 0x0043001a + 0x000000e0 + 0x00010000 + 0x000000e4 + 0x000e0005 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x0b141b11 + 0x00000104 + 0x0003031a + 0x00000108 + 0x03060809 + 0x0000010c + 0x00606000 + 0x00000110 + 0x08020409 + 0x00000114 + 0x01010606 + 0x00000118 + 0x02020004 + 0x00000120 + 0x00000404 + 0x00000138 + 0x00000058 + 0x00000180 + 0x00900024 + 0x00000184 + 0x01400000 + 0x00000190 + 0x07050002 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x0a020b28 + 0x00000244 + 0x00000101 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000b + 0x00000028 + 0x0000000c + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000006 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi new file mode 100644 index 0000000000..62d809e833 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xC + 0x3 + 0x1 + 0x0 + 0x0 + 0x10 + 0x10 + 0 + + 0x0c48a18a + 0x00000000 + 0x00000021 + 0x00000482 + 0x00000015 + 0x0000021a + 0x000000ff + + 333 + 6 + 0 + + 0x00000000 + 0xc3040008 + 0x00000064 + 0x00140023 + 0x000000d0 + 0x00220002 + 0x000000d4 + 0x00010000 + 0x000000d8 + 0x00000703 + 0x000000dc + 0x00830004 + 0x000000e0 + 0x00010000 + 0x000000e4 + 0x00070003 + 0x00000100 + 0x06090b07 + 0x00000104 + 0x0002020b + 0x00000108 + 0x02030506 + 0x0000010c + 0x00505000 + 0x00000110 + 0x03020204 + 0x00000114 + 0x01010303 + 0x00000118 + 0x02020003 + 0x00000120 + 0x00000303 + 0x00000138 + 0x00000025 + 0x00000180 + 0x003c000f + 0x00000184 + 0x00900000 + 0x00000190 + 0x07020000 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x0900090c + 0x00000244 + 0x00000101 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000b + 0x00000028 + 0x00000006 + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000003 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 2d80addbb0..a080ae8d69 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -351,10 +351,15 @@ status = "disabled"; }; - dmc: dmc@ff400000 { + dmc: dmc { u-boot,dm-pre-reloc; - compatible = "rockchip,rk3328-dmc", "syscon"; - reg = <0x0 0xff400000 0x0 0x1000>; + compatible = "rockchip,rk3328-dmc"; + reg = <0x0 0xff400000 0x0 0x1000 + 0x0 0xff780000 0x0 0x3000 + 0x0 0xff100000 0x0 0x1000 + 0x0 0xff440000 0x0 0x1000 + 0x0 0xff720000 0x0 0x1000 + 0x0 0xff798000 0x0 0x1000>; }; cru: clock-controller@ff440000 { diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi index eab86bdb30..f3f7aa7c45 100644 --- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi @@ -3,4 +3,11 @@ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> */ +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = &sdhci, &sdmmc; + }; +}; diff --git a/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi new file mode 100644 index 0000000000..ca1bbffb50 --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Nick Xie <nick@khadas.com> + */ + +#include "rk3399-khadas-edge-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-khadas-edge-captain.dts b/arch/arm/dts/rk3399-khadas-edge-captain.dts new file mode 100644 index 0000000000..8302e51def --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge-captain.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge-Captain"; + compatible = "khadas,edge-captain", "rockchip,rk3399"; +}; + +&gmac { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi new file mode 100644 index 0000000000..35b9fdda77 --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Nick Xie <nick@khadas.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; diff --git a/arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi new file mode 100644 index 0000000000..ca1bbffb50 --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Nick Xie <nick@khadas.com> + */ + +#include "rk3399-khadas-edge-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-khadas-edge-v.dts b/arch/arm/dts/rk3399-khadas-edge-v.dts new file mode 100644 index 0000000000..f5dcb99dc3 --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge-v.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge-V"; + compatible = "khadas,edge-v", "rockchip,rk3399"; +}; + +&gmac { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-khadas-edge.dts b/arch/arm/dts/rk3399-khadas-edge.dts new file mode 100644 index 0000000000..31616e7ad8 --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge"; + compatible = "khadas,edge", "rockchip,rk3399"; +}; diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi new file mode 100644 index 0000000000..4944d78a0a --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge.dtsi @@ -0,0 +1,804 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vsys_5v0>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vsys_3v3>; + }; + + vsys: vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: vsys-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys>; + }; + + vsys_5v0: vsys-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vsys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <18000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>; + + sys-led { + label = "sys_led"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + user-led { + label = "user_led"; + default-state = "off"; + gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 150 200 255>; + #cooling-cells = <2>; + fan-supply = <&vsys_5v0>; + pwms = <&pwm0 0 40000 0>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_thermal { + trips { + gpu_warm: gpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + gpu_hot: gpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&gpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map2 { + trip = <&gpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vsys_3v3>; + vcc2-supply = <&vsys_3v3>; + vcc3-supply = <&vsys_3v3>; + vcc4-supply = <&vsys_3v3>; + vcc6-supply = <&vsys_3v3>; + vcc7-supply = <&vsys_3v3>; + vcc8-supply = <&vsys_3v3>; + vcc9-supply = <&vsys_3v3>; + vcc10-supply = <&vsys_3v3>; + vcc11-supply = <&vsys_3v3>; + vcc12-supply = <&vsys_3v3>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_apio2: LDO_REG1 { + regulator-name = "vcc1v8_apio2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_vldo2: LDO_REG2 { + regulator-name = "vcc_vldo2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-name = "vcc1v8_pmupll"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_vldo5: LDO_REG5 { + regulator-name = "vcc_vldo5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc1v8_codec: LDO_REG7 { + regulator-name = "vcc1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_apio2>; + audio-supply = <&vcc1v8_codec>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sys_led_gpio: sys_led-gpio { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led_gpio: user_led-gpio { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdio0 { + /* WiFi & BT combo module Ampak AP6356S */ + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + vqmmc-supply = <&vcc1v8_s3>; + vmmc-supply = <&vccio_sd>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vsys_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi index 5256f6d3f2..4850debdf0 100644 --- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -3,4 +3,11 @@ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> */ +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr3-2GB-1600.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = &sdhci, &sdmmc; + }; +}; diff --git a/arch/arm/dts/tegra124-apalis.dts b/arch/arm/dts/tegra124-apalis.dts index a962c0a2f0..08184ab3ac 100644 --- a/arch/arm/dts/tegra124-apalis.dts +++ b/arch/arm/dts/tegra124-apalis.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 Toradex AG + * Copyright 2016-2019 Toradex AG * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -230,19 +230,21 @@ }; /* Apalis GPIO */ - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; }; pex_l0_rst_n_pdd1 { nvidia,pins = "pex_l0_rst_n_pdd1"; @@ -333,40 +335,40 @@ nvidia,open-drain = <TEGRA_PIN_ENABLE>; }; - /* Apalis I2C2 (DDC) */ - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; + /* Apalis I2C3 (CAM) */ + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; }; - /* Apalis I2C3 (CAM) */ - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; + /* Apalis I2C4 (DDC) */ + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; }; /* Apalis MMC1 */ @@ -470,12 +472,12 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; - /* PWM3 active on pu6 being Apalis BKL1_PWM */ + /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ ph3 { nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; @@ -736,8 +738,8 @@ }; /* Apalis USBH_EN */ - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; @@ -755,8 +757,8 @@ }; /* Apalis USBO1_EN */ - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; @@ -1501,10 +1503,14 @@ nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; - pv0 { /* NC */ + /* + * PCB Version Indication: V1.2 and later have GPIO_PV0 + * wired to GND, was NC before + */ + pv0 { nvidia,pins = "pv0"; nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; @@ -1630,13 +1636,7 @@ }; }; - /* - * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) - */ - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <10000>; - }; + /* GEN2_I2C: unused */ /* * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor @@ -1647,7 +1647,14 @@ clock-frequency = <400000>; }; - /* I2C4 (DDC): unused */ + /* + * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 + * (e.g. display EDID) + */ + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <10000>; + }; /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ i2c@7000d000 { @@ -2112,7 +2119,7 @@ regulator-name = "VCC_USBO1"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <®_5v0>; }; @@ -2123,7 +2130,7 @@ regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <®_5v0>; }; diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h new file mode 100644 index 0000000000..11411ead10 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h @@ -0,0 +1,441 @@ +/* + * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SDRAM_RK3328_H +#define _ASM_ARCH_SDRAM_RK3328_H + +#define SR_IDLE 93 +#define PD_IDLE 13 +#define SDRAM_ADDR 0x00000000 +#define PATTERN (0x5aa5f00f) + +/* ddr pctl registers define */ +#define DDR_PCTL2_MSTR 0x0 +#define DDR_PCTL2_STAT 0x4 +#define DDR_PCTL2_MSTR1 0x8 +#define DDR_PCTL2_MRCTRL0 0x10 +#define DDR_PCTL2_MRCTRL1 0x14 +#define DDR_PCTL2_MRSTAT 0x18 +#define DDR_PCTL2_MRCTRL2 0x1c +#define DDR_PCTL2_DERATEEN 0x20 +#define DDR_PCTL2_DERATEINT 0x24 +#define DDR_PCTL2_PWRCTL 0x30 +#define DDR_PCTL2_PWRTMG 0x34 +#define DDR_PCTL2_HWLPCTL 0x38 +#define DDR_PCTL2_RFSHCTL0 0x50 +#define DDR_PCTL2_RFSHCTL1 0x54 +#define DDR_PCTL2_RFSHCTL2 0x58 +#define DDR_PCTL2_RFSHCTL4 0x5c +#define DDR_PCTL2_RFSHCTL3 0x60 +#define DDR_PCTL2_RFSHTMG 0x64 +#define DDR_PCTL2_RFSHTMG1 0x68 +#define DDR_PCTL2_RFSHCTL5 0x6c +#define DDR_PCTL2_INIT0 0xd0 +#define DDR_PCTL2_INIT1 0xd4 +#define DDR_PCTL2_INIT2 0xd8 +#define DDR_PCTL2_INIT3 0xdc +#define DDR_PCTL2_INIT4 0xe0 +#define DDR_PCTL2_INIT5 0xe4 +#define DDR_PCTL2_INIT6 0xe8 +#define DDR_PCTL2_INIT7 0xec +#define DDR_PCTL2_DIMMCTL 0xf0 +#define DDR_PCTL2_RANKCTL 0xf4 +#define DDR_PCTL2_CHCTL 0xfc +#define DDR_PCTL2_DRAMTMG0 0x100 +#define DDR_PCTL2_DRAMTMG1 0x104 +#define DDR_PCTL2_DRAMTMG2 0x108 +#define DDR_PCTL2_DRAMTMG3 0x10c +#define DDR_PCTL2_DRAMTMG4 0x110 +#define DDR_PCTL2_DRAMTMG5 0x114 +#define DDR_PCTL2_DRAMTMG6 0x118 +#define DDR_PCTL2_DRAMTMG7 0x11c +#define DDR_PCTL2_DRAMTMG8 0x120 +#define DDR_PCTL2_DRAMTMG9 0x124 +#define DDR_PCTL2_DRAMTMG10 0x128 +#define DDR_PCTL2_DRAMTMG11 0x12c +#define DDR_PCTL2_DRAMTMG12 0x130 +#define DDR_PCTL2_DRAMTMG13 0x134 +#define DDR_PCTL2_DRAMTMG14 0x138 +#define DDR_PCTL2_DRAMTMG15 0x13c +#define DDR_PCTL2_DRAMTMG16 0x140 +#define DDR_PCTL2_ZQCTL0 0x180 +#define DDR_PCTL2_ZQCTL1 0x184 +#define DDR_PCTL2_ZQCTL2 0x188 +#define DDR_PCTL2_ZQSTAT 0x18c +#define DDR_PCTL2_DFITMG0 0x190 +#define DDR_PCTL2_DFITMG1 0x194 +#define DDR_PCTL2_DFILPCFG0 0x198 +#define DDR_PCTL2_DFILPCFG1 0x19c +#define DDR_PCTL2_DFIUPD0 0x1a0 +#define DDR_PCTL2_DFIUPD1 0x1a4 +#define DDR_PCTL2_DFIUPD2 0x1a8 +#define DDR_PCTL2_DFIMISC 0x1b0 +#define DDR_PCTL2_DFITMG2 0x1b4 +#define DDR_PCTL2_DFITMG3 0x1b8 +#define DDR_PCTL2_DFISTAT 0x1bc +#define DDR_PCTL2_DBICTL 0x1c0 +#define DDR_PCTL2_ADDRMAP0 0x200 +#define DDR_PCTL2_ADDRMAP1 0x204 +#define DDR_PCTL2_ADDRMAP2 0x208 +#define DDR_PCTL2_ADDRMAP3 0x20c +#define DDR_PCTL2_ADDRMAP4 0x210 +#define DDR_PCTL2_ADDRMAP5 0x214 +#define DDR_PCTL2_ADDRMAP6 0x218 +#define DDR_PCTL2_ADDRMAP7 0x21c +#define DDR_PCTL2_ADDRMAP8 0x220 +#define DDR_PCTL2_ADDRMAP9 0x224 +#define DDR_PCTL2_ADDRMAP10 0x228 +#define DDR_PCTL2_ADDRMAP11 0x22c +#define DDR_PCTL2_ODTCFG 0x240 +#define DDR_PCTL2_ODTMAP 0x244 +#define DDR_PCTL2_SCHED 0x250 +#define DDR_PCTL2_SCHED1 0x254 +#define DDR_PCTL2_PERFHPR1 0x25c +#define DDR_PCTL2_PERFLPR1 0x264 +#define DDR_PCTL2_PERFWR1 0x26c +#define DDR_PCTL2_DQMAP0 0x280 +#define DDR_PCTL2_DQMAP1 0x284 +#define DDR_PCTL2_DQMAP2 0x288 +#define DDR_PCTL2_DQMAP3 0x28c +#define DDR_PCTL2_DQMAP4 0x290 +#define DDR_PCTL2_DQMAP5 0x294 +#define DDR_PCTL2_DBG0 0x300 +#define DDR_PCTL2_DBG1 0x304 +#define DDR_PCTL2_DBGCAM 0x308 +#define DDR_PCTL2_DBGCMD 0x30c +#define DDR_PCTL2_DBGSTAT 0x310 +#define DDR_PCTL2_SWCTL 0x320 +#define DDR_PCTL2_SWSTAT 0x324 +#define DDR_PCTL2_POISONCFG 0x36c +#define DDR_PCTL2_POISONSTAT 0x370 +#define DDR_PCTL2_ADVECCINDEX 0x374 +#define DDR_PCTL2_ADVECCSTAT 0x378 +#define DDR_PCTL2_PSTAT 0x3fc +#define DDR_PCTL2_PCCFG 0x400 +#define DDR_PCTL2_PCFGR_n 0x404 +#define DDR_PCTL2_PCFGW_n 0x408 +#define DDR_PCTL2_PCTRL_n 0x490 + +/* PCTL2_MRSTAT */ +#define MR_WR_BUSY BIT(0) + +/* PHY_REG0 */ +#define DIGITAL_DERESET BIT(3) +#define ANALOG_DERESET BIT(2) +#define DIGITAL_RESET (0 << 3) +#define ANALOG_RESET (0 << 2) + +/* PHY_REG1 */ +#define PHY_DDR2 (0) +#define PHY_LPDDR2 (1) +#define PHY_DDR3 (2) +#define PHY_LPDDR3 (3) +#define PHY_DDR4 (4) +#define PHY_BL_4 (0 << 2) +#define PHY_BL_8 BIT(2) + +/* PHY_REG2 */ +#define PHY_DTT_EN BIT(0) +#define PHY_DTT_DISB (0 << 0) +#define PHY_WRITE_LEVELING_EN BIT(2) +#define PHY_WRITE_LEVELING_DISB (0 << 2) +#define PHY_SELECT_CS0 (2) +#define PHY_SELECT_CS1 (1) +#define PHY_SELECT_CS0_1 (0) +#define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6) +#define PHY_DATA_TRAINING_SELECTCS(n) (n << 4) + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) +#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) +#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) +#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) +#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) +#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) +#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) +#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) +#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) +#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) +#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) +#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) +#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) +#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) +#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) +#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) +#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) +#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) +#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) +#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) +#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) +#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) +#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) + +/* noc registers define */ +#define DDRCONF 0x8 +#define DDRTIMING 0xc +#define DDRMODE 0x10 +#define READLATENCY 0x14 +#define AGING0 0x18 +#define AGING1 0x1c +#define AGING2 0x20 +#define AGING3 0x24 +#define AGING4 0x28 +#define AGING5 0x2c +#define ACTIVATE 0x38 +#define DEVTODEV 0x3c +#define DDR4TIMING 0x40 + +/* DDR GRF */ +#define DDR_GRF_CON(n) (0 + (n) * 4) +#define DDR_GRF_STATUS_BASE (0X100) +#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) + +/* CRU_SOFTRESET_CON5 */ +#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15)) +#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14)) +#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13)) +#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12)) +#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11)) +#define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9)) +#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8)) +#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7)) +/* CRU_SOFTRESET_CON9 */ +#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9)) + +/* CRU register */ +#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) +#define CRU_MODE (0x80) +#define CRU_GLB_CNT_TH (0x90) +#define CRU_CLKSEL_CON_BASE 0x100 +#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) +#define CRU_CLKGATE_CON_BASE 0x200 +#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) +#define CRU_CLKSFTRST_CON_BASE 0x300 +#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) + +/* CRU_PLL_CON0 */ +#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) +#define FBDIV(n) ((0xFFF << 16) | (n)) + +/* CRU_PLL_CON1 */ +#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) +#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) +#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) +#define LOCK(n) (((n) >> 10) & 0x1) +#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) +#define REFDIV(n) ((0x3F << 16) | (n)) + +union noc_ddrtiming { + u32 d32; + struct { + unsigned acttoact:6; + unsigned rdtomiss:6; + unsigned wrtomiss:6; + unsigned burstlen:3; + unsigned rdtowr:5; + unsigned wrtord:5; + unsigned bwratio:1; + } b; +} NOC_TIMING_T; + +union noc_activate { + u32 d32; + struct { + unsigned rrd:4; + unsigned faw:6; + unsigned fawbank:1; + unsigned reserved1:21; + } b; +}; + +union noc_devtodev { + u32 d32; + struct { + unsigned busrdtord:2; + unsigned busrdtowr:2; + unsigned buswrtord:2; + unsigned reserved2:26; + } b; +}; + +union noc_ddr4timing { + u32 d32; + struct { + unsigned ccdl:3; + unsigned wrtordl:5; + unsigned rrdl:4; + unsigned reserved2:20; + } b; +}; + +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge:1; + unsigned bwratioextended:1; + unsigned reserved3:30; + } b; +}; + +u32 addrmap[21][9] = { + /* map0 map1 map2 map3 map4 map5 map6 map7 map8 */ + {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f0f, 0x3f3f}, + {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f3f}, + {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, + 0x0f080808, 0x00000f0f, 0x3f3f}, + {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f3f}, + {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, + 0x0f090909, 0x00000f0f, 0x3f3f}, + {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f3f}, + {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f3f}, + {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909, + 0x0f090909, 0x00000f0f, 0x3f3f}, + {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f0f, 0x3f3f}, + {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x0f070707, 0x00000f0f, 0x3f3f}, + + {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x0801}, + {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x0f080808, 0x00000f0f, 0x0801}, + {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x0700}, + {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x0700}, + {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f01}, + {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f01}, + {24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f06, 0x3f00}, + {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909, + 0x0f090909, 0x00000f0f, 0x0801}, + {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x0700}, + {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f01}, + + {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f00} +}; + +struct rk3328_msch_timings { + union noc_ddrtiming ddrtiming; + union noc_ddrmode ddrmode; + u32 readlatency; + union noc_activate activate; + union noc_devtodev devtodev; + union noc_ddr4timing ddr4timing; + u32 agingx0; +}; + +struct rk3328_msch_regs { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 aging0; + u32 aging1; + u32 aging2; + u32 aging3; + u32 aging4; + u32 aging5; + u32 reserved[2]; + u32 activate; + u32 devtodev; + u32 ddr4_timing; +}; + +struct rk3328_ddr_grf_regs { + u32 ddr_grf_con[4]; + u32 reserved[(0x100 - 0x10) / 4]; + u32 ddr_grf_status[11]; +}; + +struct rk3328_ddr_pctl_regs { + u32 pctl[30][2]; +}; + +struct rk3328_ddr_phy_regs { + u32 phy[5][2]; +}; + +struct rk3328_ddr_skew { + u32 a0_a1_skew[15]; + u32 cs0_dm0_skew[11]; + u32 cs0_dm1_skew[11]; + u32 cs0_dm2_skew[11]; + u32 cs0_dm3_skew[11]; + u32 cs1_dm0_skew[11]; + u32 cs1_dm1_skew[11]; + u32 cs1_dm2_skew[11]; + u32 cs1_dm3_skew[11]; +}; + +struct rk3328_sdram_channel { + unsigned int rank; + unsigned int col; + /* 3:8bank, 2:4bank */ + unsigned int bk; + /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int bw; + /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int dbw; + unsigned int row_3_4; + unsigned int cs0_row; + unsigned int cs1_row; + unsigned int ddrconfig; + struct rk3328_msch_timings noc_timings; +}; + +struct rk3328_sdram_params { + struct rk3328_sdram_channel ch; + unsigned int ddr_freq; + unsigned int dramtype; + unsigned int odt; + struct rk3328_ddr_pctl_regs pctl_regs; + struct rk3328_ddr_phy_regs phy_regs; + struct rk3328_ddr_skew skew; +}; + +#define PHY_REG(base, n) (base + 4 * (n)) + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index e337d06b99..f5a80b4f0c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -110,9 +110,14 @@ config ROCKCHIP_RK3328 select ARM64 select SUPPORT_SPL select SPL + select SUPPORT_TPL + select TPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL + select TPL_NEEDS_SEPARATE_STACK if TPL imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SERIAL_SUPPORT + imply TPL_SERIAL_SUPPORT imply SPL_SEPARATE_BSS select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index f8e15288e0..d13a169022 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -27,6 +27,18 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" + +config TPL_TEXT_BASE + default 0xff091000 + +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0xff098000 + source "board/rockchip/evb_rk3328/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index 592f287613..c2448d7273 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CRU_BASE 0xFF440000 #define GRF_BASE 0xFF100000 #define UART2_BASE 0xFF130000 +#define FW_DDR_CON_REG 0xFF7C0040 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000", @@ -46,8 +47,12 @@ struct mm_region *mem_map = rk3328_mem_map; int arch_cpu_init(void) { +#ifdef CONFIG_SPL_BUILD /* We do some SoC one time setting here. */ + /* Disable the ddr secure region setting to make it non-secure */ + rk_setreg(FW_DDR_CON_REG, 0x200); +#endif return 0; } diff --git a/arch/arm/mach-tegra/sys_info.c b/arch/arm/mach-tegra/sys_info.c index 9975f33e0b..5dc998a52b 100644 --- a/arch/arm/mach-tegra/sys_info.c +++ b/arch/arm/mach-tegra/sys_info.c @@ -6,24 +6,36 @@ #include <common.h> #include <linux/ctype.h> +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30) +#include <asm/arch-tegra/pmc.h> -static void upstring(char *s) +static char *get_reset_cause(void) { - while (*s) { - *s = toupper(*s); - s++; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + switch (pmc->pmc_reset_status) { + case 0x00: + return "POR"; + case 0x01: + return "WATCHDOG"; + case 0x02: + return "SENSOR"; + case 0x03: + return "SW_MAIN"; + case 0x04: + return "LP0"; } + return "UNKNOWN"; } +#endif /* Print CPU information */ int print_cpuinfo(void) { - char soc_name[10]; - - strncpy(soc_name, CONFIG_SYS_SOC, 10); - upstring(soc_name); - puts(soc_name); - puts("\n"); + printf("SoC: %s\n", CONFIG_SYS_SOC); +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30) + printf("Reset cause: %s\n", get_reset_cause()); +#endif /* TBD: Add printf of major/minor rev info, stepping, etc. */ return 0; diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 992c0beb04..abc050c27b 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -238,6 +238,45 @@ static bool is_partition_powered(u32 partid) return !!(reg & (1 << partid)); } +static void unpower_partition(u32 partid) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + debug("%s: part ID = %08X\n", __func__, partid); + /* Is the partition on? */ + if (is_partition_powered(partid)) { + /* Yes, toggle the partition power state (ON -> OFF) */ + debug("power_partition, toggling state\n"); + writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); + + /* Wait for the power to come down */ + while (is_partition_powered(partid)) + ; + + /* Give I/O signals time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + } +} + +void unpower_cpus(void) +{ + debug("%s entry: G cluster\n", __func__); + + /* Power down the fast cluster rail partition */ + debug("%s: CRAIL\n", __func__); + unpower_partition(CRAIL); + + /* Power down the fast cluster non-CPU partition */ + debug("%s: C0NC\n", __func__); + unpower_partition(C0NC); + + /* Power down the fast cluster CPU0 partition */ + debug("%s: CE0\n", __func__); + unpower_partition(CE0); + + debug("%s: done\n", __func__); +} + static void power_partition(u32 partid) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; @@ -284,6 +323,12 @@ void start_cpu(u32 reset_vector) debug("%s entry, reset_vector = %x\n", __func__, reset_vector); + /* + * High power clusters are on after software reset, + * it may interfere with tegra124_ram_repair. + * unpower them. + */ + unpower_cpus(); tegra124_init_clocks(); /* Set power-gating timer multiplier */ diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 3308b3595f..d9711ab227 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,24 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig +KHADAS-EDGE +M: Nick Xie <nick@khadas.com> +S: Maintained +F: configs/khadas-edge-rk3399_defconfig +F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi + +KHADAS-EDGE-CAPTAIN +M: Nick Xie <nick@khadas.com> +S: Maintained +F: configs/khadas-edge-captain-rk3399_defconfig +F: arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi + +KHADAS-EDGE-V +M: Nick Xie <nick@khadas.com> +S: Maintained +F: configs/khadas-edge-v-rk3399_defconfig +F: arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi + NANOPC-T4 M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index b87e9e7a3e..beb7e10dfe 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <environment.h> #include <pci_tegra.h> #include <power/as3722.h> #include <power/pmic.h> @@ -19,11 +20,16 @@ #define LAN_DEV_OFF_N TEGRA_GPIO(O, 6) #define LAN_RESET_N TEGRA_GPIO(S, 2) +#define FAN_EN TEGRA_GPIO(DD, 2) #define LAN_WAKE_N TEGRA_GPIO(O, 5) #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT #define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */ #define RESET_MOCI_CTRL TEGRA_GPIO(U, 4) #endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */ +#define VCC_USBH TEGRA_GPIO(T, 6) +#define VCC_USBH_V1_0 TEGRA_GPIO(N, 5) +#define VCC_USBO1 TEGRA_GPIO(T, 5) +#define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4) int arch_misc_init(void) { @@ -31,6 +37,38 @@ int arch_misc_init(void) NVBOOTTYPE_RECOVERY) printf("USB recovery mode\n"); + /* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */ + gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication"); + gpio_direction_input(TEGRA_GPIO(V, 0)); + if (gpio_get_value(TEGRA_GPIO(V, 0))) { + /* + * if using the default device tree for new V1.2 and later HW, + * use version for older V1.0 and V1.1 HW + */ + char *fdt_env = env_get("fdt_module"); + + if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) { + env_set("fdt_module", FDT_MODULE_V1_0); + printf("patching fdt_module to " FDT_MODULE_V1_0 + " for older V1.0 and V1.1 HW\n"); +#ifndef CONFIG_ENV_IS_NOWHERE + env_save(); +#endif + } + + /* activate USB power enable GPIOs */ + gpio_request(VCC_USBH_V1_0, "VCC_USBH"); + gpio_direction_output(VCC_USBH_V1_0, 1); + gpio_request(VCC_USBO1_V1_0, "VCC_USBO1"); + gpio_direction_output(VCC_USBO1_V1_0, 1); + } else { + /* activate USB power enable GPIOs */ + gpio_request(VCC_USBH, "VCC_USBH"); + gpio_direction_output(VCC_USBH, 1); + gpio_request(VCC_USBO1, "VCC_USBO1"); + gpio_direction_output(VCC_USBO1, 1); + } + return 0; } @@ -242,6 +280,15 @@ void tegra_pcie_board_port_reset(struct tegra_pcie_port *port) #endif /* CONFIG_PCI_TEGRA */ /* + * Enable/start PWM CPU fan + */ +void start_cpu_fan(void) +{ + gpio_request(FAN_EN, "FAN_EN"); + gpio_direction_output(FAN_EN, 1); +} + +/* * Backlight off before OS handover */ void board_preboot_os(void) diff --git a/board/toradex/apalis-tk1/as3722_init.c b/board/toradex/apalis-tk1/as3722_init.c index bd754e5fcf..15f8dce2f1 100644 --- a/board/toradex/apalis-tk1/as3722_init.c +++ b/board/toradex/apalis-tk1/as3722_init.c @@ -43,6 +43,29 @@ void pmic_enable_cpu_vdd(void) udelay(10 * 1000); #endif + /* + * Make sure all non-fused regulators are down. + * That way we're in known state after software reboot from linux + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES); + udelay(10 * 1000); + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES); + udelay(10 * 1000); + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES); + udelay(10 * 1000); + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES); + udelay(10 * 1000); + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES); + udelay(10 * 1000); + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES); + udelay(10 * 1000); + debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); /* * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. diff --git a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h index 1584d9b2d3..6778a41e07 100644 --- a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h +++ b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (c) 2016, Toradex, Inc. + * Copyright (c) 2016-2019, Toradex, Inc. */ #ifndef _PINMUX_CONFIG_APALIS_TK1_H_ @@ -24,8 +24,6 @@ static const struct tegra_gpio_config apalis_tk1_gpio_inits[] = { GPIO_INIT(K, 2, IN), GPIO_INIT(K, 7, IN), GPIO_INIT(N, 2, OUT1), - GPIO_INIT(N, 4, OUT1), - GPIO_INIT(N, 5, OUT1), GPIO_INIT(N, 7, IN), GPIO_INIT(O, 5, IN), GPIO_INIT(Q, 0, OUT0), /* Shift_CTRL_OE[0] */ @@ -39,7 +37,8 @@ static const struct tegra_gpio_config apalis_tk1_gpio_inits[] = { GPIO_INIT(R, 1, OUT0), /* Shift_CTRL_Dir_In[1] */ GPIO_INIT(R, 2, OUT0), /* Shift_CTRL_OE[3] */ GPIO_INIT(S, 3, OUT0), /* Shift_CTRL_Dir_In[2] */ - GPIO_INIT(U, 4, OUT1), + GPIO_INIT(U, 4, OUT0), /* RESET_MOCI_CTRL */ + GPIO_INIT(V, 0, IN), GPIO_INIT(W, 3, IN), GPIO_INIT(W, 5, IN), GPIO_INIT(BB, 0, IN), @@ -130,8 +129,8 @@ static const struct pmux_pingrp_config apalis_tk1_pingrps[] = { PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(USB_VBUS_EN0_PN4, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(USB_VBUS_EN1_PN5, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(HDMI_INT_PN7, RSVD1, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL), PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), @@ -175,8 +174,8 @@ static const struct pmux_pingrp_config apalis_tk1_pingrps[] = { PINCFG(KB_ROW15_PS7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW17_PT1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN2_I2C_SCL_PT5, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN2_I2C_SDA_PT6, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PU1, UARTA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), @@ -185,12 +184,12 @@ static const struct pmux_pingrp_config apalis_tk1_pingrps[] = { PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PU5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PU6, PWM3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PV0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CD_N_PV2, RSVD3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC1_WP_N_PV3, SDMMC1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), - PINCFG(DDC_SCL_PV4, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DDC_SDA_PV5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), PINCFG(GPIO_W2_AUD_PW2, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(GPIO_W3_AUD_PW3, SPI6, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 41f3aff149..be0554b150 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -8,7 +8,7 @@ CONFIG_TARGET_APALIS_TK1=y CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=1 -CONFIG_BOOTCOMMAND="run emmcboot; setenv fdtfile ${soc}-apalis-${fdt_board}.dtb && run distro_bootcmd" +CONFIG_BOOTCOMMAND="run emmcboot; setenv fdtfile ${soc}-${fdt-module}-${fdt_board}.dtb && run distro_bootcmd" CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_VERSION_VARIABLE=y @@ -17,7 +17,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Apalis TK1 # " # CONFIG_CMD_IMI is not set -CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -34,8 +33,6 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis" CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_SPL_DM=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y @@ -56,7 +53,7 @@ CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 -CONFIG_USB_GADGET_PRODUCT_NUM=0xffff +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index cf4d14434d..75b5a1dca3 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -14,7 +14,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Apalis T30 # " # CONFIG_CMD_IMI is not set -CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -31,8 +30,6 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis" CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_SPL_DM=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_E1000=y CONFIG_PCI=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 170a1b0b27..73d13bbb06 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -13,7 +13,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Colibri T20 # " # CONFIG_CMD_IMI is not set -CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -39,8 +38,6 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=1536 CONFIG_SPL_DM=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_MTD=y CONFIG_MTD_UBI_FASTMAP=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 769f6f3c9e..1e2268a105 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -14,7 +14,6 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Colibri T30 # " # CONFIG_CMD_IMI is not set -CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -30,8 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri" CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_SPL_DM=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index fcc04f27ec..12be1dedc6 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -1,5 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y @@ -9,31 +15,50 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF_SUPPORT=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_BOOTROM_SUPPORT=y +CONFIG_TPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_TPL_SERIAL_PRESENT=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y -CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y +CONFIG_TPL_CLK=y CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y +CONFIG_TPL_OF_PLATDATA=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y @@ -44,6 +69,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y @@ -51,9 +77,14 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y @@ -69,4 +100,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x330a CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig new file mode 100644 index 0000000000..11ec2dab13 --- /dev/null +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_SYS_PROMPT="kedge# " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig new file mode 100644 index 0000000000..c31360af86 --- /dev/null +++ b/configs/khadas-edge-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_SYS_PROMPT="kedge# " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig new file mode 100644 index 0000000000..8c9e9fc7b9 --- /dev/null +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_SYS_PROMPT="kedge# " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index ef453e72c1..6484845fb6 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -34,15 +34,20 @@ CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y +CONFIG_TPL_CLK=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -65,6 +70,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 @@ -85,4 +91,12 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x330a CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_TPL_DM=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_BOOTROM_SUPPORT=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 8ccbb87264..7d4dc1b33b 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -309,17 +309,11 @@ Booting from an SD card on Pine64 Rock64 (RK3328) ================================================= For Rock64 rk3328 board the following three parts are required: -TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and -u-boot.itb are to be compiled as usual, TPL is currently not -implemented in u-boot, so you need to pick one from rkbin: - - - Get the rkbin - - => git clone https://github.com/rockchip-linux/rkbin.git +TPL, SPL, and the u-boot image tree blob. - Create TPL/SPL image - => tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img + => tools/mkimage -n rk3328 -T rksd -d tpl/u-boot-tpl.bin idbloader.img => cat spl/u-boot-spl.bin >> idbloader.img - Write TPL/SPL image at 64 sector diff --git a/doc/device-tree-bindings/sound/intel-hda.txt b/doc/device-tree-bindings/sound/intel-hda.txt index fb2ce55006..aa96be06e9 100644 --- a/doc/device-tree-bindings/sound/intel-hda.txt +++ b/doc/device-tree-bindings/sound/intel-hda.txt @@ -12,6 +12,7 @@ Required properties: Optional properties - intel,beep-nid: Node ID to use for beep (will be detected if not provided) +- codec-enable-gpio : The GPIO used to enable the audio codec Required subnodes: - codecs: Contains a list of codec nodes diff --git a/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt new file mode 100644 index 0000000000..25c63eac62 --- /dev/null +++ b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt @@ -0,0 +1,54 @@ +NVIDIA Tegra audio complex, with MAX98090 CODEC + +Required properties: +- compatible : "nvidia,tegra-audio-max98090" +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names : Must include the following entries: + - pll_a + - pll_a_out0 + - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) +- nvidia,model : The user-visible name of this sound complex. +- nvidia,audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the connection's sink, + the second being the connection's source. Valid names for sources and + sinks are the MAX98090's pins (as documented in its binding), and the jacks + on the board: + + * Headphones + * Speakers + * Mic Jack + * Int Mic + +- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's + connected to the CODEC. +- nvidia,audio-codec : The phandle of the MAX98090 audio codec. + +Optional properties: +- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in +- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in +- codec-enable-gpio : The GPIO used to enable the audio codec + +Example: + +sound { + compatible = "nvidia,tegra-audio-max98090-venice2", + "nvidia,tegra-audio-max98090"; + nvidia,model = "NVIDIA Tegra Venice2"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; +}; diff --git a/doc/device-tree-bindings/sound/snow.txt b/doc/device-tree-bindings/sound/snow.txt new file mode 100644 index 0000000000..fa06956e77 --- /dev/null +++ b/doc/device-tree-bindings/sound/snow.txt @@ -0,0 +1,32 @@ +Audio Binding for Snow boards + +Required properties: +- compatible : Can be one of the following, + "google,snow-audio-max98090" or + "google,snow-audio-max98091" or + "google,snow-audio-max98095" +- samsung,i2s-controller (deprecated): The phandle of the Samsung I2S controller +- samsung,audio-codec (deprecated): The phandle of the audio codec + +Required sub-nodes: + + - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S + controller + - 'codec' subnode with a 'sound-dai' property containing list of phandles + to the CODEC nodes, first entry must be the phandle of the MAX98090, + MAX98091 or MAX98095 CODEC (exact device type is indicated by the compatible + string) and the second entry must be the phandle of the HDMI IP block node + +Optional: +- samsung,model: The name of the sound-card +- codec-enable-gpio : The GPIO used to enable the audio codec + +Example: + +sound { + compatible = "google,snow-audio-max98095"; + + samsung,model = "Snow-I2S-MAX98095"; + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&max98095>; +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 4cdae41b59..c6812f6517 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -156,6 +156,7 @@ config MMC_HS400_SUPPORT config SPL_MMC_HS400_SUPPORT bool "enable HS400 support in SPL" + select SPL_MMC_HS200_SUPPORT help The HS400 mode is support by some eMMC. The bus frequency is up to 200MHz. This mode requires tuning the IO. @@ -591,6 +592,17 @@ config MMC_SDHCI_TEGRA If unsure, say N. +config TEGRA124_MMC_DISABLE_EXT_LOOPBACK + bool "Disable external clock loopback" + depends on MMC_SDHCI_TEGRA && TEGRA124 + help + Disable the external clock loopback and use the internal one on SDMMC3 + as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits + being set to 0xfffd according to the TRM. + + TODO(marcel.ziswiler@toradex.com): Move to device tree controlled + approach once proper kernel integration made it mainline. + config MMC_SDHCI_ZYNQ bool "Arasan SDHCI controller support" depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL @@ -670,17 +682,6 @@ config MMC_MTK endif -config TEGRA124_MMC_DISABLE_EXT_LOOPBACK - bool "Disable external clock loopback" - depends on MMC_SDHCI_TEGRA && TEGRA124 - help - Disable the external clock loopback and use the internal one on SDMMC3 - as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits - being set to 0xfffd according to the TRM. - - TODO(marcel.ziswiler@toradex.com): Move to device tree controlled - approach once proper kernel integration made it mainline. - config FSL_ESDHC bool "Freescale/NXP eSDHC controller support" help diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index 4be47ba75e..d930ed8da0 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -88,13 +88,13 @@ static int atmel_sdhci_probe(struct udevice *dev) return -EINVAL; host->max_clk = max_clk; + host->mmc = &plat->mmc; + host->mmc->dev = dev; ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ); if (ret) return ret; - host->mmc = &plat->mmc; - host->mmc->dev = dev; host->mmc->priv = host; upriv->mmc = host->mmc; diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 08bddd410e..bf3304c4dc 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -214,6 +214,9 @@ static int bcm2835_sdhci_probe(struct udevice *dev) host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; host->ops = &bcm2835_ops; + host->mmc = &plat->mmc; + host->mmc->dev = dev; + ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ); if (ret) { debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret); @@ -221,7 +224,6 @@ static int bcm2835_sdhci_probe(struct udevice *dev) } upriv->mmc = &plat->mmc; - host->mmc = &plat->mmc; host->mmc->priv = host; return sdhci_probe(dev); diff --git a/drivers/mmc/bcmstb_sdhci.c b/drivers/mmc/bcmstb_sdhci.c index eef46f3af1..c14f8289e6 100644 --- a/drivers/mmc/bcmstb_sdhci.c +++ b/drivers/mmc/bcmstb_sdhci.c @@ -73,6 +73,8 @@ static int sdhci_bcmstb_probe(struct udevice *dev) if (ret) return ret; + host->mmc = &plat->mmc; + host->mmc->dev = dev; ret = sdhci_setup_cfg(&plat->cfg, host, BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY, BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY); @@ -80,7 +82,6 @@ static int sdhci_bcmstb_probe(struct udevice *dev) return ret; upriv->mmc = &plat->mmc; - host->mmc = &plat->mmc; host->mmc->priv = host; return sdhci_probe(dev); diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 1992d61182..22f6c7eefd 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -13,6 +13,7 @@ #include <mmc.h> #include <dwmmc.h> #include <wait_bit.h> +#include <power/regulator.h> #define PAGE_SIZE 4096 @@ -493,6 +494,21 @@ static int dwmci_set_ios(struct mmc *mmc) if (host->clksel) host->clksel(host); +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (mmc->vqmmc_supply) { + int ret; + + if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + regulator_set_value(mmc->vqmmc_supply, 1800000); + else + regulator_set_value(mmc->vqmmc_supply, 3300000); + + ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true); + if (ret) + return ret; + } +#endif + return 0; } diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 51f9e0ec05..cae42ec4ac 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -141,12 +141,12 @@ static int msm_sdc_probe(struct udevice *dev) writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); } - ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); host->mmc = &plat->mmc; + host->mmc->dev = dev; + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret) return ret; host->mmc->priv = &prv->host; - host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 182d41637f..404264a697 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -33,12 +33,12 @@ static int pci_mmc_probe(struct udevice *dev) host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); host->name = dev->name; + host->mmc = &plat->mmc; + host->mmc->dev = dev; ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret) return ret; - host->mmc = &plat->mmc; host->mmc->priv = &priv->host; - host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 9dd0b865eb..53efa968cf 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -204,13 +204,13 @@ static int s5p_sdhci_probe(struct udevice *dev) if (ret) return ret; + host->mmc = &plat->mmc; + host->mmc->dev = dev; ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000); if (ret) return ret; - host->mmc = &plat->mmc; host->mmc->priv = host; - host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 4f9338f733..4736263bf2 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -269,12 +269,13 @@ static int sdhci_cdns_probe(struct udevice *dev) if (ret) return ret; + host->mmc = &plat->mmc; + host->mmc->dev = dev; ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret) return ret; upriv->mmc = &plat->mmc; - host->mmc = &plat->mmc; host->mmc->priv = host; return sdhci_probe(dev); diff --git a/drivers/mmc/tangier_sdhci.c b/drivers/mmc/tangier_sdhci.c index 4c33356b9f..0d6e5d6246 100644 --- a/drivers/mmc/tangier_sdhci.c +++ b/drivers/mmc/tangier_sdhci.c @@ -51,13 +51,14 @@ static int sdhci_tangier_probe(struct udevice *dev) /* MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195 */ host->voltages = MMC_VDD_165_195; + host->mmc = &plat->mmc; + host->mmc->dev = dev; ret = sdhci_setup_cfg(&plat->cfg, host, SDHCI_TANGIER_FMAX, SDHCI_TANGIER_FMIN); if (ret) return ret; upriv->mmc = &plat->mmc; - host->mmc = &plat->mmc; host->mmc->priv = host; return sdhci_probe(dev); diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index c525084250..3225a7ac93 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -242,13 +242,14 @@ static int arasan_sdhci_probe(struct udevice *dev) host->max_clk = clock; + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; + ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, CONFIG_ZYNQ_SDHCI_MIN_FREQ); - host->mmc = &plat->mmc; if (ret) return ret; - host->mmc->priv = host; - host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index f4e0b18447..656696ac3c 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -2,22 +2,1029 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ - #include <common.h> +#include <clk.h> +#include <debug_uart.h> #include <dm.h> +#include <dt-structs.h> #include <ram.h> +#include <regmap.h> #include <syscon.h> +#include <asm/io.h> #include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3328.h> #include <asm/arch-rockchip/grf_rk3328.h> #include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_rk3328.h> +#include <asm/arch-rockchip/uart.h> struct dram_info { +#ifdef CONFIG_TPL_BUILD + struct rk3328_ddr_pctl_regs *pctl; + struct rk3328_ddr_phy_regs *phy; + struct clk ddr_clk; + struct rk3328_cru *cru; + struct rk3328_msch_regs *msch; + struct rk3328_ddr_grf_regs *ddr_grf; +#endif struct ram_info info; struct rk3328_grf_regs *grf; }; +#ifdef CONFIG_TPL_BUILD + +struct rk3328_sdram_channel sdram_ch; + +struct rockchip_dmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3328_dmc dtplat; +#else + struct rk3328_sdram_params sdram_params; +#endif + struct regmap *map; +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rockchip_dmc_plat *plat = dev_get_platdata(dev); + struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; + int ret; + + ret = regmap_init_mem_platdata(dev, dtplat->reg, + ARRAY_SIZE(dtplat->reg) / 2, + &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static void rkclk_ddr_reset(struct dram_info *dram, + u32 ctl_srstn, u32 ctl_psrstn, + u32 phy_srstn, u32 phy_psrstn) +{ + writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) | + ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn), + &dram->cru->softrst_con[5]); + writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]); +} + +static void rkclk_set_dpll(struct dram_info *dram, unsigned int mhz) +{ + unsigned int refdiv, postdiv1, postdiv2, fbdiv; + int delay = 1000; + + refdiv = 1; + if (mhz <= 300) { + postdiv1 = 4; + postdiv2 = 2; + } else if (mhz <= 400) { + postdiv1 = 6; + postdiv2 = 1; + } else if (mhz <= 600) { + postdiv1 = 4; + postdiv2 = 1; + } else if (mhz <= 800) { + postdiv1 = 3; + postdiv2 = 1; + } else if (mhz <= 1600) { + postdiv1 = 2; + postdiv2 = 1; + } else { + postdiv1 = 1; + postdiv2 = 1; + } + fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; + + writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con); + writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); + writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), + &dram->cru->dpll_con[1]); + + while (delay > 0) { + udelay(1); + if (LOCK(readl(&dram->cru->dpll_con[1]))) + break; + delay--; + } + + writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con); +} + +static void rkclk_configure_ddr(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + void __iomem *phy_base = dram->phy; + + /* choose DPLL for ddr clk source */ + clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); + + /* for inno ddr phy need 2*freq */ + rkclk_set_dpll(dram, sdram_params->ddr_freq * 2); +} + +static void phy_soft_reset(struct dram_info *dram) +{ + void __iomem *phy_base = dram->phy; + + clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2); + udelay(1); + setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET); + udelay(5); + setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET); + udelay(1); +} + +static int pctl_cfg(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + u32 i; + void __iomem *pctl_base = dram->pctl; + + for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) { + writel(sdram_params->pctl_regs.pctl[i][1], + pctl_base + sdram_params->pctl_regs.pctl[i][0]); + } + clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG, + (0xff << 16) | 0x1f, + ((SR_IDLE & 0xff) << 16) | (PD_IDLE & 0x1f)); + /* + * dfi_lp_en_pd=1,dfi_lp_wakeup_pd=2 + * hw_lp_idle_x32=1 + */ + if (sdram_params->dramtype == LPDDR3) { + setbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, 1); + clrsetbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, + 0xf << 4, + 2 << 4); + } + clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL, + 0xfff << 16, + 1 << 16); + /* disable zqcs */ + setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31); + setbits_le32(pctl_base + 0x2000 + DDR_PCTL2_ZQCTL0, 1u << 31); + + return 0; +} + +/* return ddrconfig value + * (-1), find ddrconfig fail + * other, the ddrconfig value + * only support cs0_row >= cs1_row + */ +static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params) +{ + static const u16 ddr_cfg_2_rbc[] = { + /*************************** + * [5:4] row(13+n) + * [3] cs(0:0 cs, 1:2 cs) + * [2] bank(0:0bank,1:8bank) + * [1:0] col(11+n) + ****************************/ + /* row, cs, bank, col */ + ((3 << 4) | (0 << 3) | (1 << 2) | 0), + ((3 << 4) | (0 << 3) | (1 << 2) | 1), + ((2 << 4) | (0 << 3) | (1 << 2) | 2), + ((3 << 4) | (0 << 3) | (1 << 2) | 2), + ((2 << 4) | (0 << 3) | (1 << 2) | 3), + ((3 << 4) | (1 << 3) | (1 << 2) | 0), + ((3 << 4) | (1 << 3) | (1 << 2) | 1), + ((2 << 4) | (1 << 3) | (1 << 2) | 2), + ((3 << 4) | (0 << 3) | (0 << 2) | 1), + ((2 << 4) | (0 << 3) | (1 << 2) | 1), + }; + + static const u16 ddr4_cfg_2_rbc[] = { + /*************************** + * [6] cs 0:0cs 1:2 cs + * [5:3] row(13+n) + * [2] cs(0:0 cs, 1:2 cs) + * [1] bw 0: 16bit 1:32bit + * [0] diebw 0:8bit 1:16bit + ***************************/ + /* cs, row, cs, bw, diebw */ + ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0), + ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0), + ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0), + ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0), + ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1), + ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1), + ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1), + ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0), + ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0), + ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1), + ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1), + }; + + u32 cs, bw, die_bw, col, row, bank; + u32 i, tmp; + u32 ddrconf = -1; + + cs = sdram_ch.rank; + bw = sdram_ch.bw; + die_bw = sdram_ch.dbw; + col = sdram_ch.col; + row = sdram_ch.cs0_row; + bank = sdram_ch.bk; + + if (sdram_params->dramtype == DDR4) { + tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw; + for (i = 10; i < 17; i++) { + if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) && + ((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) && + ((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) { + ddrconf = i; + goto out; + } + } + } else { + if (bank == 2) { + ddrconf = 8; + goto out; + } + + tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0); + for (i = 0; i < 5; i++) + if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) && + ((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) { + ddrconf = i; + goto out; + } + } + +out: + if (ddrconf > 20) + printf("calculate_ddrconfig error\n"); + + return ddrconf; +} + +/* n: Unit bytes */ +static void copy_to_reg(u32 *dest, u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +/******* + * calculate controller dram address map, and setting to register. + * argument sdram_ch.ddrconf must be right value before + * call this function. + *******/ +static void set_ctl_address_map(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + void __iomem *pctl_base = dram->pctl; + + copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), + &addrmap[sdram_ch.ddrconfig][0], 9 * 4); + if (sdram_params->dramtype == LPDDR3 && sdram_ch.row_3_4) + setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); + if (sdram_params->dramtype == DDR4 && sdram_ch.bw == 0x1) + setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); + + if (sdram_ch.rank == 1) + clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f); +} + +static void phy_dll_bypass_set(struct dram_info *dram, u32 freq) +{ + u32 tmp; + void __iomem *phy_base = dram->phy; + + setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); + clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); + setbits_le32(PHY_REG(phy_base, 0x26), 1 << 4); + clrbits_le32(PHY_REG(phy_base, 0x27), 1 << 3); + setbits_le32(PHY_REG(phy_base, 0x36), 1 << 4); + clrbits_le32(PHY_REG(phy_base, 0x37), 1 << 3); + setbits_le32(PHY_REG(phy_base, 0x46), 1 << 4); + clrbits_le32(PHY_REG(phy_base, 0x47), 1 << 3); + setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4); + clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3); + + if (freq <= (400 * MHz)) + /* DLL bypass */ + setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); + else + clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); + if (freq <= (680 * MHz)) + tmp = 2; + else + tmp = 1; + writel(tmp, PHY_REG(phy_base, 0x28)); + writel(tmp, PHY_REG(phy_base, 0x38)); + writel(tmp, PHY_REG(phy_base, 0x48)); + writel(tmp, PHY_REG(phy_base, 0x58)); +} + +static void set_ds_odt(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + u32 cmd_drv, clk_drv, dqs_drv, dqs_odt; + void __iomem *phy_base = dram->phy; + + if (sdram_params->dramtype == DDR3) { + cmd_drv = PHY_DDR3_RON_RTT_34ohm; + clk_drv = PHY_DDR3_RON_RTT_45ohm; + dqs_drv = PHY_DDR3_RON_RTT_34ohm; + dqs_odt = PHY_DDR3_RON_RTT_225ohm; + } else { + cmd_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm; + clk_drv = PHY_DDR4_LPDDR3_RON_RTT_43ohm; + dqs_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm; + dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_240ohm; + } + /* DS */ + writel(cmd_drv, PHY_REG(phy_base, 0x11)); + clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3); + writel(clk_drv, PHY_REG(phy_base, 0x16)); + writel(clk_drv, PHY_REG(phy_base, 0x18)); + writel(dqs_drv, PHY_REG(phy_base, 0x20)); + writel(dqs_drv, PHY_REG(phy_base, 0x2f)); + writel(dqs_drv, PHY_REG(phy_base, 0x30)); + writel(dqs_drv, PHY_REG(phy_base, 0x3f)); + writel(dqs_drv, PHY_REG(phy_base, 0x40)); + writel(dqs_drv, PHY_REG(phy_base, 0x4f)); + writel(dqs_drv, PHY_REG(phy_base, 0x50)); + writel(dqs_drv, PHY_REG(phy_base, 0x5f)); + /* ODT */ + writel(dqs_odt, PHY_REG(phy_base, 0x21)); + writel(dqs_odt, PHY_REG(phy_base, 0x2e)); + writel(dqs_odt, PHY_REG(phy_base, 0x31)); + writel(dqs_odt, PHY_REG(phy_base, 0x3e)); + writel(dqs_odt, PHY_REG(phy_base, 0x41)); + writel(dqs_odt, PHY_REG(phy_base, 0x4e)); + writel(dqs_odt, PHY_REG(phy_base, 0x51)); + writel(dqs_odt, PHY_REG(phy_base, 0x5e)); +} + +static void phy_cfg(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + u32 i; + void __iomem *phy_base = dram->phy; + + phy_dll_bypass_set(dram, sdram_params->ddr_freq); + for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) { + writel(sdram_params->phy_regs.phy[i][1], + phy_base + sdram_params->phy_regs.phy[i][0]); + } + if (sdram_ch.bw == 2) { + clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4); + } else { + clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4); + /* disable DQS2,DQS3 tx dll for saving power */ + clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); + clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); + } + set_ds_odt(dram, sdram_params); + /* deskew */ + setbits_le32(PHY_REG(phy_base, 2), 8); + copy_to_reg(PHY_REG(phy_base, 0xb0), + &sdram_params->skew.a0_a1_skew[0], 15 * 4); + copy_to_reg(PHY_REG(phy_base, 0x70), + &sdram_params->skew.cs0_dm0_skew[0], 44 * 4); + copy_to_reg(PHY_REG(phy_base, 0xc0), + &sdram_params->skew.cs0_dm1_skew[0], 44 * 4); +} + +static int update_refresh_reg(struct dram_info *dram) +{ + void __iomem *pctl_base = dram->pctl; + u32 ret; + + ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1); + writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3); + + return 0; +} + +static int data_training(struct dram_info *dram, u32 cs, u32 dramtype) +{ + u32 ret; + u32 dis_auto_zq = 0; + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + + /* disable zqcs */ + if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) & + (1ul << 31))) { + dis_auto_zq = 1; + setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31); + } + /* disable auto refresh */ + setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1); + update_refresh_reg(dram); + + if (dramtype == DDR4) { + clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0); + clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0); + clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0); + clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0); + } + /* choose training cs */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs)); + /* enable gate training */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1); + udelay(50); + ret = readl(PHY_REG(phy_base, 0xff)); + /* disable gate training */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0); + /* restore zqcs */ + if (dis_auto_zq) + clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31); + /* restore auto refresh */ + clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1); + update_refresh_reg(dram); + + if (dramtype == DDR4) { + clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2); + clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2); + clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2); + clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2); + } + + if (ret & 0x10) { + ret = -1; + } else { + ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4); + ret = (ret == 0) ? 0 : -1; + } + return ret; +} + +/* rank = 1: cs0 + * rank = 2: cs1 + * rank = 3: cs0 & cs1 + * note: be careful of keep mr original val + */ +static int write_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 arg, + u32 dramtype) +{ + void __iomem *pctl_base = dram->pctl; + + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + continue; + if (dramtype == DDR3 || dramtype == DDR4) { + writel((mr_num << 12) | (rank << 4) | (0 << 0), + pctl_base + DDR_PCTL2_MRCTRL0); + writel(arg, pctl_base + DDR_PCTL2_MRCTRL1); + } else { + writel((rank << 4) | (0 << 0), + pctl_base + DDR_PCTL2_MRCTRL0); + writel((mr_num << 8) | (arg & 0xff), + pctl_base + DDR_PCTL2_MRCTRL1); + } + + setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); + while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) + continue; + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + continue; + + return 0; +} + +/* + * rank : 1:cs0, 2:cs1, 3:cs0&cs1 + * vrefrate: 4500: 45%, + */ +static int write_vrefdq(struct dram_info *dram, u32 rank, u32 vrefrate, + u32 dramtype) +{ + u32 tccd_l, value; + u32 dis_auto_zq = 0; + void __iomem *pctl_base = dram->pctl; + + if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9200) + return -1; + + tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf; + tccd_l = (tccd_l - 4) << 10; + + if (vrefrate > 7500) { + /* range 1 */ + value = ((vrefrate - 6000) / 65) | tccd_l; + } else { + /* range 2 */ + value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6); + } + + /* disable zqcs */ + if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) & + (1ul << 31))) { + dis_auto_zq = 1; + setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31); + } + /* disable auto refresh */ + setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1); + update_refresh_reg(dram); + + /* enable vrefdq calibratin */ + write_mr(dram, rank, 6, value | (1 << 7), dramtype); + udelay(1);/* tvrefdqe */ + /* write vrefdq value */ + write_mr(dram, rank, 6, value | (1 << 7), dramtype); + udelay(1);/* tvref_time */ + write_mr(dram, rank, 6, value | (0 << 7), dramtype); + udelay(1);/* tvrefdqx */ + + /* restore zqcs */ + if (dis_auto_zq) + clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31); + /* restore auto refresh */ + clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1); + update_refresh_reg(dram); + + return 0; +} + +#define _MAX_(x, y) ((x) > (y) ? (x) : (y)) + +static void rx_deskew_switch_adjust(struct dram_info *dram) +{ + u32 i, deskew_val; + u32 gate_val = 0; + void __iomem *phy_base = dram->phy; + + for (i = 0; i < 4; i++) + gate_val = _MAX_(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); + + deskew_val = (gate_val >> 3) + 1; + deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val; + clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); + clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, + (deskew_val & 0x1c) << 2); +} + +#undef _MAX_ + +static void tx_deskew_switch_adjust(struct dram_info *dram) +{ + void __iomem *phy_base = dram->phy; + + clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); +} + +static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) +{ + writel(ddrconfig, &dram->msch->ddrconf); +} + +static void dram_all_config(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + u32 sys_reg = 0, tmp = 0; + + set_ddrconfig(dram, sdram_ch.ddrconfig); + + sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype); + sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.row_3_4, 0); + sys_reg |= SYS_REG_ENC_RANK(sdram_ch.rank, 0); + sys_reg |= SYS_REG_ENC_COL(sdram_ch.col, 0); + sys_reg |= SYS_REG_ENC_BK(sdram_ch.bk, 0); + SYS_REG_ENC_CS0_ROW(sdram_ch.cs0_row, sys_reg, tmp, 0); + if (sdram_ch.cs1_row) + SYS_REG_ENC_CS1_ROW(sdram_ch.cs1_row, sys_reg, tmp, 0); + sys_reg |= SYS_REG_ENC_BW(sdram_ch.bw, 0); + sys_reg |= SYS_REG_ENC_DBW(sdram_ch.dbw, 0); + + writel(sys_reg, &dram->grf->os_reg[2]); + + writel(sdram_ch.noc_timings.ddrtiming.d32, &dram->msch->ddrtiming); + + writel(sdram_ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); + writel(sdram_ch.noc_timings.readlatency, &dram->msch->readlatency); + + writel(sdram_ch.noc_timings.activate.d32, &dram->msch->activate); + writel(sdram_ch.noc_timings.devtodev.d32, &dram->msch->devtodev); + writel(sdram_ch.noc_timings.ddr4timing.d32, &dram->msch->ddr4_timing); + writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging0); + writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging1); + writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging2); + writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging3); + writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging4); + writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging5); +} + +static void enable_low_power(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + void __iomem *pctl_base = dram->pctl; + + /* enable upctl2 axi clock auto gating */ + writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]); + writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]); + /* enable upctl2 core clock auto gating */ + writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]); + /* enable sr, pd */ + if (PD_IDLE == 0) + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); + else + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); + if (SR_IDLE == 0) + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); + else + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); +} + +static int sdram_init(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params, u32 pre_init) +{ + void __iomem *pctl_base = dram->pctl; + + rkclk_ddr_reset(dram, 1, 1, 1, 1); + udelay(10); + /* + * dereset ddr phy psrstn to config pll, + * if using phy pll psrstn must be dereset + * before config pll + */ + rkclk_ddr_reset(dram, 1, 1, 1, 0); + rkclk_configure_ddr(dram, sdram_params); + if (pre_init == 0) { + switch (sdram_params->dramtype) { + case DDR3: + printf("DDR3\n"); + break; + case DDR4: + printf("DDR4\n"); + break; + case LPDDR3: + default: + printf("LPDDR3\n"); + break; + } + } + /* release phy srst to provide clk to ctrl */ + rkclk_ddr_reset(dram, 1, 1, 0, 0); + udelay(10); + phy_soft_reset(dram); + /* release ctrl presetn, and config ctl registers */ + rkclk_ddr_reset(dram, 1, 0, 0, 0); + pctl_cfg(dram, sdram_params); + sdram_ch.ddrconfig = calculate_ddrconfig(sdram_params); + set_ctl_address_map(dram, sdram_params); + phy_cfg(dram, sdram_params); + + /* enable dfi_init_start to init phy after ctl srstn deassert */ + setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4)); + rkclk_ddr_reset(dram, 0, 0, 0, 0); + /* wait for dfi_init_done and dram init complete */ + while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) + continue; + + /* do ddr gate training */ + if (data_training(dram, 0, sdram_params->dramtype) != 0) { + printf("data training error\n"); + return -1; + } + + if (sdram_params->dramtype == DDR4) + write_vrefdq(dram, 0x3, 5670, sdram_params->dramtype); + + if (pre_init == 0) { + rx_deskew_switch_adjust(dram); + tx_deskew_switch_adjust(dram); + } + + dram_all_config(dram, sdram_params); + enable_low_power(dram, sdram_params); + + return 0; +} + +static u64 dram_detect_cap(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params, + unsigned char channel) +{ + void __iomem *pctl_base = dram->pctl; + + /* + * for ddr3: ddrconf = 3 + * for ddr4: ddrconf = 12 + * for lpddr3: ddrconf = 3 + * default bw = 1 + */ + u32 bk, bktmp; + u32 col, coltmp; + u32 row, rowtmp, row_3_4; + void __iomem *test_addr, *test_addr1; + u32 dbw; + u32 cs; + u32 bw = 1; + u64 cap = 0; + u32 dram_type = sdram_params->dramtype; + u32 pwrctl; + + if (dram_type != DDR4) { + /* detect col and bk for ddr3/lpddr3 */ + coltmp = 12; + bktmp = 3; + rowtmp = 16; + + for (col = coltmp; col >= 9; col -= 1) { + writel(0, SDRAM_ADDR); + test_addr = (void __iomem *)(SDRAM_ADDR + + (1ul << (col + bw - 1ul))); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(SDRAM_ADDR) == 0)) + break; + } + if (col == 8) { + printf("col error\n"); + goto cap_err; + } + + test_addr = (void __iomem *)(SDRAM_ADDR + + (1ul << (coltmp + bktmp + bw - 1ul))); + writel(0, SDRAM_ADDR); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(SDRAM_ADDR) == 0)) + bk = 3; + else + bk = 2; + if (dram_type == LPDDR3) + dbw = 2; + else + dbw = 1; + } else { + /* detect bg for ddr4 */ + coltmp = 10; + bktmp = 4; + rowtmp = 17; + + col = 10; + bk = 2; + test_addr = (void __iomem *)(SDRAM_ADDR + + (1ul << (coltmp + bw + 1ul))); + writel(0, SDRAM_ADDR); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(SDRAM_ADDR) == 0)) + dbw = 0; + else + dbw = 1; + } + /* detect row */ + for (row = rowtmp; row > 12; row--) { + writel(0, SDRAM_ADDR); + test_addr = (void __iomem *)(SDRAM_ADDR + + (1ul << (row + bktmp + coltmp + bw - 1ul))); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(SDRAM_ADDR) == 0)) + break; + } + if (row == 12) { + printf("row error"); + goto cap_err; + } + /* detect row_3_4 */ + test_addr = SDRAM_ADDR; + test_addr1 = (void __iomem *)(SDRAM_ADDR + + (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul))); + + writel(0, test_addr); + writel(PATTERN, test_addr1); + if ((readl(test_addr) == 0) && + (readl(test_addr1) == PATTERN)) + row_3_4 = 0; + else + row_3_4 = 1; + + /* disable auto low-power */ + pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); + writel(0, pctl_base + DDR_PCTL2_PWRCTL); + + /* bw and cs detect using phy read gate training */ + if (data_training(dram, 1, dram_type) == 0) + cs = 1; + else + cs = 0; + + bw = 2; + + /* restore auto low-power */ + writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); + + sdram_ch.rank = cs + 1; + sdram_ch.col = col; + sdram_ch.bk = bk; + sdram_ch.dbw = dbw; + sdram_ch.bw = bw; + sdram_ch.cs0_row = row; + if (cs) + sdram_ch.cs1_row = row; + else + sdram_ch.cs1_row = 0; + sdram_ch.row_3_4 = row_3_4; + + if (dram_type == DDR4) + cap = 1llu << (cs + row + bk + col + ((dbw == 0) ? 2 : 1) + bw); + else + cap = 1llu << (cs + row + bk + col + bw); + + return cap; + +cap_err: + return 0; +} + +static u32 remodify_sdram_params(struct rk3328_sdram_params *sdram_params) +{ + u32 tmp = 0, tmp_adr = 0, i; + + for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) { + if (sdram_params->pctl_regs.pctl[i][0] == 0) { + tmp = sdram_params->pctl_regs.pctl[i][1];/* MSTR */ + tmp_adr = i; + } + } + + tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12)); + + switch (sdram_ch.dbw) { + case 2: + tmp |= (3ul << 30); + break; + case 1: + tmp |= (2ul << 30); + break; + case 0: + default: + tmp |= (1ul << 30); + break; + } + + if (sdram_ch.rank == 2) + tmp |= 3 << 24; + else + tmp |= 1 << 24; + + tmp |= (2 - sdram_ch.bw) << 12; + + sdram_params->pctl_regs.pctl[tmp_adr][1] = tmp; + + if (sdram_ch.bw == 2) + sdram_ch.noc_timings.ddrtiming.b.bwratio = 0; + else + sdram_ch.noc_timings.ddrtiming.b.bwratio = 1; + + return 0; +} + +static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params, + unsigned char channel) +{ + u32 ret = 0; + u32 cs1_bit; + void __iomem *test_addr, *cs1_addr; + u32 row, bktmp, coltmp, bw; + u32 ddrconf = sdram_ch.ddrconfig; + + if (sdram_ch.rank == 2) { + cs1_bit = addrmap[ddrconf][0] + 8; + + if (cs1_bit > 31) + goto out; + + cs1_addr = (void __iomem *)(1ul << cs1_bit); + if (cs1_bit < 20) + cs1_bit = 1; + else + cs1_bit = 0; + + if (sdram_params->dramtype == DDR4) { + if (sdram_ch.dbw == 0) + bktmp = sdram_ch.bk + 2; + else + bktmp = sdram_ch.bk + 1; + } else { + bktmp = sdram_ch.bk; + } + bw = sdram_ch.bw; + coltmp = sdram_ch.col; + + /* detect cs1 row */ + for (row = sdram_ch.cs0_row; row > 12; row--) { + test_addr = (void __iomem *)(SDRAM_ADDR + cs1_addr + + (1ul << (row + cs1_bit + bktmp + + coltmp + bw - 1ul))); + writel(0, SDRAM_ADDR + cs1_addr); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(SDRAM_ADDR + cs1_addr) == 0)) { + ret = row; + break; + } + } + } + +out: + return ret; +} + +static int sdram_init_detect(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + debug("Starting SDRAM initialization...\n"); + + memcpy(&sdram_ch, &sdram_params->ch, + sizeof(struct rk3328_sdram_channel)); + + sdram_init(dram, sdram_params, 1); + dram_detect_cap(dram, sdram_params, 0); + + /* modify bw, cs related timing */ + remodify_sdram_params(sdram_params); + /* reinit sdram by real dram cap */ + sdram_init(dram, sdram_params, 0); + + /* redetect cs1 row */ + sdram_ch.cs1_row = + dram_detect_cs1_row(sdram_params, 0); + + return 0; +} + +static int rk3328_dmc_init(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rockchip_dmc_plat *plat = dev_get_platdata(dev); + int ret; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3328_sdram_params *params = &plat->sdram_params; +#else + struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; + struct rk3328_sdram_params *params = + (void *)dtplat->rockchip_sdram_params; + + ret = conv_of_platdata(dev); + if (ret) + return ret; +#endif + priv->phy = regmap_get_range(plat->map, 0); + priv->pctl = regmap_get_range(plat->map, 1); + priv->grf = regmap_get_range(plat->map, 2); + priv->cru = regmap_get_range(plat->map, 3); + priv->msch = regmap_get_range(plat->map, 4); + priv->ddr_grf = regmap_get_range(plat->map, 5); + + debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n", + __func__, priv->phy, priv->pctl, priv->grf, priv->cru, + priv->msch, priv->ddr_grf); + ret = sdram_init_detect(priv, params); + if (ret < 0) { + printf("%s DRAM init failed%d\n", __func__, ret); + return ret; + } + + return 0; +} + +static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_dmc_plat *plat = dev_get_platdata(dev); + int ret; + + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)&plat->sdram_params, + sizeof(plat->sdram_params) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params %d\n", + __func__, ret); + return ret; + } + ret = regmap_init_mem(dev, &plat->map); + if (ret) + printf("%s: regmap failed %d\n", __func__, ret); +#endif + return 0; +} + +#endif + static int rk3328_dmc_probe(struct udevice *dev) { +#ifdef CONFIG_TPL_BUILD + if (rk3328_dmc_init(dev)) + return 0; +#else struct dram_info *priv = dev_get_priv(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); @@ -25,7 +1032,7 @@ static int rk3328_dmc_probe(struct udevice *dev) priv->info.base = CONFIG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[2]); - +#endif return 0; } @@ -42,7 +1049,6 @@ static struct ram_ops rk3328_dmc_ops = { .get_info = rk3328_dmc_get_info, }; - static const struct udevice_id rk3328_dmc_ids[] = { { .compatible = "rockchip,rk3328-dmc" }, { } @@ -53,6 +1059,12 @@ U_BOOT_DRIVER(dmc_rk3328) = { .id = UCLASS_RAM, .of_match = rk3328_dmc_ids, .ops = &rk3328_dmc_ops, +#ifdef CONFIG_TPL_BUILD + .ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata, +#endif .probe = rk3328_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), +#ifdef CONFIG_TPL_BUILD + .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), +#endif }; diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index b4ddd1bdc6..dacf36bf79 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -18,6 +18,9 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define FDT_MODULE "apalis-v1.2" +#define FDT_MODULE_V1_0 "apalis" + /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ CONFIG_TDX_CFG_BLOCK_OFFSET) @@ -42,7 +45,7 @@ #define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \ "boot part 0 1 mmcpart 0; " \ "rootfs part 0 2 mmcpart 0; " \ - "uImage fat 0 1 mmcpart 0; " \ + "zImage fat 0 1 mmcpart 0; " \ "tegra124-apalis-eval.dtb fat 0 1 mmcpart 0" #define EMMC_BOOTCMD \ @@ -54,11 +57,11 @@ "run emmcdtbload; " \ "load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} - ${dtbparam}\0" \ + "bootz ${kernel_addr_r} - ${dtbparam}\0" \ "emmcbootpart=1\0" \ "emmcdev=0\0" \ "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \ - "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb && " \ + "${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb && " \ "setenv dtbparam ${fdt_addr_r}\0" \ "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \ "emmcrootpart=2\0" @@ -68,9 +71,9 @@ "nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \ "${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootm ${kernel_addr_r} - ${dtbparam}\0" \ + "&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \ - "${soc}-apalis-${fdt_board}.dtb " \ + "${soc}-${fdt_module}-${fdt_board}.dtb " \ "&& setenv dtbparam ${fdt_addr_r}\0" #define SD_BOOTCMD \ @@ -81,44 +84,28 @@ "${vidargs}; echo Booting from SD card in 8bit slot...; " \ "run sddtbload; load mmc ${sddev}:${sdbootpart} " \ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} - ${dtbparam}\0" \ + "bootz ${kernel_addr_r} - ${dtbparam}\0" \ "sdbootpart=1\0" \ "sddev=1\0" \ "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \ - "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb " \ + "${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb " \ "&& setenv dtbparam ${fdt_addr_r}\0" \ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \ "sdrootpart=2\0" -#define USB_BOOTCMD \ - "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} ro " \ - "rootfstype=ext4 rootwait\0" \ - "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \ - "setenv bootargs ${defargs} ${setupargs} " \ - "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ - "run usbdtbload; load usb ${usbdev}:${usbbootpart} " \ - "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} - ${dtbparam}\0" \ - "usbbootpart=1\0" \ - "usbdev=0\0" \ - "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \ - "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb " \ - "&& setenv dtbparam ${fdt_addr_r}\0" \ - "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \ - "usbrootpart=2\0" - #define BOARD_EXTRA_ENV_SETTINGS \ - "boot_file=uImage\0" \ + "boot_file=zImage\0" \ "console=ttyS0\0" \ "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \ - "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0\0" \ + "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \ + "user_debug=30 pcie_aspm=off\0" \ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ EMMC_BOOTCMD \ "fdt_board=eval\0" \ "fdt_fixup=;\0" \ + "fdt_module=" FDT_MODULE "\0" \ NFS_BOOTCMD \ SD_BOOTCMD \ - USB_BOOTCMD \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ "flash_eth.img && source ${loadaddr}\0" \ @@ -135,8 +122,7 @@ "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ - USB_BOOTCMD \ - "vidargs=video=tegrafb0:640x480-16@60 fbcon=map:1\0" + "vidargs=fbcon=map:1\0" /* Increase console I/O buffer size */ #undef CONFIG_SYS_CBSIZE diff --git a/test/py/tests/test_mmc_wr.py b/test/py/tests/test_mmc_wr.py index 601279a6a4..7678c3c9c1 100644 --- a/test/py/tests/test_mmc_wr.py +++ b/test/py/tests/test_mmc_wr.py @@ -35,7 +35,7 @@ env__mmc_wr_configs = ( """ -@pytest.mark.buildconfigspec('cmd_mmc','cmd_memory') +@pytest.mark.buildconfigspec('cmd_mmc','cmd_random') def test_mmc_wr(u_boot_console, env__mmc_wr_config): """Test the "mmc write" command. |