diff options
147 files changed, 72 insertions, 9276 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 053f816db5..0fa92479b4 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2019 ubuntu_vm: ubuntu-22.04 macos_vm: macOS-12 - ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220302-15Mar2022 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20220801-09Aug2022 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -170,13 +170,11 @@ stages: vmImage: $(ubuntu_vm) steps: - script: | - cat << EOF > build.sh - set -ex - cd ${WORK_DIR} - EOF - cat << "EOF" >> build.sh + cat << "EOF" > build.sh + cd $(work_dir) git config --global user.name "Azure Pipelines" git config --global user.email bmeng.cn@gmail.com + git config --global --add safe.directory $(work_dir) export USER=azure virtualenv -p /usr/bin/python3 /tmp/venv . /tmp/venv/bin/activate @@ -185,6 +183,7 @@ stages: export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH} ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl + set -ex ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test ./tools/buildman/buildman -t ./tools/dtoc/dtoc -t @@ -217,7 +216,7 @@ stages: options: $(container_option) steps: - script: | - cd ${WORK_DIR} + git config --global --add safe.directory $(work_dir) export USER=azure pip install -r test/py/requirements.txt pip install asteval pylint==2.12.2 pyopenssl @@ -226,6 +225,7 @@ stages: echo "load-plugins=pylint.extensions.docparams" >> .pylintrc export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl + set -ex pylint --version export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt make pylint_err @@ -514,20 +514,8 @@ stages: BUILDMAN: "m68k" mips: BUILDMAN: "mips" - non_fsl_ppc: - BUILDMAN: "powerpc -x freescale" - mpc85xx_freescale: - BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x bsc91*" - t208xrdb_corenet_ds: - BUILDMAN: "t208xrdb corenet_ds" - fsl_ppc: - BUILDMAN: "mpc83xx&freescale" - t102x: - BUILDMAN: "t102*" - p1_p2_rdb_pc: - BUILDMAN: "p1_p2_rdb_pc" - p1010rdb_bsc91: - BUILDMAN: "p1010rdb bsc91" + powerpc: + BUILDMAN: "powerpc" siemens: BUILDMAN: "siemens" tegra: diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a516c5d4ee..5592862f74 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found at: # https://source.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:focal-20220302-15Mar2022 +image: trini/u-boot-gitlab-ci-runner:jammy-20220801-09Aug2022 # We run some tests in different order, to catch some failures quicker. stages: @@ -199,6 +199,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites: script: - git config --global user.name "GitLab CI Runner"; git config --global user.email trini@konsulko.com; + git config --global --add safe.directory "${CI_PROJECT_DIR}"; export USER=gitlab; virtualenv -p /usr/bin/python3 /tmp/venv; . /tmp/venv/bin/activate; @@ -206,8 +207,10 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites: export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl; export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"; export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"; + set +e; ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl; + set -e; ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test; ./tools/buildman/buildman -t; ./tools/dtoc/dtoc -t; @@ -224,14 +227,17 @@ Run tests for Nokia RX-51 (aka N900): Run pylint: stage: testsuites script: + - git config --global --add safe.directory "${CI_PROJECT_DIR}" - pip install -r test/py/requirements.txt - pip install asteval pylint==2.12.2 pyopenssl - export PATH=${PATH}:~/.local/bin - echo "[MASTER]" >> .pylintrc - echo "load-plugins=pylint.extensions.docparams" >> .pylintrc - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl + - set +e - ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl + - set -e - pylint --version - export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt" - make pylint_err @@ -1151,7 +1151,6 @@ ifneq ($(CONFIG_DM),y) endif $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) - $(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET)) $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY)) $(call deprecated,CONFIG_DM_KEYBOARD,Keyboard drivers,v2022.10,$(CONFIG_KEYBOARD)) @# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 2fa7ebf163..427de1cb33 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -671,7 +671,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) "clock-frequency", get_qman_freq(), 1); #endif -#ifdef CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_FMAN_ENET fdt_fixup_fman_firmware(blob); #endif #ifdef CONFIG_FSL_PFE diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 32d68cbeb8..dc414c7d84 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -26,9 +26,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } -/* Ethernet */ -#define LPC32XX_ETH_BASE ETHERNET_BASE - /* NAND */ #if defined(CONFIG_NAND_LPC32XX_SLC) #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index eceb730856..ec560fe257 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -640,11 +640,6 @@ config TARGET_WANDBOARD select BOARD_LATE_INIT select SUPPORT_SPL -config TARGET_WARP - bool "WaRP" - depends on MX6SL - select BOARD_LATE_INIT - config TARGET_BRPPT2 bool "brppt2" depends on MX6QDL @@ -724,7 +719,6 @@ source "board/k+p/kp_imx6q_tpc/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" -source "board/warp/Kconfig" source "board/BuR/brppt2/Kconfig" source "board/out4/o4-imx6ull-nano/Kconfig" diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index c2586d0929..a97f9a1958 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -59,11 +59,3 @@ int print_cpuinfo(void) return 0; } #endif - -#ifdef CONFIG_LPC32XX_ETH -int cpu_eth_init(struct bd_info *bis) -{ - lpc32xx_eth_initialize(bis); - return 0; -} -#endif diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fa41047476..914d43b049 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -207,7 +207,6 @@ source "board/siemens/rut/Kconfig" source "board/ti/ti816x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/am335x/Kconfig" -source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" source "board/phytec/phycore_am335x_r2/Kconfig" diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index bd6b086552..987ab367ec 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -125,13 +125,6 @@ config TARGET_CHILIBOARD select DM_SERIAL imply CMD_DM -config TARGET_CM_T335 - bool "Support cm_t335" - select DM - select DM_GPIO - select DM_SERIAL - imply CMD_DM - config TARGET_DRACO bool "Support draco" select BOARD_LATE_INIT diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index b8b45a048c..e677211b2e 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -6,21 +6,8 @@ config 88F5182 config FEROCEON bool -choice - prompt "Marvell Orion board select" - optional - -config TARGET_EDMINIV2 - bool "LaCie Ethernet Disk mini V2" - select 88F5182 - select FEROCEON - select SUPPORT_SPL - -endchoice - config SYS_SOC default "orion5x" -source "board/LaCie/edminiv2/Kconfig" endif diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index ea98bb00f3..a07eff71df 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -50,9 +50,6 @@ choice prompt "Renesas ARM SoCs board select" optional -config TARGET_ARMADILLO_800EVA - bool "armadillo 800 eva board" - config TARGET_BLANCHE bool "Blanche board" select DM @@ -86,9 +83,6 @@ config TARGET_LAGER select SPL_USE_TINY_PRINTF imply CMD_DM -config TARGET_KZM9G - bool "KZM9D board" - config TARGET_ALT bool "Alt board" select DM @@ -156,12 +150,10 @@ config QOS_PRI_GFX endchoice -source "board/atmark-techno/armadillo-800eva/Kconfig" source "board/renesas/blanche/Kconfig" source "board/renesas/gose/Kconfig" source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" -source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" source "board/renesas/silk/Kconfig" source "board/renesas/porter/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 9d24f029b3..ec3405e967 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -132,15 +132,6 @@ config ARCH_MPC8308 select MPC83XX_PCIE1_SUPPORT select MPC83XX_SECOND_I2C -config ARCH_MPC8309 - bool - select ARCH_MPC830X - select MPC83XX_QUICC_ENGINE - select MPC83XX_PCI_SUPPORT - select MPC83XX_SECOND_I2C - select SYS_FSL_ERRATUM_ESDHC111 - select FSL_ELBC - config ARCH_MPC831X bool select MPC83XX_PCI_SUPPORT diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig index 71fa73801a..b67ccd661d 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -160,10 +160,6 @@ config QUICC_VCO_DIVIDER_2 config QUICC_VCO_DIVIDER_4 bool "4" -config QUICC_VCO_DIVIDER_8 - depends on ARCH_MPC8309 - bool "8" - endchoice choice @@ -399,14 +395,6 @@ config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM depends on ARCH_MPC837X bool "PCI2" -config BOOT_ROM_INTERFACE_ESDHC - depends on ARCH_MPC8309 - bool "eSDHC" - -config BOOT_ROM_INTERFACE_SPI - depends on ARCH_MPC8309 - bool "SPI" - config BOOT_ROM_INTERFACE_GPCM_8BIT bool "Local bus GPCM - 8-bit ROM" @@ -623,8 +611,6 @@ config BOOT_ROM_INTERFACE hex default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM default 0x4 if BOOT_ROM_INTERFACE_PCI1 - default 0x8 if BOOT_ROM_INTERFACE_ESDHC - default 0xc if BOOT_ROM_INTERFACE_SPI default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT @@ -676,12 +662,8 @@ config LDP_PIN_MUX_STATE config QUICC_VCO_DIVIDER int default 0 if !MPC83XX_QUICC_ENGINE - default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309 - default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309 - default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309 default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360) default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360) - default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360 config QUICC_DIV_FACTOR int diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr index e6b6130de2..86c5f42dd3 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr @@ -1,6 +1,6 @@ menu "LCRR - Clock Ratio Register register" -if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X +if !ARCH_MPC831X && !ARCH_MPC832X choice prompt "DLL bypass" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index f835263f25..b7a87fec2f 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -93,8 +93,6 @@ int get_clocks(void) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -#elif defined(CONFIG_ARCH_MPC8309) - u32 usbdr_clk; #endif #ifdef CONFIG_ARCH_MPC834X u32 usbmph_clk; @@ -107,9 +105,7 @@ int get_clocks(void) #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif -#if !defined(CONFIG_ARCH_MPC8309) u32 enc_clk; -#endif u32 lbiu_clk; u32 lclk_clk; u32 mem_clk; @@ -252,7 +248,6 @@ int get_clocks(void) return -6; } #endif -#if !defined(CONFIG_ARCH_MPC8309) switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { case 0: enc_clk = 0; @@ -270,7 +265,6 @@ int get_clocks(void) /* unknown SCCR_ENCCM value */ return -7; } -#endif #if defined(CONFIG_FSL_ESDHC) switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) { @@ -304,8 +298,6 @@ int get_clocks(void) i2c1_clk = sdhc_clk; #elif defined(CONFIG_ARCH_MPC837X) i2c1_clk = enc_clk; -#elif defined(CONFIG_ARCH_MPC8309) - i2c1_clk = csb_clk; #endif #if !defined(CONFIG_ARCH_MPC832X) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ @@ -434,8 +426,6 @@ int get_clocks(void) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; -#elif defined(CONFIG_ARCH_MPC8309) - gd->arch.usbdr_clk = usbdr_clk; #endif #if defined(CONFIG_ARCH_MPC834X) gd->arch.usbmph_clk = usbmph_clk; @@ -448,9 +438,7 @@ int get_clocks(void) #if !defined(CONFIG_ARCH_MPC832X) gd->arch.i2c2_clk = i2c2_clk; #endif -#if !defined(CONFIG_ARCH_MPC8309) gd->arch.enc_clk = enc_clk; -#endif gd->arch.lbiu_clk = lbiu_clk; gd->arch.lclk_clk = lclk_clk; gd->mem_clk = mem_clk; @@ -524,10 +512,8 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc, printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->arch.mem_sec_clk)); #endif -#if !defined(CONFIG_ARCH_MPC8309) printf(" SEC: %-4s MHz\n", strmhz(buf, gd->arch.enc_clk)); -#endif printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->arch.i2c1_clk)); #if !defined(CONFIG_ARCH_MPC832X) @@ -546,9 +532,6 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc, strmhz(buf, gd->arch.tsec2_clk)); printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); -#elif defined(CONFIG_ARCH_MPC8309) - printf(" USB DR: %-4s MHz\n", - strmhz(buf, gd->arch.usbdr_clk)); #endif #if defined(CONFIG_ARCH_MPC834X) printf(" USB MPH: %-4s MHz\n", diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 81f7991268..085ddd8439 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1444,7 +1444,6 @@ config FSL_VIA bool source "board/emulation/qemu-ppce500/Kconfig" -source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" source "board/freescale/p1010rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" diff --git a/arch/powerpc/dts/km8309-uboot.dtsi b/arch/powerpc/dts/km8309-uboot.dtsi deleted file mode 100644 index a93bdb2d00..0000000000 --- a/arch/powerpc/dts/km8309-uboot.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Hitachi Power Grids 8309 U-Boot specific Device Tree Source parts - * - * Copyright (C) 2020 Heiko Schocher <hs@denx.de> - * - */ - -/ { - cpus { - u-boot,dm-pre-reloc; - PowerPC,8309@0 { - u-boot,dm-pre-reloc; - }; - }; - - chosen { - stdout-path = &serial0; - }; -}; - -&qe { - compatible = "fsl,qe", "simple-bus"; -}; - -&soc { - u-boot,dm-pre-reloc; -}; - -&serial0 { - clock-frequency = <132000000>; - u-boot,dm-pre-reloc; -}; diff --git a/arch/powerpc/dts/kmtegr1.dts b/arch/powerpc/dts/kmtegr1.dts deleted file mode 100644 index d40d9716e5..0000000000 --- a/arch/powerpc/dts/kmtegr1.dts +++ /dev/null @@ -1,392 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Hitachi Power Grids TEGR1 Device Tree Source - * - * Copyright (C) 2020 Heiko Schocher <hs@denx.de> - * - */ - -/dts-v1/; - -/ { - model = "KMTEGR1"; - compatible = "hitachi,kmpbec8309"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - ethernet0 = &enet_zynq; - ethernet1 = &enet_piggy2; - serial0 = &serial0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,8309@0 { - device_type = "cpu"; - reg = <0x0>; - d-cache-line-size = <32>; // 32 bytes - i-cache-line-size = <32>; // 32 bytes - d-cache-size = <16384>; // L1, 16K - i-cache-size = <16384>; // L1, 16K - timebase-frequency = <66000000>; - bus-frequency = <264000000>; - clock-frequency = <264000000>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - soc: soc8309@e0000000 { - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "simple-bus"; - ranges = <0x0 0xe0000000 0x00100000>; - reg = <0xe0000000 0x00000200>; - bus-frequency = <264000000>; - - i2c@3000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl,mpc8313-i2c","fsl-i2c"; - reg = <0x3000 0x100>; - interrupts = <14 0x8>; - interrupt-parent = <&ipic>; - clock-frequency = <400000>; - - mux@70 { - compatible = "nxp,pca9547"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* - * Inventory EEPROM of the - * unit itself - */ - ivm@50 { - label = "MAIN_CTRL"; - compatible = "dummy"; - reg = <0x50>; - }; - }; - - i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - /* Temperature sensors */ - temp@48 { - label = "front"; - compatible = "national,lm75"; - reg = <0x48>; - }; - - temp@49 { - label = "board"; - compatible = "national,lm75"; - reg = <0x49>; - }; - - temp@4a { - label = "power"; - compatible = "national,lm75"; - reg = <0x4a>; - }; - - temp@4b { - label = "bottom"; - compatible = "national,lm75"; - reg = <0x4b>; - }; - }; - - i2c@6 { - reg = <6>; - #address-cells = <1>; - #size-cells = <0>; - - }; - - i2c@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - - }; - - i2c@7 { - reg = <7>; - #address-cells = <1>; - #size-cells = <0>; - - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - }; - }; - }; - - serial0: serial@4500 { - cell-index = <0>; - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550"; - reg = <0x4500 0x100>; - clock-frequency = <264000000>; - interrupts = <9 0x8>; - interrupt-parent = <&ipic>; - }; - - dma@82a8 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8309-dma", "fsl,elo-dma"; - reg = <0x82a8 4>; - ranges = <0 0x8100 0x1a8>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,mpc8309-dma-channel", - "fsl,elo-dma-channel"; - reg = <0 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@80 { - compatible = "fsl,mpc8309-dma-channel", - "fsl,elo-dma-channel"; - reg = <0x80 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@100 { - compatible = "fsl,mpc8309-dma-channel", - "fsl,elo-dma-channel"; - reg = <0x100 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@180 { - compatible = "fsl,mpc8309-dma-channel", - "fsl,elo-dma-channel"; - reg = <0x180 0x28>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - }; - - ipic: pic@700 { - #address-cells = <0>; - #interrupt-cells = <2>; - compatible = "fsl,pq2pro-pic", "fsl,ipic"; - interrupt-controller; - reg = <0x700 0x100>; - device_type = "ipic"; - }; - - gpio1: gpio-controller@c00 { - #gpio-cells = <2>; - compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio"; - reg = <0xc00 0x100>; - interrupts = <75 0x8>; - interrupt-parent = <&ipic>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio-controller@d00 { - #gpio-cells = <2>; - compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio"; - reg = <0xd00 0x100>; - interrupts = <75 0x8>; - interrupt-parent = <&ipic>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi@7000 { - cell-index = <0>; - compatible = "fsl,spi"; - reg = <0x7000 0x1000>; - interrupts = <16 0x8>; - interrupt-parent = <&ipic>; - mode = "cpu"; - #address-cells = <1>; - #size-cells = <0>; - - /* GPIO_15 chipselect for ZYNQ flash */ - gpios = <&gpio1 15 0>; - - zynq_flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,m25p80"; - reg = <0>; - spi-max-frequency = <4000000>; - m25p,fast-read; - partition@0 { - label = "bootloader"; - reg = <0x0 0x01000000>; - }; - }; - }; - }; - - qe: qe@e0100000 { - #address-cells = <1>; - #size-cells = <1>; - device_type = "qe"; - compatible = "fsl,qe"; - ranges = <0x0 0xe0100000 0x00100000>; - reg = <0xe0100000 0x480>; - brg-frequency = <0>; - bus-frequency = <396000000>; - fsl,qe-num-snums = <32>; - - muram@10000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,qe-muram", "fsl,cpm-muram"; - ranges = <0x0 0x00010000 0x00004000>; - - data-only@0 { - compatible = "fsl,qe-muram-data", - "fsl,cpm-muram-data"; - reg = <0x0 0x4000>; - }; - }; - - /* ZYNQ (UCC1, MDIO 0x10, MII) */ - enet_zynq: ethernet@2000 { - device_type = "network"; - compatible = "ucc_geth"; - cell-index = <1>; - reg = <0x2000 0x200>; - interrupts = <32>; - interrupt-parent = <&qeic>; - local-mac-address = [ 00 00 00 00 00 00 ]; - /*id=0, full-dup, 100M, no-pause, no-asym_p*/ - fixed-link = <0 1 100 0 0>; - rx-clock-name = "clk9"; - tx-clock-name = "clk10"; - phy-connection-type = "mii"; - }; - - /* Piggy2 (UCC3, MDIO 0x00, RMII) */ - enet_piggy2: ucc@2200 { - device_type = "network"; - compatible = "ucc_geth"; - cell-index = <3>; - reg = <0x2200 0x200>; - interrupts = <34>; - interrupt-parent = <&qeic>; - local-mac-address = [ 00 00 00 00 00 00 ]; - rx-clock-name = "none"; - tx-clock-name = "clk12"; - phy-handle = <&phy_piggy2>; - phy-connection-type = "rmii"; - }; - - mdio@2320 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2320 0x38>; - compatible = "fsl,ucc-mdio"; - - /* Piggy2 (UCC3, MDIO 0x00, RMII) */ - phy_piggy2: ethernet-phy@0 { - reg = <0x0>; - device_type = "ethernet-phy"; - }; - - /* Explicitly set the tbi-phy to a non-zero address - * so that it does not conflict with phy_piggy2 that - * is unfortunately at address 0 - */ - tbi1: tbi-phy@1 { - reg = <0x1>; - device_type = "tbi-phy"; - }; - }; - - qeic: interrupt-controller@80 { - interrupt-controller; - compatible = "fsl,qe-ic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0x80 0x80>; - big-endian; - interrupts = <32 8 33 8>; - interrupt-parent = <&ipic>; - }; - bootcount@0x13ff8 { - device_type = "bootcount"; - compatible = "u-boot,bootcount"; - reg = <0x13ff8 0x08>; - }; - - }; - localbus@e0005000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus", - "simple-bus"; - reg = <0xe0005000 0xd8>; - ranges = <0 0 0xf0000000 0x04000000 - 1 0 0xe8000000 0x01000000 - 2 0 0xe0000000 0x10000000 - 3 0 0xb0000000 0x10000000>; - - flash@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x04000000>; - bank-width = <2>; - nornand = "nor"; - #address-cells = <1>; - #size-cells = <1>; - use-advanced-sector-protection; - partition@0 { /* 768KB */ - label = "u-boot"; - reg = <0 0xc0000>; - }; - partition@c0000 { /* 256KB */ - label = "qe-fw"; - reg = <0xc0000 0x40000>; - }; - partition@100000 { /* 128KB */ - label = "env"; - reg = <0x100000 0x20000>; - }; - partition@120000 { /* 128KB */ - label = "envred"; - reg = <0x120000 0x20000>; - }; - partition@140000 { /* 64256KB */ - label = "ubi0"; - reg = <0x140000 0x3EC0000>; - }; - }; - }; -}; - -#include "km8309-uboot.dtsi" diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index b740675183..19c2506c9b 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -8,8 +8,7 @@ */ #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) #define MPC83XX_GPIO_CTRLRS 1 -#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) || \ - defined(CONFIG_ARCH_MPC8309) +#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) #define MPC83XX_GPIO_CTRLRS 2 #else #define MPC83XX_GPIO_CTRLRS 0 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 770adcd30f..6709e692e6 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -32,8 +32,6 @@ struct arch_global_data { u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -# elif defined(CONFIG_ARCH_MPC8309) - u32 usbdr_clk; # endif # if defined(CONFIG_ARCH_MPC834X) u32 usbmph_clk; diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 6d1ddbcd27..c7313472de 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -64,14 +64,7 @@ typedef struct sysconf83xx { #else u32 pecr2; /* PCI Express control register 2 */ #endif -#if defined(CONFIG_ARCH_MPC8309) - u32 can_dbg_ctrl; - u32 res9a; - u32 gpr1; - u8 res9b[0xAC]; -#else u8 res9[0xB8]; -#endif } sysconf83xx_t; /* @@ -604,11 +597,7 @@ typedef struct serdes83xx { * On Chip ROM */ typedef struct rom83xx { -#if defined(CONFIG_ARCH_MPC8309) - u8 mem[0x8000]; -#else u8 mem[0x10000]; -#endif } rom83xx_t; /* @@ -857,55 +846,6 @@ typedef struct immap { u8 res8[0xC0000]; u8 qe[0x100000]; /* QE block */ } immap_t; -#elif defined(CONFIG_ARCH_MPC8309) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[2]; /* General purpose I/O module */ - u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */ - qepi83xx_t qepi; /* QE Ports Interrupts Registers */ - qepio83xx_t qepio; /* QE Parallel I/O ports */ - u8 res1[0x800]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res2[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res3[0x200]; - duart83xx_t duart1[2]; /* DUART */ - u8 res4[0x500]; - fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ - u8 res5[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */ - u8 res7[0x80]; - ios83xx_t ios; /* Sequencer (IOS) */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */ - u8 res8[0x13A00]; - u8 can1[0x1000]; /* Flexcan 1 */ - u8 can2[0x1000]; /* Flexcan 2 */ - u8 res9[0x5000]; - usb83xx_t usb; - u8 res10[0x5000]; - u8 can3[0x1000]; /* Flexcan 3 */ - u8 can4[0x1000]; /* Flexcan 4 */ - u8 res11[0x1000]; - u8 dma1[0x2000]; /* DMA */ - sdhc83xx_t sdhc; /* SDHC Controller */ - u8 res12[0xC1000]; - rom83xx_t rom; /* On Chip ROM */ - u8 res13[0x8000]; - u8 qe[0x100000]; /* QE block */ - u8 res14[0xE00000];/* Added for 8309 */ -} immap_t; #endif struct ccsr_gpio { diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index f2210a14ae..83cfe23b4e 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -11,7 +11,6 @@ #include <asm/types.h> #if defined(CONFIG_ARCH_MPC8308) || \ - defined(CONFIG_ARCH_MPC8309) || \ defined(CONFIG_ARCH_MPC8313) || \ defined(CONFIG_ARCH_MPC834X) || \ defined(CONFIG_ARCH_MPC837X) diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig deleted file mode 100644 index ac3fe3fbcb..0000000000 --- a/board/LaCie/edminiv2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_EDMINIV2 - -config SYS_BOARD - default "edminiv2" - -config SYS_VENDOR - default "LaCie" - -config SYS_CONFIG_NAME - default "edminiv2" - -endif diff --git a/board/LaCie/edminiv2/MAINTAINERS b/board/LaCie/edminiv2/MAINTAINERS deleted file mode 100644 index 055afd0e76..0000000000 --- a/board/LaCie/edminiv2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EDMINIV2 BOARD -M: Simon Guinot <simon.guinot@sequanux.org> -S: Maintained -F: board/LaCie/edminiv2/ -F: include/configs/edminiv2.h -F: configs/edminiv2_defconfig diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile deleted file mode 100644 index 5252c2b0e6..0000000000 --- a/board/LaCie/edminiv2/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> -# -# Based on original Kirkwood support which is -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> - -obj-y := edminiv2.o ../common/common.o diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c deleted file mode 100644 index 9c066a283c..0000000000 --- a/board/LaCie/edminiv2/edminiv2.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - */ - -#include <common.h> -#include <miiphy.h> -#include <net.h> -#include <asm/arch/orion5x.h> -#include <asm/global_data.h> -#include "../common/common.h" -#include <spl.h> -#include <ns16550.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* arch number of board */ - gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; - - /* boot parameter start at 256th byte of RAM base */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - - return 0; -} - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - mv_phy_88e1116_init("egiga0", 8); -} -#endif /* CONFIG_RESET_PHY_R */ - -/* - * SPL serial setup and NOR boot device selection - */ - -#ifdef CONFIG_SPL_BUILD - -void spl_board_init(void) -{ - preloader_console_init(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NOR; -} - -#endif /* CONFIG_SPL_BUILD */ diff --git a/board/atmark-techno/armadillo-800eva/Kconfig b/board/atmark-techno/armadillo-800eva/Kconfig deleted file mode 100644 index cd37dd4861..0000000000 --- a/board/atmark-techno/armadillo-800eva/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ARMADILLO_800EVA - -config SYS_BOARD - default "armadillo-800eva" - -config SYS_VENDOR - default "atmark-techno" - -config SYS_CONFIG_NAME - default "armadillo-800eva" - -endif diff --git a/board/atmark-techno/armadillo-800eva/MAINTAINERS b/board/atmark-techno/armadillo-800eva/MAINTAINERS deleted file mode 100644 index 6f547d82ec..0000000000 --- a/board/atmark-techno/armadillo-800eva/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ARMADILLO-800EVA BOARD -M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -S: Maintained -F: board/atmark-techno/armadillo-800eva/ -F: include/configs/armadillo-800eva.h -F: configs/armadillo-800eva_defconfig diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile deleted file mode 100644 index 7e01cb6794..0000000000 --- a/board/atmark-techno/armadillo-800eva/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - -obj-y += armadillo-800eva.o diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c deleted file mode 100644 index c1c3dfd3de..0000000000 --- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <malloc.h> -#include <asm/global_data.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/rmobile.h> - -#define s_init_wait(cnt) \ - ({ \ - volatile u32 i = 0x10000 * cnt; \ - while (i > 0) \ - i--; \ - }) - -#define USBCR1 0xE605810A - -void s_init(void) -{ - struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE; - struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE; - struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE; - struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE; - struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE; - struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE; - - /* Watchdog init */ - writew(0xA500, &rwdt0->rwtcsra0); - writew(0xA500, &rwdt1->rwtcsra0); - - /* CPG */ - writel(0xFF800080, &cpg->rmstpcr4); - writel(0xFF800080, &cpg->smstpcr4); - - /* USB clock */ - writel(0x00000080, &cpg->usbckcr); - s_init_wait(1); - - /* USBCR1 */ - writew(0x0710, USBCR1); - - /* FRQCR */ - writel(0x00000000, &cpg->frqcrb); - writel(0x62030533, &cpg->frqcra); - writel(0x208A354E, &cpg->frqcrc); - writel(0x80331050, &cpg->frqcrb); - s_init_wait(1); - - writel(0x00000000, &cpg->frqcrd); - s_init_wait(1); - - /* SUBClk */ - writel(0x0000010B, &cpg->subckcr); - - /* PLL */ - writel(0x00004004, &cpg->pllc01cr); - s_init_wait(1); - - writel(0xa0000000, &cpg->pllc2cr); - s_init_wait(2); - - /* BSC */ - writel(0x0000001B, &bsc->cmncr); - - writel(0x20000000, &dbsc->dbcmd); - writel(0x10009C40, &dbsc->dbcmd); - s_init_wait(1); - - writel(0x00000007, &dbsc->dbkind); - writel(0x0E030A02, &dbsc->dbconf0); - writel(0x00000001, &dbsc->dbphytype); - writel(0x00000000, &dbsc->dbbl); - writel(0x00000006, &dbsc->dbtr0); - writel(0x00000005, &dbsc->dbtr1); - writel(0x00000000, &dbsc->dbtr2); - writel(0x00000006, &dbsc->dbtr3); - writel(0x00080006, &dbsc->dbtr4); - writel(0x00000015, &dbsc->dbtr5); - writel(0x0000000f, &dbsc->dbtr6); - writel(0x00000004, &dbsc->dbtr7); - writel(0x00000018, &dbsc->dbtr8); - writel(0x00000006, &dbsc->dbtr9); - writel(0x00000006, &dbsc->dbtr10); - writel(0x0000000F, &dbsc->dbtr11); - writel(0x0000000D, &dbsc->dbtr12); - writel(0x000000A0, &dbsc->dbtr13); - writel(0x000A0003, &dbsc->dbtr14); - writel(0x00000003, &dbsc->dbtr15); - writel(0x40005005, &dbsc->dbtr16); - writel(0x0C0C0000, &dbsc->dbtr17); - writel(0x00000200, &dbsc->dbtr18); - writel(0x00000040, &dbsc->dbtr19); - writel(0x00000001, &dbsc->dbrnk0); - writel(0x00000110, &dbsc->dbdficnt); - writel(0x00000101, &ddrp->funcctrl); - writel(0x00000001, &ddrp->dllctrl); - writel(0x00000186, &ddrp->zqcalctrl); - writel(0xB3440051, &ddrp->zqodtctrl); - writel(0x94449443, &ddrp->rdctrl); - writel(0x000000C0, &ddrp->rdtmg); - writel(0x00000101, &ddrp->fifoinit); - writel(0x02060506, &ddrp->outctrl); - writel(0x00004646, &ddrp->dqcalofs1); - writel(0x00004646, &ddrp->dqcalofs2); - writel(0x800000aa, &ddrp->dqcalexp); - writel(0x00000000, &ddrp->dllctrl); - writel(0x00000000, DDRPNCNT); - - writel(0x0000000C, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000002, DDRPNCNT); - - writel(0x0000000C, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000187, &ddrp->zqcalctrl); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000010, &dbsc->dbdficnt); - writel(0x02060507, &ddrp->outctrl); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x21009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x11000044, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x2A000000, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x2B000000, &dbsc->dbcmd); - readl(&dbsc->dbwait); - - writel(0x29000004, &dbsc->dbcmd); - readl(&dbsc->dbwait); - - writel(0x28001520, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x03000200, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x000001FF, &dbsc->dbrfcnf0); - writel(0x00010C30, &dbsc->dbrfcnf1); - writel(0x00000000, &dbsc->dbrfcnf2); - - writel(0x00000001, &dbsc->dbrfen); - writel(0x00000001, &dbsc->dbacen); - - /* BSC */ - writel(0x00410400, &bsc->cs0bcr); - writel(0x00410400, &bsc->cs2bcr); - writel(0x00410400, &bsc->cs5bbcr); - writel(0x02CB0400, &bsc->cs6abcr); - - writel(0x00000440, &bsc->cs0wcr); - writel(0x00000440, &bsc->cs2wcr); - writel(0x00000240, &bsc->cs5bwcr); - writel(0x00000240, &bsc->cs6awcr); - - writel(0x00000005, &bsc->rbwtcnt); - writel(0x00000002, &bsc->cs0wcr2); - writel(0x00000002, &bsc->cs2wcr2); - writel(0x00000002, &bsc->cs4wcr2); -} - -#define GPIO_ICCR (0xE60581A0) -#define ICCR_15BIT (1 << 15) /* any time 1 */ -#define IIC0_CONTA (1 << 7) -#define IIC0_CONTB (1 << 6) -#define IIC1_CONTA (1 << 5) -#define IIC1_CONTB (1 << 4) -#define IIC0_PS33E (1 << 1) -#define IIC1_PS33E (1 << 0) -#define GPIO_ICCR_DATA \ - (ICCR_15BIT | \ - IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \ - IIC1_CONTB | IIC0_PS33E | IIC1_PS33E) - -#define MSTPCR1 0xE6150134 -#define TMU0_MSTP125 (1 << 25) -#define I2C0_MSTP116 (1 << 16) - -#define MSTPCR3 0xE615013C -#define I2C1_MSTP323 (1 << 23) -#define GETHER_MSTP309 (1 << 9) - -#define GPIO_SCIFA1_TXD (0xE60520C4) -#define GPIO_SCIFA1_RXD (0xE60520C3) - -int board_early_init_f(void) -{ - /* TMU */ - clrbits_le32(MSTPCR1, TMU0_MSTP125); - - /* GETHER */ - clrbits_le32(MSTPCR3, GETHER_MSTP309); - - /* I2C 0/1 */ - clrbits_le32(MSTPCR1, I2C0_MSTP116); - clrbits_le32(MSTPCR3, I2C1_MSTP323); - - /* SCIFA1 */ - writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */ - writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */ - - /* IICCR */ - writew(GPIO_ICCR_DATA, GPIO_ICCR); - - return 0; -} - -DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - /* board id for linux */ - gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA; - /* adress of boot parameters */ - gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100; - - /* Init PFC controller */ - r8a7740_pinmux_init(); - - /* GETHER Enable */ - gpio_request(GPIO_FN_ET_CRS, NULL); - gpio_request(GPIO_FN_ET_MDC, NULL); - gpio_request(GPIO_FN_ET_MDIO, NULL); - gpio_request(GPIO_FN_ET_TX_ER, NULL); - gpio_request(GPIO_FN_ET_RX_ER, NULL); - gpio_request(GPIO_FN_ET_ERXD0, NULL); - gpio_request(GPIO_FN_ET_ERXD1, NULL); - gpio_request(GPIO_FN_ET_ERXD2, NULL); - gpio_request(GPIO_FN_ET_ERXD3, NULL); - gpio_request(GPIO_FN_ET_TX_CLK, NULL); - gpio_request(GPIO_FN_ET_TX_EN, NULL); - gpio_request(GPIO_FN_ET_ETXD0, NULL); - gpio_request(GPIO_FN_ET_ETXD1, NULL); - gpio_request(GPIO_FN_ET_ETXD2, NULL); - gpio_request(GPIO_FN_ET_ETXD3, NULL); - gpio_request(GPIO_FN_ET_PHY_INT, NULL); - gpio_request(GPIO_FN_ET_COL, NULL); - gpio_request(GPIO_FN_ET_RX_DV, NULL); - gpio_request(GPIO_FN_ET_RX_CLK, NULL); - - gpio_request(GPIO_PORT18, NULL); /* PHY_RST */ - gpio_direction_output(GPIO_PORT18, 1); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} - -int board_late_init(void) -{ - return 0; -} - -void reset_cpu(void) -{ -} diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 018fed9cc2..a337db4efc 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -135,30 +135,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ -#ifdef CONFIG_KS8851_MLL -void at91sam9n12ek_ks8851_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[2].setup); - writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | - AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), - &smc->cs[2].pulse); - writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), - &smc->cs[2].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | - AT91_SMC_MODE_TDF_CYCLE(1), - &smc->cs[2].mode); - - /* Configure NCS2 PIN */ - at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0); -} -#endif - #ifdef CONFIG_USB_ATMEL void at91sam9n12ek_usb_hw_init(void) { @@ -193,10 +169,6 @@ int board_init(void) at91_lcd_hw_init(); #endif -#ifdef CONFIG_KS8851_MLL - at91sam9n12ek_ks8851_hw_init(); -#endif - #ifdef CONFIG_USB_ATMEL at91sam9n12ek_usb_hw_init(); #endif @@ -204,13 +176,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_KS8851_MLL -int board_eth_init(struct bd_info *bis) -{ - return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); -} -#endif - int dram_init(void) { gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig deleted file mode 100644 index 683efde764..0000000000 --- a/board/compulab/cm_t335/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_CM_T335 - -config SYS_BOARD - default "cm_t335" - -config SYS_VENDOR - default "compulab" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "cm_t335" - -endif diff --git a/board/compulab/cm_t335/MAINTAINERS b/board/compulab/cm_t335/MAINTAINERS deleted file mode 100644 index 5fb922c68b..0000000000 --- a/board/compulab/cm_t335/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM_T335 BOARD -M: Igor Grinberg <grinberg@compulab.co.il> -S: Maintained -F: board/compulab/cm_t335/ -F: include/configs/cm_t335.h -F: configs/cm_t335_defconfig diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile deleted file mode 100644 index 34f6713118..0000000000 --- a/board/compulab/cm_t335/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/ -# -# Author: Ilya Ledvich <ilya@compulab.co.il> - -obj-y += cm_t335.o -obj-$(CONFIG_SPL_BUILD) += mux.o spl.o diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c deleted file mode 100644 index 1d4a3aceef..0000000000 --- a/board/compulab/cm_t335/cm_t335.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Board functions for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich <ilya@compulab.co.il> - */ - -#include <common.h> -#include <env.h> -#include <errno.h> -#include <miiphy.h> -#include <net.h> -#include <status_led.h> -#include <cpsw.h> -#include <asm/global_data.h> -#include <linux/delay.h> - -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware_am33xx.h> -#include <asm/io.h> -#include <asm/gpio.h> - -#include "../common/eeprom.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - gpmc_init(); - -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF); -#endif - return 0; -} - -#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - return; -} - -static struct cpsw_slave_data cpsw_slave = { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = &cpsw_slave, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -/* PHY reset GPIO */ -#define GPIO_PHY_RST GPIO_PIN(3, 7) - -static void board_phy_init(void) -{ - gpio_request(GPIO_PHY_RST, "phy_rst"); - gpio_direction_output(GPIO_PHY_RST, 0); - mdelay(2); - gpio_set_value(GPIO_PHY_RST, 1); - mdelay(2); -} - -static void get_efuse_mac_addr(uchar *enetaddr) -{ - uint32_t mac_hi, mac_lo; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - enetaddr[0] = mac_hi & 0xFF; - enetaddr[1] = (mac_hi & 0xFF00) >> 8; - enetaddr[2] = (mac_hi & 0xFF0000) >> 16; - enetaddr[3] = (mac_hi & 0xFF000000) >> 24; - enetaddr[4] = mac_lo & 0xFF; - enetaddr[5] = (mac_lo & 0xFF00) >> 8; -} - -/* - * Routine: handle_mac_address - * Description: prepare MAC address for on-board Ethernet. - */ -static int handle_mac_address(void) -{ - uchar enetaddr[6]; - int rv; - - rv = eth_env_get_enetaddr("ethaddr", enetaddr); - if (rv) - return 0; - - rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); - if (rv) - get_efuse_mac_addr(enetaddr); - - if (!is_valid_ethaddr(enetaddr)) - return -1; - - return eth_env_set_enetaddr("ethaddr", enetaddr); -} - -#define AR8051_PHY_DEBUG_ADDR_REG 0x1d -#define AR8051_PHY_DEBUG_DATA_REG 0x1e -#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 -#define AR8051_RGMII_TX_CLK_DLY 0x100 - -int board_eth_init(struct bd_info *bis) -{ - int rv, n = 0; - const char *devname; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - rv = handle_mac_address(); - if (rv) - printf("No MAC address found!\n"); - - writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); - - board_phy_init(); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; - - /* - * CPSW RGMII Internal Delay Mode is not supported in all PVT - * operating points. So we must set the TX clock delay feature - * in the AR8051 PHY. Since we only support a single ethernet - * device, we only do this for the first instance. - */ - devname = miiphy_get_current_dev(); - - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, - AR8051_DEBUG_RGMII_CLK_DLY_REG); - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, - AR8051_RGMII_TX_CLK_DLY); - return n; -} -#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */ diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c deleted file mode 100644 index 1c326bd1b6..0000000000 --- a/board/compulab/cm_t335/mux.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Pinmux configuration for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich <ilya@compulab.co.il> - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mux.h> -#include <asm/io.h> - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, - {-1}, -}; - -static struct module_pin_mux uart1_pin_mux[] = { - {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, - {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)}, - {-1}, -}; - -static struct module_pin_mux mmc0_pin_mux[] = { - {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {-1}, -}; - -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux i2c1_pin_mux[] = { - /* I2C_DATA */ - {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - /* I2C_SCLK */ - {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux rgmii1_pin_mux[] = { - {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ - {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ - {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ - {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ - {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ - {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ - {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ - {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ - {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ - {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ - {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ - {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {-1}, -}; - -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; - -static struct module_pin_mux eth_phy_rst_pin_mux[] = { - {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */ - {-1}, -}; - -static struct module_pin_mux status_led_pin_mux[] = { - {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */ - {-1}, -}; - -void set_uart_mux_conf(void) -{ - configure_module_pin_mux(uart0_pin_mux); - configure_module_pin_mux(uart1_pin_mux); -} - -void set_mux_conf_regs(void) -{ - configure_module_pin_mux(i2c0_pin_mux); - configure_module_pin_mux(i2c1_pin_mux); - configure_module_pin_mux(rgmii1_pin_mux); - configure_module_pin_mux(eth_phy_rst_pin_mux); - configure_module_pin_mux(mmc0_pin_mux); - configure_module_pin_mux(nand_pin_mux); - configure_module_pin_mux(status_led_pin_mux); -} diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c deleted file mode 100644 index 33264dfa71..0000000000 --- a/board/compulab/cm_t335/spl.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL specific code for Compulab CM-T335 board - * - * Board functions for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich <ilya@compulab.co.il> - */ - -#include <common.h> -#include <cpu_func.h> -#include <errno.h> -#include <init.h> -#include <log.h> - -#include <asm/arch/ddr_defs.h> -#include <asm/arch/clock.h> -#include <asm/arch/clocks_am33xx.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware_am33xx.h> -#include <linux/sizes.h> - -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, - .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, - .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, - .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, - .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, -}; - -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41J128MJT125_RD_DQS, - .datawdsratio0 = MT41J128MJT125_WR_DQS, - .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, - .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41J128MJT125_RATIO, - .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, - - .cmd1csratio = MT41J128MJT125_RATIO, - .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, - - .cmd2csratio = MT41J128MJT125_RATIO, - .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41J128MJT125_EMIF_SDCFG, - .ref_ctrl = MT41J128MJT125_EMIF_SDREF, - .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, - .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, - .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, - .zq_config = MT41J128MJT125_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -const struct dpll_params dpll_ddr = { -/* M N M2 M3 M4 M5 M6 */ - 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - - /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - -static void probe_sdram_size(long size) -{ - switch (size) { - case SZ_512M: - ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; - break; - case SZ_256M: - ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; - break; - case SZ_128M: - ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; - break; - default: - puts("Failed configuring DRAM, resetting...\n\n"); - reset_cpu(); - } - debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); - config_ddr(303, &ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} - -void sdram_init(void) -{ - long size = SZ_1G; - - do { - size = size / 2; - probe_sdram_size(size); - } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); - - return; -} diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds deleted file mode 100644 index 4993880461..0000000000 --- a/board/compulab/cm_t335/u-boot.lds +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - *(.vectors) - CPUDIR/start.o (.text*) - board/compulab/cm_t335/built-in.o (.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = .; - - . = ALIGN(4); - __u_boot_list : { - KEEP(*(SORT(__u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - .hash : { *(.hash*) } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - - /* - * Deprecated: this MMU section is used by pxa at present but - * should not be used by new boards/CPUs. - */ - . = ALIGN(4096); - .mmutable : { - *(.mmutable) - } - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 7c93d30e1d..377c6aa077 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -41,7 +41,6 @@ obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o endif -obj-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o ifndef CONFIG_RAMBOOT_PBL obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c deleted file mode 100644 index 2315793010..0000000000 --- a/board/freescale/common/sgmii_riser.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Freescale SGMII Riser Card - * - * This driver supports the SGMII Riser card found on the - * "DS" style of development board from Freescale. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <net.h> -#include <linux/libfdt.h> -#include <tsec.h> -#include <fdt_support.h> - -void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num) -{ - int i; - - for (i = 0; i < num; i++) - if (tsec_info[i].flags & TSEC_SGMII) - tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET; -} - -void fsl_sgmii_riser_fdt_fixup(void *fdt) -{ - struct eth_device *dev; - int node; - int mdio_node; - int i = -1; - int etsec_num = 0; - - node = fdt_path_offset(fdt, "/aliases"); - if (node < 0) - return; - - while ((dev = eth_get_dev_by_index(++i)) != NULL) { - struct tsec_private *priv; - int phy_node; - int enet_node; - uint32_t ph; - char sgmii_phy[16]; - char enet[16]; - const u32 *phyh; - const char *model; - const char *path; - - if (!strstr(dev->name, "eTSEC")) - continue; - - priv = dev->priv; - if (!(priv->flags & TSEC_SGMII)) { - etsec_num++; - continue; - } - - mdio_node = fdt_node_offset_by_compatible(fdt, -1, - "fsl,gianfar-mdio"); - if (mdio_node < 0) - return; - - sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num); - phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy); - if (phy_node > 0) { - fdt_increase_size(fdt, 32); - ph = fdt_create_phandle(fdt, phy_node); - if (!ph) - continue; - } - - sprintf(enet, "ethernet%d", etsec_num++); - path = fdt_getprop(fdt, node, enet, NULL); - if (!path) { - debug("No alias for %s\n", enet); - continue; - } - - enet_node = fdt_path_offset(fdt, path); - if (enet_node < 0) - continue; - - model = fdt_getprop(fdt, enet_node, "model", NULL); - - /* - * We only want to do this to eTSECs. On some platforms - * there are more than one type of gianfar-style ethernet - * controller, and as we are creating an implicit connection - * between ethernet nodes and eTSEC devices, it is best to - * make the connection use as much explicit information - * as exists. - */ - if (!strstr(model, "TSEC")) - continue; - - if (phy_node < 0) { - /* - * This part is only for old device tree without - * sgmii_phy nodes. It's kept just for compatible - * reason. Soon to be deprecated if all device tree - * get updated. - */ - phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL); - if (!phyh) - continue; - - phy_node = fdt_node_offset_by_phandle(fdt, - fdt32_to_cpu(*phyh)); - - priv = dev->priv; - - if (priv->flags & TSEC_SGMII) - fdt_setprop_cell(fdt, phy_node, "reg", - priv->phyaddr); - } else { - fdt_setprop(fdt, enet_node, "phy-handle", &ph, - sizeof(ph)); - fdt_setprop_string(fdt, enet_node, - "phy-connection-type", - phy_string_for_interface( - PHY_INTERFACE_MODE_SGMII)); - } - } -} diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig deleted file mode 100644 index dbcd1afcba..0000000000 --- a/board/freescale/corenet_ds/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -if TARGET_P3041DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P3041DS" - -endif - -if TARGET_P4080DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P4080DS" - -endif - -if TARGET_P5040DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P5040DS" - -endif diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS deleted file mode 100644 index f0da86a34c..0000000000 --- a/board/freescale/corenet_ds/MAINTAINERS +++ /dev/null @@ -1,21 +0,0 @@ -CORENET_DS BOARD -#M: - -S: Maintained -F: board/freescale/corenet_ds/ -F: include/configs/P3041DS.h -F: configs/P3041DS_defconfig -F: configs/P3041DS_NAND_defconfig -F: configs/P3041DS_SDCARD_defconfig -F: configs/P3041DS_SPIFLASH_defconfig -F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P4080DS.h -F: configs/P4080DS_defconfig -F: configs/P4080DS_SDCARD_defconfig -F: configs/P4080DS_SPIFLASH_defconfig -F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P5040DS.h -F: configs/P5040DS_defconfig -F: configs/P5040DS_NAND_defconfig -F: configs/P5040DS_SDCARD_defconfig -F: configs/P5040DS_SPIFLASH_defconfig -F: configs/P5040DS_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile deleted file mode 100644 index 4d62fc9ce1..0000000000 --- a/board/freescale/corenet_ds/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += corenet_ds.o -obj-y += ddr.o -obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o -obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o -obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o -obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o -obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o -obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c deleted file mode 100644 index 3a83e65f2f..0000000000 --- a/board/freescale/corenet_ds/corenet_ds.c +++ /dev/null @@ -1,218 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <fdt_support.h> -#include <image.h> -#include <init.h> -#include <netdev.h> -#include <asm/global_data.h> -#include <linux/compiler.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_liodn.h> -#include <fm_eth.h> - -#include "../common/ngpixis.h" -#include "corenet_ds.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) -{ - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - unsigned int i; -#endif - static const char * const freq[] = {"100", "125", "156.25", "212.5" }; - - printf("Board: %sDS, ", cpu->name); - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); - - sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); - sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); - - /* Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference Clocks: "); -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; - - printf("Bank%u=%sMhz ", i+1, freq[clock]); - } -#ifdef CONFIG_TARGET_P5040DS - /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ - sw = in_8(&PIXIS_SW(9)); - printf("Bank4=%sMhz ", freq[sw & 3]); -#endif - puts("\n"); -#else - sw = in_8(&PIXIS_SW(3)); - /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ - /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ - /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ - printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); - printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); - printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); -#endif - - return 0; -} - -int board_early_init_f(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* - * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 - * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce - * the noise introduced by these unterminated and unused clock pairs. - */ - setbits_be32(&gur->ddrclkdr, 0x001B001B); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - - return 0; -} - -#define NUM_SRDS_BANKS 3 - -int misc_init_r(void) -{ - serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 actual[NUM_SRDS_BANKS]; - unsigned int i; - u8 sw; - -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; - switch (clock) { - case 0: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 2: - actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - default: - printf("Warning: SDREFCLK%u switch setting of '11' is " - "unsupported\n", i + 1); - break; - } - } -#else - /* Warn if the expected SERDES reference clocks don't match the - * actual reference clocks. This needs to be done after calling - * p4080_erratum_serdes8(), since that function may modify the clocks. - */ - sw = in_8(&PIXIS_SW(3)); - actual[0] = (sw & 0x40) ? - SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; - actual[1] = (sw & 0x20) ? - SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; - actual[2] = (sw & 0x10) ? - SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; -#endif - - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES bank %u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - - return 0; -} diff --git a/board/freescale/corenet_ds/corenet_ds.h b/board/freescale/corenet_ds/corenet_ds.h deleted file mode 100644 index 84e5c4a2de..0000000000 --- a/board/freescale/corenet_ds/corenet_ds.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); - -#endif diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c deleted file mode 100644 index 2c440673e7..0000000000 --- a/board/freescale/corenet_ds/ddr.c +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <i2c.h> -#include <hwconfig.h> -#include <init.h> -#include <log.h> -#include <vsprintf.h> -#include <asm/global_data.h> -#include <asm/mmu.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <asm/fsl_law.h> - -DECLARE_GLOBAL_DATA_PTR; - - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -extern fixed_ddr_parm_t fixed_ddr_parm_0[]; -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) -extern fixed_ddr_parm_t fixed_ddr_parm_1[]; -#endif - -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - unsigned int lawbar1_target_id; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_1[i].ddr_settings, - sizeof(ddr_cfg_regs)); - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); -#endif - - /* - * setup laws for DDR. If not interleaving, presuming half memory on - * DDR1 and the other half on DDR2 - */ - if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - LAW_TRGT_IF_DDR_INTRLV) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - } else { -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) - /* We require both controllers have identical DIMMs */ - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size / 2, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - lawbar1_target_id = LAW_TRGT_IF_DDR_2; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, - ddr_size / 2, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } -#else - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } -#endif - } - return ddr_size; -} - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 wrlvl_start; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 5, 6, 0xff, 2, 0}, - {2, 1050, 5, 7, 0xff, 2, 0}, - {2, 1250, 4, 6, 0xff, 2, 0}, - {2, 1350, 5, 7, 0xff, 2, 0}, - {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 1250, 4, 6, 0xff, 2, 0}, - {1, 1335, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. The center values are good - * for both slots. We use identical speed tables for them. In future use, if - * DIMMs have fewer center values that require two separated tables, copy the - * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 4, 6, 0xff, 2, 0}, - {2, 1050, 4, 7, 0xff, 2, 0}, - {2, 1666, 4, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 60 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN; -} - -int dram_init(void) -{ - phys_size_t dram_size; - - puts("Initializing...."); - - if (fsl_use_spd()) { - puts("using SPD\n"); - dram_size = fsl_ddr_sdram(); - } else { - puts("using fixed parameters\n"); - dram_size = fixed_sdram(); - } - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c deleted file mode 100644 index a27e905ace..0000000000 --- a/board/freescale/corenet_ds/eth_hydra.c +++ /dev/null @@ -1,526 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Author: Timur Tabi <timur@freescale.com> - */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference - * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are - * provided by the standard Freescale four-port SGMII riser card. The 10Gb - * XGMII PHY is provided via the XAUI riser card. Since there is only one - * Fman device on a P3041 and P5020, we only support one SGMII card and one - * RGMII card. - * - * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is - * always the same (0). The value for SGMII depends on which slot the riser is - * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, - * the value is based on which slot the XAUI is inserted in. - * - * The SERDES configuration is used to determine where the SGMII and XAUI cards - * exist, and also which Fman MACs are routed to which PHYs. So for a given - * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed - * to PHYs dynamically. - * - * - * This file also updates the device tree in three ways: - * - * 1) The status of each virtual MDIO node that is referenced by an Ethernet - * node is set to "okay". - * - * 2) The phy-handle property of each active Ethernet MAC node is set to the - * appropriate PHY node. - * - * 3) The "mux value" for each virtual MDIO node is set to the correct value, - * if necessary. Some virtual MDIO nodes do not have configurable mux - * values, so those values are hard-coded in the DTS. On the HYDRA board, - * the virtual MDIO node for the SGMII card needs to be updated. - * - * For all this to work, the device tree needs to have the following: - * - * 1) An alias for each PHY node that an Ethernet node could be routed to. - * - * 2) An alias for each real and virtual MDIO node that is disabled by default - * and might need to be enabled, and also might need to have its mux-value - * updated. - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fdt_support.h> -#include <fsl_dtsec.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET - -#define BRDCFG1_EMI1_SEL_MASK 0x78 -#define BRDCFG1_EMI1_SEL_SLOT1 0x10 -#define BRDCFG1_EMI1_SEL_SLOT2 0x20 -#define BRDCFG1_EMI1_SEL_SLOT5 0x30 -#define BRDCFG1_EMI1_SEL_SLOT6 0x40 -#define BRDCFG1_EMI1_SEL_SLOT7 0x50 -#define BRDCFG1_EMI1_SEL_RGMII 0x00 -#define BRDCFG1_EMI1_EN 0x08 -#define BRDCFG1_EMI2_SEL_MASK 0x06 -#define BRDCFG1_EMI2_SEL_SLOT1 0x00 -#define BRDCFG1_EMI2_SEL_SLOT2 0x02 - -#define BRDCFG2_REG_GPIO_SEL 0x20 - -#define PHY_BASE_ADDR 0x00 - -/* - * BRDCFG1 mask and value for each MAC - * - * This array contains the BRDCFG1 values (in mask/val format) that route the - * MDIO bus to a particular RGMII or SGMII PHY. - */ -struct { - u8 mask; - u8 val; -} mdio_mux[NUM_FM_PORTS]; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 -}; - -/* - * Set the board muxing for a given MAC - * - * The MDIO layer calls this function every time it wants to talk to a PHY. - */ -void hydra_mux_mdio(u8 mask, u8 val) -{ - clrsetbits_8(&pixis->brdcfg1, mask, val); -} - -struct hydra_mdio { - u8 mask; - u8 val; - struct mii_dev *realbus; -}; - -static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct hydra_mdio *priv = bus->priv; - - hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct hydra_mdio *priv = bus->priv; - - hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int hydra_mdio_reset(struct mii_dev *bus) -{ - struct hydra_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static void hydra_mdio_set_mux(char *name, u8 mask, u8 val) -{ - struct mii_dev *bus = miiphy_get_dev_by_name(name); - struct hydra_mdio *priv = bus->priv; - - priv->mask = mask; - priv->val = val; -} - -static int hydra_mdio_init(char *realbusname, char *fakebusname) -{ - struct hydra_mdio *hmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate Hydra MDIO bus\n"); - return -1; - } - - hmdio = malloc(sizeof(*hmdio)); - if (!hmdio) { - printf("Failed to allocate Hydra private data\n"); - free(bus); - return -1; - } - - bus->read = hydra_mdio_read; - bus->write = hydra_mdio_write; - bus->reset = hydra_mdio_reset; - strcpy(bus->name, fakebusname); - - hmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!hmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(hmdio); - return -1; - } - - bus->priv = hmdio; - - return mdio_register(bus); -} - -/* - * Given an alias or a path for a node, set the mux value of that node. - * - * If 'alias' is not a valid alias, then it is treated as a full path to the - * node. No error checking is performed. - * - * This function is normally called to set the fsl,hydra-mdio-muxval property - * of a virtual MDIO node. - */ -static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) -{ - const char *path = fdt_get_alias(fdt, alias); - - if (!path) - path = alias; - - do_fixup_by_path(fdt, path, "reg", - &mux, sizeof(mux), 1); - do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", - &mux, sizeof(mux), 1); -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. That - * information is stored in mdio_mux[]. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - * Note that this code would be cleaner if had a function called - * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] - * array. That's because all we're doing is figuring out the PHY address for - * a given Fman MAC and writing it to the device tree. Well, we already did - * the hard work to figure that out in board_eth_init(), so it's silly to - * repeat that here. - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; - char phy[16]; - - if (port == FM1_10GEC1) { - /* XAUI */ - int lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - return; - } - - if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) { - /* RGMII */ - /* The RGMII PHY is identified by the MAC connected to it */ - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - return; - } - - /* If it's not RGMII or XGMII, it must be SGMII */ - if (mux) { - /* The SGMII PHY is identified by the MAC connected to it */ - sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } -} - -#define PIXIS_SW2_LANE_23_SEL 0x80 -#define PIXIS_SW2_LANE_45_SEL 0x40 -#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 -#define PIXIS_SW2_LANE_67_SEL_5 0x00 -#define PIXIS_SW2_LANE_67_SEL_6 0x20 -#define PIXIS_SW2_LANE_67_SEL_7 0x10 -#define PIXIS_SW2_LANE_8_SEL 0x08 -#define PIXIS_SW2_LANE_1617_SEL 0x04 - -/* - * Initialize the lane_to_slot[] array. - * - * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board - * slots is hard-coded. On the Hydra board, however, the mapping is controlled - * by board switch SW2, so the lane_to_slot[] array needs to be dynamically - * initialized. - */ -static void initialize_lane_to_slot(void) -{ - u8 sw2 = in_8(&PIXIS_SW(2)); - - lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; - lane_to_slot[3] = lane_to_slot[2]; - - lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; - lane_to_slot[5] = lane_to_slot[4]; - - switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { - case PIXIS_SW2_LANE_67_SEL_5: - lane_to_slot[6] = 5; - break; - case PIXIS_SW2_LANE_67_SEL_6: - lane_to_slot[6] = 6; - break; - case PIXIS_SW2_LANE_67_SEL_7: - lane_to_slot[6] = 7; - break; - } - lane_to_slot[7] = lane_to_slot[6]; - - lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; - - lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; - lane_to_slot[17] = lane_to_slot[16]; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -/* - * Configure the status for the virtual MDIO nodes - * - * Rather than create the virtual MDIO nodes from scratch for each active - * virtual MDIO, we expect the DTS to have the nodes defined already, and we - * only enable the ones that are actually active. - * - * We assume that the DTS already hard-codes the status for all the - * virtual MDIO nodes to "disabled", so all we need to do is enable the - * active ones. - * - * For SGMII, we also need to set the mux value in the node. - */ -void fdt_fixup_board_enet(void *fdt) -{ -#ifdef CONFIG_FMAN_ENET - unsigned int i; - int lane; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane >= 0) { - fdt_status_okay_by_alias(fdt, "emi1_sgmii"); - /* Also set the MUX value */ - fdt_set_mdio_mux(fdt, "emi1_sgmii", - mdio_mux[i].val); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "emi1_rgmii"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) - fdt_status_okay_by_alias(fdt, "emi2_xgmii"); -#endif -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - struct mii_dev *bus; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ - setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); - - memset(mdio_mux, 0, sizeof(mdio_mux)); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the three virtual MDIO front-ends */ - hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); - hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); - - /* - * Program the DTSEC PHY addresses assuming that they are all SGMII. - * For any DTSEC that's RGMII, we'll override its PHY address later. - * We assume that DTSEC5 is only used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - switch (slot) { - case 1: - /* Always DTSEC5 on Bank 3 */ - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - hydra_mdio_set_mux("HYDRA_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * If DTSEC4 is RGMII, then it's routed via via EC1 to - * the first on-board RGMII port. If DTSEC5 is RGMII, - * then it's routed via via EC2 to the second on-board - * RGMII port. The other DTSECs cannot be routed to - * RGMII. - */ - fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - hydra_mdio_set_mux("HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"); - set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR); - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot == 1) { - /* XAUI card is in slot 1 */ - clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, - BRDCFG1_EMI2_SEL_SLOT1); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - } else { - /* XAUI card is in slot 2 */ - clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, - BRDCFG1_EMI2_SEL_SLOT2); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM2_10GEC1_PHY_ADDR); - } - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c deleted file mode 100644 index df5a69bcba..0000000000 --- a/board/freescale/corenet_ds/eth_p4080.c +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <linux/delay.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" -#include <fsl_dtsec.h> - -#define EMI_NONE 0xffffffff -#define EMI_MASK 0xf0000000 -#define EMI1_RGMII 0x0 -#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */ -#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */ -#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ -#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */ -#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */ -#define EMI1_MASK 0xc0000000 -#define EMI2_MASK 0x30000000 - -#define PHY_BASE_ADDR 0x00 -#define PHY_BASE_ADDR_SLOT5 0x10 - -static int mdio_mux[NUM_FM_PORTS]; - -static char *mdio_names[16] = { - "P4080DS_MDIO0", - "P4080DS_MDIO1", - NULL, - "P4080DS_MDIO3", - "P4080DS_MDIO4", - NULL, NULL, NULL, - "P4080DS_MDIO8", - NULL, NULL, NULL, - "P4080DS_MDIO12", - NULL, NULL, NULL, -}; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot. - */ -static u8 lane_to_slot[] = { - 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5 -}; - -static char *p4080ds_mdio_name_for_muxval(u32 muxval) -{ - return mdio_names[(muxval & EMI_MASK) >> 28]; -} - -struct mii_dev *mii_dev_for_muxval(u32 muxval) -{ - struct mii_dev *bus; - char *name = p4080ds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS) -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - if (phydev->drv->uid == PHY_UID_TN2020) { - unsigned long timeout = 1 * 1000; /* 1 seconds */ - enum srds_prtcl device; - - /* - * Wait for the XAUI to come out of reset. This is when it - * starts transmitting alignment signals. - */ - while (--timeout) { - int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1); - if (reg < 0) { - printf("TN2020: Error reading from PHY at " - "address %u\n", phydev->addr); - break; - } - /* - * Note that we've never actually seen - * MDIO_CTRL1_RESET set to 1. - */ - if ((reg & MDIO_CTRL1_RESET) == 0) - break; - udelay(1000); - } - - if (!timeout) { - printf("TN2020: Timeout waiting for PHY at address %u " - " to reset.\n", phydev->addr); - } - - switch (phydev->addr) { - case CONFIG_SYS_FM1_10GEC1_PHY_ADDR: - device = XAUI_FM1; - break; - case CONFIG_SYS_FM2_10GEC1_PHY_ADDR: - device = XAUI_FM2; - break; - default: - device = NONE; - } - - serdes_reset_rx(device); - } - - return 0; -} -#endif - -struct p4080ds_mdio { - u32 muxval; - struct mii_dev *realbus; -}; - -static void p4080ds_mux_mdio(u32 muxval) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK); - gpioval |= muxval; - - out_be32(&pgpio->gpdat, gpioval); -} - -static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct p4080ds_mdio *priv = bus->priv; - - p4080ds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct p4080ds_mdio *priv = bus->priv; - - p4080ds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int p4080ds_mdio_reset(struct mii_dev *bus) -{ - struct p4080ds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int p4080ds_mdio_init(char *realbusname, u32 muxval) -{ - struct p4080ds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate P4080DS MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate P4080DS private data\n"); - free(bus); - return -1; - } - - bus->read = p4080ds_mdio_read; - bus->write = p4080ds_mdio_write; - bus->reset = p4080ds_mdio_reset; - sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, - enum fm_port port, int offset) -{ - if (mdio_mux[port] == EMI1_RGMII) - fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); - - if (mdio_mux[port] == EMI1_SLOT3) { - int idx = port - FM2_DTSEC1 + 5; - char phy[16]; - - sprintf(phy, "phy%d_slot3", idx); - - fdt_set_phy_handle(blob, prop, pa, phy); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - /* - * P4080DS can be configured in many different ways, supporting a number - * of combinations of ethernet devices and phy types. In order to - * have just one device tree for all of those configurations, we fix up - * the tree here. By default, the device tree configures FM1 and FM2 - * for SGMII, and configures XAUI on both 10G interfaces. So we have - * a number of different variables to track: - * - * 1) Whether the device is configured at all. Whichever devices are - * not enabled should be disabled by setting the "status" property - * to "disabled". - * 2) What the PHY interface is. If this is an RGMII connection, - * we should change the "phy-connection-type" property to - * "rgmii" - * 3) Which PHY is being used. Because the MDIO buses are muxed, - * we need to redirect the "phy-handle" property to point at the - * PHY on the right slot/bus. - */ - - /* We've got six MDIO nodes that may or may not need to exist */ - fdt_status_disabled_by_alias(fdt, "emi1_slot3"); - fdt_status_disabled_by_alias(fdt, "emi1_slot4"); - fdt_status_disabled_by_alias(fdt, "emi1_slot5"); - fdt_status_disabled_by_alias(fdt, "emi2_slot4"); - fdt_status_disabled_by_alias(fdt, "emi2_slot5"); - - for (i = 0; i < NUM_FM_PORTS; i++) { - switch (mdio_mux[i]) { - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); - break; - case EMI1_SLOT5: - fdt_status_okay_by_alias(fdt, "emi1_slot5"); - break; - case EMI2_SLOT4: - fdt_status_okay_by_alias(fdt, "emi2_slot4"); - break; - case EMI2_SLOT5: - fdt_status_okay_by_alias(fdt, "emi2_slot5"); - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - int i; - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - struct mii_dev *bus; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - /* The first 4 GPIOs are outputs to control MDIO bus muxing */ - out_be32(&pgpio->gpdir, EMI_MASK); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the 6 muxing front-ends to the MDIO buses */ - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4); - p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5); - - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - -#if (CONFIG_SYS_NUM_FMAN == 2) - fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); -#endif - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fm_info_set_phy_address(i, 0); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - bus = mii_dev_for_muxval(EMI1_SLOT5); - set_sgmii_phy(bus, FM1_DTSEC1, - CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5); - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - int idx = i - FM1_10GEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(XAUI_FM1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 4: - mdio_mux[i] = EMI2_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI2_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fm_info_set_phy_address(i, 0); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - bus = mii_dev_for_muxval(EMI1_SLOT3); - set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); - bus = mii_dev_for_muxval(EMI1_SLOT4); - set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { - int idx = i - FM2_10GEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(XAUI_FM2 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 4: - mdio_mux[i] = EMI2_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI2_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } -#endif - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c deleted file mode 100644 index 55bac0f761..0000000000 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ /dev/null @@ -1,783 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> - */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference - * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are - * provided by the standard Freescale four-port SGMII riser card. The 10Gb - * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans - * and 5 1G interfaces and 10G interface per FMan. Based on the options in - * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. - * - * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is - * always the same (0). The value for SGMII depends on which slot the riser is - * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, - * the value is based on which slot the XAUI is inserted in. - * - * The SERDES configuration is used to determine where the SGMII and XAUI cards - * exist, and also which Fman's MACs are routed to which PHYs. So for a given - * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed - * to PHYs dynamically. - * - * - * This file also updates the device tree in three ways: - * - * 1) The status of each virtual MDIO node that is referenced by an Ethernet - * node is set to "okay". - * - * 2) The phy-handle property of each active Ethernet MAC node is set to the - * appropriate PHY node. - * - * 3) The "mux value" for each virtual MDIO node is set to the correct value, - * if necessary. Some virtual MDIO nodes do not have configurable mux - * values, so those values are hard-coded in the DTS. On the HYDRA board, - * the virtual MDIO node for the SGMII card needs to be updated. - * - * For all this to work, the device tree needs to have the following: - * - * 1) An alias for each PHY node that an Ethernet node could be routed to. - * - * 2) An alias for each real and virtual MDIO node that is disabled by default - * and might need to be enabled, and also might need to have its mux-value - * updated. - */ - -#include <common.h> -#include <log.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fdt_support.h> -#include <fsl_dtsec.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET - -#define BRDCFG1_EMI1_SEL_MASK 0x70 -#define BRDCFG1_EMI1_SEL_SLOT1 0x10 -#define BRDCFG1_EMI1_SEL_SLOT2 0x20 -#define BRDCFG1_EMI1_SEL_SLOT5 0x30 -#define BRDCFG1_EMI1_SEL_SLOT6 0x40 -#define BRDCFG1_EMI1_SEL_SLOT7 0x50 -#define BRDCFG1_EMI1_SEL_SLOT3 0x60 -#define BRDCFG1_EMI1_SEL_RGMII 0x00 -#define BRDCFG1_EMI1_EN 0x08 -#define BRDCFG1_EMI2_SEL_MASK 0x06 -#define BRDCFG1_EMI2_SEL_SLOT1 0x00 -#define BRDCFG1_EMI2_SEL_SLOT2 0x02 - -#define BRDCFG2_REG_GPIO_SEL 0x20 - -/* SGMII */ -#define PHY_BASE_ADDR 0x00 -#define REGNUM 0x00 -#define PORT_NUM_FM1 0x04 -#define PORT_NUM_FM2 0x02 - -/* - * BRDCFG1 mask and value for each MAC - * - * This array contains the BRDCFG1 values (in mask/val format) that route the - * MDIO bus to a particular RGMII or SGMII PHY. - */ -static struct { - u8 mask; - u8 val; -} mdio_mux[NUM_FM_PORTS]; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 -}; - -/* - * Set the board muxing for a given MAC - * - * The MDIO layer calls this function every time it wants to talk to a PHY. - */ -void super_hydra_mux_mdio(u8 mask, u8 val) -{ - clrsetbits_8(&pixis->brdcfg1, mask, val); -} - -struct super_hydra_mdio { - u8 mask; - u8 val; - struct mii_dev *realbus; -}; - -static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct super_hydra_mdio *priv = bus->priv; - - super_hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct super_hydra_mdio *priv = bus->priv; - - super_hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int super_hydra_mdio_reset(struct mii_dev *bus) -{ - struct super_hydra_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) -{ - struct mii_dev *bus = miiphy_get_dev_by_name(name); - struct super_hydra_mdio *priv = bus->priv; - - priv->mask = mask; - priv->val = val; -} - -static int super_hydra_mdio_init(char *realbusname, char *fakebusname) -{ - struct super_hydra_mdio *hmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate Hydra MDIO bus\n"); - return -1; - } - - hmdio = malloc(sizeof(*hmdio)); - if (!hmdio) { - printf("Failed to allocate Hydra private data\n"); - free(bus); - return -1; - } - - bus->read = super_hydra_mdio_read; - bus->write = super_hydra_mdio_write; - bus->reset = super_hydra_mdio_reset; - strcpy(bus->name, fakebusname); - - hmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!hmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(hmdio); - return -1; - } - - bus->priv = hmdio; - - return mdio_register(bus); -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. That - * information is stored in mdio_mux[]. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - enum srds_prtcl device; - int lane, slot, phy; - char alias[32]; - - /* RGMII and XGMII are already mapped correctly in the DTS */ - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - device = serdes_device_from_fm_port(port); - lane = serdes_get_first_lane(device); - slot = lane_to_slot[lane]; - phy = fm_info_get_phy_address(port); - - sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - } -} - -#define PIXIS_SW2_LANE_23_SEL 0x80 -#define PIXIS_SW2_LANE_45_SEL 0x40 -#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 -#define PIXIS_SW2_LANE_67_SEL_5 0x00 -#define PIXIS_SW2_LANE_67_SEL_6 0x20 -#define PIXIS_SW2_LANE_67_SEL_7 0x10 -#define PIXIS_SW2_LANE_8_SEL 0x08 -#define PIXIS_SW2_LANE_1617_SEL 0x04 -#define PIXIS_SW11_LANE_9_SEL 0x04 -/* - * Initialize the lane_to_slot[] array. - * - * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board - * slots is hard-coded. On the Hydra board, however, the mapping is controlled - * by board switch SW2, so the lane_to_slot[] array needs to be dynamically - * initialized. - */ -static void initialize_lane_to_slot(void) -{ - u8 sw2 = in_8(&PIXIS_SW(2)); - /* SW11 appears in the programming model as SW9 */ - u8 sw11 = in_8(&PIXIS_SW(9)); - - lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; - lane_to_slot[3] = lane_to_slot[2]; - - lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; - lane_to_slot[5] = lane_to_slot[4]; - - switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { - case PIXIS_SW2_LANE_67_SEL_5: - lane_to_slot[6] = 5; - break; - case PIXIS_SW2_LANE_67_SEL_6: - lane_to_slot[6] = 6; - break; - case PIXIS_SW2_LANE_67_SEL_7: - lane_to_slot[6] = 7; - break; - } - lane_to_slot[7] = lane_to_slot[6]; - - lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; - lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; - - lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; - lane_to_slot[17] = lane_to_slot[16]; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -/* - * Configure the status for the virtual MDIO nodes - * - * Rather than create the virtual MDIO nodes from scratch for each active - * virtual MDIO, we expect the DTS to have the nodes defined already, and we - * only enable the ones that are actually active. - * - * We assume that the DTS already hard-codes the status for all the - * virtual MDIO nodes to "disabled", so all we need to do is enable the - * active ones. - */ -void fdt_fixup_board_enet(void *fdt) -{ -#ifdef CONFIG_FMAN_ENET - enum fm_port i; - int lane, slot; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_sg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", - alias, slot); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "hydra_rg"); - debug("Enabled MDIO node hydra_rg\n"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_xg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", alias, slot); - } - -#if CONFIG_SYS_NUM_FMAN == 2 - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_sg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", - alias, slot); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "hydra_rg"); - debug("Enabled MDIO node hydra_rg\n"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM2); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_xg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", alias, slot); - } -#endif /* CONFIG_SYS_NUM_FMAN == 2 */ -#endif /* CONFIG_FMAN_ENET */ -} - -/* - * Mapping of SerDes Protocol to MDIO MUX value and PHY address. - * - * Fman 1: - * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 - * Mux Phy | Mux Phy | Mux Phy | Mux Phy - * Value Addr | Value Addr | Value Addr | Value Addr - * 0x00 2 1c | 2 1d | 2 1e | 2 1f - * 0x01 | | 6 1c | - * 0x02 | | 3 1c | 3 1d - * 0x03 2 1c | 2 1d | 2 1e | 2 1f - * 0x04 2 1c | 2 1d | 2 1e | 2 1f - * 0x05 | | 3 1c | 3 1d - * 0x06 2 1c | 2 1d | 2 1e | 2 1f - * 0x07 | | 6 1c | - * 0x11 2 1c | 2 1d | 2 1e | 2 1f - * 0x2a 2 | | 2 1e | 2 1f - * 0x34 6 1c | 6 1d | 4 1e | 4 1f - * 0x35 | | 3 1c | 3 1d - * 0x36 6 1c | 6 1d | 4 1e | 4 1f - * | | | - * Fman 2: | | | - * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 - * EMI1 | EMI1 | EMI1 | EMI1 - * Mux Phy | Mux Phy | Mux Phy | Mux Phy - * Value Addr | Value Addr | Value Addr | Value Addr - * 0x00 | | 6 1c | 6 1d - * 0x01 | | | - * 0x02 | | 6 1c | 6 1d - * 0x03 3 1c | 3 1d | 6 1c | 6 1d - * 0x04 3 1c | 3 1d | 6 1c | 6 1d - * 0x05 | | 6 1c | 6 1d - * 0x06 | | 6 1c | 6 1d - * 0x07 | | | - * 0x11 | | | - * 0x2a | | | - * 0x34 | | | - * 0x35 | | | - * 0x36 | | | - */ - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - struct mii_dev *bus; - int qsgmii; - int phy_real_addr; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int srds_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ - setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); - - memset(mdio_mux, 0, sizeof(mdio_mux)); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the three virtual MDIO front-ends */ - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_RGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM1_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM2_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM3_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, - "SUPER_HYDRA_FM1_TGEC_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, - "SUPER_HYDRA_FM2_TGEC_MDIO"); - - /* - * Program the DTSEC PHY addresses assuming that they are all SGMII. - * For any DTSEC that's RGMII, we'll override its PHY address later. - * We assume that DTSEC5 is only used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); - -#if (CONFIG_SYS_NUM_FMAN == 2) - fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); -#endif - - switch (srds_prtcl) { - case 0: - case 3: - case 4: - case 6: - case 0x11: - case 0x2a: - case 0x34: - case 0x36: - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - case 1: - case 2: - case 5: - case 7: - case 0x35: - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - break; - default: - printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - switch (slot) { - case 1: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 3: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * FM1 DTSEC5 is routed via EC1 to the first on-board - * RGMII port. FM2 DTSEC5 is routed via EC2 to the - * second on-board RGMII port. The other DTSECs cannot - * be routed to RGMII. - */ - debug("FM1@DTSEC%u is RGMII at address %u\n", - idx + 1, 0); - fm_info_set_phy_address(i, 0); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"); - qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); - - if (qsgmii) { - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) { - if (fm_info_get_enet_if(i) == - PHY_INTERFACE_MODE_SGMII) { - phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1; - fm_info_set_phy_address(i, phy_real_addr); - } - } - switch (srds_prtcl) { - case 0x00: - case 0x03: - case 0x04: - case 0x06: - case 0x11: - case 0x2a: - case 0x34: - case 0x36: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3); - break; - case 0x01: - case 0x02: - case 0x05: - case 0x07: - case 0x35: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); - break; - default: - break; - } - } - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - debug("FM2@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - switch (slot) { - case 1: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 3: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { - super_hydra_mdio_set_mux( - "SUPER_HYDRA_FM3_SGMII_MDIO", - mdio_mux[i].mask, - mdio_mux[i].val); - fm_info_set_mdio(i, miiphy_get_dev_by_name( - "SUPER_HYDRA_FM3_SGMII_MDIO")); - } else { - super_hydra_mdio_set_mux( - "SUPER_HYDRA_FM2_SGMII_MDIO", - mdio_mux[i].mask, - mdio_mux[i].val); - fm_info_set_mdio(i, miiphy_get_dev_by_name( - "SUPER_HYDRA_FM2_SGMII_MDIO")); - } - - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * FM1 DTSEC5 is routed via EC1 to the first on-board - * RGMII port. FM2 DTSEC5 is routed via EC2 to the - * second on-board RGMII port. The other DTSECs cannot - * be routed to RGMII. - */ - debug("FM2@DTSEC%u is RGMII at address %u\n", - idx + 1, 1); - fm_info_set_phy_address(i, 1); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman2: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"); - set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR); - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO"); - set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR); - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM2); - if (lane >= 0) { - debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - } - - fm_info_set_mdio(FM2_10GEC1, - miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); - -#endif - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c deleted file mode 100644 index c62d85ccc0..0000000000 --- a/board/freescale/corenet_ds/p3041ds_ddr.c +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c deleted file mode 100644 index 9839eaceaf..0000000000 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 -#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 -#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 -#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 -#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 -#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 -#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 -#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 -#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF -#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 -#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 -#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 -#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce -#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 -#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 -#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 -#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 -#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {850, 950, &ddr_cfg_regs_900}, - {950, 1050, &ddr_cfg_regs_1000}, - {1050, 1250, &ddr_cfg_regs_1200}, - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {750, 850, &ddr_cfg_regs_800_2nd}, - {850, 950, &ddr_cfg_regs_900_2nd}, - {950, 1050, &ddr_cfg_regs_1000_2nd}, - {1050, 1250, &ddr_cfg_regs_1200_2nd}, - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c deleted file mode 100644 index 112733be78..0000000000 --- a/board/freescale/corenet_ds/p5040ds_ddr.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg deleted file mode 100644 index 8813156219..0000000000 --- a/board/freescale/corenet_ds/rcw_p3041ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P3041DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -12600000 00000000 241C0000 00000000 -D8984A01 03002000 58000000 41000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg deleted file mode 100644 index 6a26339599..0000000000 --- a/board/freescale/corenet_ds/rcw_p4080ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P4080DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -105a0000 00000000 1e1e181e 0000cccc -58400000 3c3c2000 58000000 e1000000 -00000000 00000000 00000000 008b6000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg deleted file mode 100644 index 82fa7417d9..0000000000 --- a/board/freescale/corenet_ds/rcw_p5040ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P5040DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -0c580000 00000000 22121200 00000000 -089c4400 00283000 58000000 61000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 5ab03b3340..3ed6100b7c 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -109,44 +109,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_TSEC_ENET -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} -#endif - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index 65030342be..8cbf33fa0c 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -6,5 +6,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o -obj-y += eth.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c deleted file mode 100644 index a9f162b974..0000000000 --- a/board/freescale/ls1021aqds/eth.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * This file handles the board muxing between the RGMII/SGMII PHYs on - * Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb - * ports. The SGMII PHYs are provided by the standard Freescale four-port - * SGMII riser card. - * - * Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends - * on which port is used. The value for SGMII depends on which slot the riser - * is inserted in. - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/arch/fsl_serdes.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <malloc.h> - -#include "../common/sgmii_riser.h" -#include "../common/qixis.h" - -#define EMI1_MASK 0x1f -#define EMI1_RGMII0 1 -#define EMI1_RGMII1 2 -#define EMI1_RGMII2 3 -#define EMI1_SGMII1 0x1c -#define EMI1_SGMII2 0x1d - -struct ls1021a_mdio { - struct mii_dev *realbus; -}; - -static void ls1021a_mux_mdio(int addr) -{ - u8 brdcfg4; - - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= EMI1_MASK; - - switch (addr) { - case EMI1_RGMII0: - brdcfg4 |= 0; - break; - case EMI1_RGMII1: - brdcfg4 |= 0x20; - break; - case EMI1_RGMII2: - brdcfg4 |= 0x40; - break; - case EMI1_SGMII1: - brdcfg4 |= 0x60; - break; - case EMI1_SGMII2: - brdcfg4 |= 0x80; - break; - default: - brdcfg4 |= 0xa0; - break; - } - - QIXIS_WRITE(brdcfg[4], brdcfg4); -} - -static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1021a_mdio *priv = bus->priv; - - ls1021a_mux_mdio(addr); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1021a_mdio *priv = bus->priv; - - ls1021a_mux_mdio(addr); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int ls1021a_mdio_reset(struct mii_dev *bus) -{ - struct ls1021a_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1021a_mdio_init(char *realbusname, char *fakebusname) -{ - struct ls1021a_mdio *lsmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate LS102xA MDIO bus\n"); - return -1; - } - - lsmdio = malloc(sizeof(*lsmdio)); - if (!lsmdio) { - printf("Failed to allocate LS102xA private data\n"); - free(bus); - return -1; - } - - bus->read = ls1021a_mdio_read; - bus->write = ls1021a_mdio_write; - bus->reset = ls1021a_mdio_reset; - strcpy(bus->name, fakebusname); - - lsmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!lsmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(lsmdio); - return -1; - } - - bus->priv = lsmdio; - - return mdio_register(bus); -} - -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[3]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode\n"); - tsec_info[num].flags |= TSEC_SGMII; - tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; - } else { - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode\n"); - tsec_info[num].flags |= TSEC_SGMII; - tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; - } else { - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_init(tsec_info, num); -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - /* Register the virtual MDIO front-ends */ - ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO"); - ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO"); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index e156ba0104..7bfbacde4f 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -30,8 +30,6 @@ #define EMI1_SLOT4 5 #define EMI2 6 -static int mdio_mux[NUM_FM_PORTS]; - static const char * const mdio_names[] = { "LS1043AQDS_MDIO_RGMII1", "LS1043AQDS_MDIO_RGMII2", @@ -43,7 +41,11 @@ static const char * const mdio_names[] = { }; /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + static u8 lane_to_slot[] = {1, 2, 3, 4}; +#endif static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) { @@ -75,6 +77,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; } +#ifdef CONFIG_FMAN_ENET struct ls1043aqds_mdio { u8 muxval; struct mii_dev *realbus; @@ -296,7 +299,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(struct bd_info *bis) { -#ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; @@ -493,7 +495,7 @@ int board_eth_init(struct bd_info *bis) } cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); } +#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 13359f947b..7ac2c1ae90 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -556,10 +556,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 8233f5461e..13207a1a37 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -27,8 +27,6 @@ #define EMI1_SLOT2 3 #define EMI1_SLOT4 4 -static int mdio_mux[NUM_FM_PORTS]; - static const char * const mdio_names[] = { "LS1046AQDS_MDIO_RGMII1", "LS1046AQDS_MDIO_RGMII2", @@ -39,7 +37,11 @@ static const char * const mdio_names[] = { }; /* Map SerDes 1 & 2 lanes to default slot. */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; +#endif static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) { @@ -71,6 +73,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; } +#ifdef CONFIG_FMAN_ENET struct ls1046aqds_mdio { u8 muxval; struct mii_dev *realbus; @@ -263,7 +266,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(struct bd_info *bis) { -#ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -423,7 +425,7 @@ int board_eth_init(struct bd_info *bis) } cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); } +#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index e5b5441e2c..aa6e30e6b2 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -439,10 +439,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index dac821f1ac..8886d8be33 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -169,7 +169,8 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ } -void configure_rgmii(void) +#ifndef CONFIG_DM_ETH +static void configure_rgmii(void) { unsigned short temp; @@ -248,3 +249,4 @@ int board_eth_init(struct bd_info *bis) return pci_eth_init(bis); } +#endif diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS index c565010ccf..f20baa91c6 100644 --- a/board/freescale/mx28evk/MAINTAINERS +++ b/board/freescale/mx28evk/MAINTAINERS @@ -5,6 +5,3 @@ F: board/freescale/mx28evk/ F: arch/arm/dts/imx28-evk.dts F: include/configs/mx28evk.h F: configs/mx28evk_defconfig -F: configs/mx28evk_auart_console_defconfig -F: configs/mx28evk_nand_defconfig -F: configs/mx28evk_spi_defconfig diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/p2041rdb/pbi.cfg index 75dfc32162..75dfc32162 100644 --- a/board/freescale/corenet_ds/pbi.cfg +++ b/board/freescale/p2041rdb/pbi.cfg diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/p2041rdb/rcw_p2041rdb.cfg index 8df19dd3fe..8df19dd3fe 100644 --- a/board/freescale/corenet_ds/rcw_p2041rdb.cfg +++ b/board/freescale/p2041rdb/rcw_p2041rdb.cfg diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 0932f62b9b..6c5e6fbbcb 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -88,62 +88,6 @@ int onenand_board_init(struct mtd_info *mtd) return 1; } -#if defined(CONFIG_CMD_NET) -static void reset_net_chip(int gpio) -{ - if (!gpio_request(gpio, "eth nrst")) { - gpio_direction_output(gpio, 1); - udelay(1); - gpio_set_value(gpio, 0); - udelay(40); - gpio_set_value(gpio, 1); - mdelay(10); - } -} - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, - }; - - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); - - reset_net_chip(64); -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} -#else -static inline void setup_net_chip(void) {} -#endif - #ifdef CONFIG_OF_BOARD_SETUP static int ft_enable_by_compatible(void *blob, char *compat, int enable) { @@ -234,8 +178,6 @@ int misc_init_r(void) OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, OMAP34XX_CTRL_WKUP_CTRL); - setup_net_chip(); - omap_die_id_display(); set_led(); diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index 8247ae39d3..ef3c62b9de 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -61,25 +61,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy endif -if TARGET_KMTEGR1 - -config SYS_BOARD - default "km83xx" - -config SYS_VENDOR - default "keymile" - -config SYS_CONFIG_NAME - default "kmtegr1" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_MPC8309 - imply CMD_CRAMFS - imply FS_CRAMFS - -endif - if TARGET_TUXX1 config SYS_BOARD diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index 9fd5a8500d..ac1f8cbd88 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -10,10 +10,8 @@ F: include/configs/tuxx1.h F: configs/kmopti2_defconfig F: configs/kmsupx5_defconfig F: configs/kmtepr2_defconfig -F: configs/kmtegr1_defconfig F: configs/tuge1_defconfig F: configs/tuxx1_defconfig -F: arch/powerpc/dts/km8309-uboot.dtsi F: arch/powerpc/dts/km8321-uboot.dtsi F: arch/powerpc/dts/km8321.dtsi F: arch/powerpc/dts/km836x-uboot.dtsi @@ -25,7 +23,6 @@ F: arch/powerpc/dts/kmeter1.dts F: arch/powerpc/dts/kmopti2.dts F: arch/powerpc/dts/kmsupc5.dts F: arch/powerpc/dts/kmsupm5.dts -F: arch/powerpc/dts/kmtegr1.dts F: arch/powerpc/dts/kmtepr2.dts F: arch/powerpc/dts/kmtuge1.dts F: arch/powerpc/dts/kmtuxa1.dts diff --git a/board/kmc/kzm9g/Kconfig b/board/kmc/kzm9g/Kconfig deleted file mode 100644 index f163efd989..0000000000 --- a/board/kmc/kzm9g/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KZM9G - -config SYS_BOARD - default "kzm9g" - -config SYS_VENDOR - default "kmc" - -config SYS_CONFIG_NAME - default "kzm9g" - -endif diff --git a/board/kmc/kzm9g/MAINTAINERS b/board/kmc/kzm9g/MAINTAINERS deleted file mode 100644 index 411efd1e31..0000000000 --- a/board/kmc/kzm9g/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KZM9G BOARD -M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -M: Tetsuyuki Kobayashi <koba@kmckk.co.jp> -S: Maintained -F: board/kmc/kzm9g/ -F: include/configs/kzm9g.h -F: configs/kzm9g_defconfig diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile deleted file mode 100644 index aebe9f3546..0000000000 --- a/board/kmc/kzm9g/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -# (C) Copyright 2012 Renesas Solutions Corp. - -obj-y := kzm9g.o diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c deleted file mode 100644 index dccf4691af..0000000000 --- a/board/kmc/kzm9g/kzm9g.c +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * (C) Copyright 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <netdev.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CS0BCR_D (0x06C00400) -#define CS4BCR_D (0x16c90400) -#define CS0WCR_D (0x55062C42) -#define CS4WCR_D (0x1e071dc3) - -#define CMNCR_BROMMD0 (1 << 21) -#define CMNCR_BROMMD1 (1 << 22) -#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) -#define VCLKCR1_D (0x27) - -#define SMSTPCR1_CMT0 (1 << 24) -#define SMSTPCR1_I2C0 (1 << 16) -#define SMSTPCR3_USB (1 << 22) -#define SMSTPCR3_I2C1 (1 << 23) - -#define PORT32CR (0xE6051020) -#define PORT33CR (0xE6051021) -#define PORT34CR (0xE6051022) -#define PORT35CR (0xE6051023) - -static int cmp_loop(u32 *addr, u32 data, u32 cmp) -{ - int err = -1; - int timeout = 100; - u32 value; - - while (timeout > 0) { - value = readl(addr); - if ((value & data) == cmp) { - err = 0; - break; - } - timeout--; - } - - return err; -} - -/* SBSC Init function */ -static void sbsc_init(struct sh73a0_sbsc *sbsc) -{ - writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); - writel(0x5, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0xacc90159, &sbsc->sdcr0); - writel(0x00010059, &sbsc->sdcr1); - writel(0x50874114, &sbsc->sdwcrc0); - writel(0x33199b37, &sbsc->sdwcrc1); - writel(0x008f2313, &sbsc->sdwcrc2); - writel(0x31020707, &sbsc->sdwcr00); - writel(0x0017040a, &sbsc->sdwcr01); - writel(0x31020707, &sbsc->sdwcr10); - writel(0x0017040a, &sbsc->sdwcr11); - writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */ - writel(0x30000000, &sbsc->sdwcr2); - - writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); - cmp_loop(&sbsc->sdpcr, 0x80, 0x80); - - writel(0x00002710, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0x0000003f, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x000001f4, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0x0000ff0a, &sbsc->sdmracr0); - if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) - writel(0x0, SDMRA3A); - else - writel(0x0, SDMRA3B); - - writel(0x00000032, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { - writel(0x00002201, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x00000402, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ - writel(0x0, SDMRA1A); - writel(0x0, SDMRA2A); - } else { - writel(0x00002201, &sbsc->sdmracr0); - writel(0x0, SDMRA1B); - writel(0x00000402, &sbsc->sdmracr0); - writel(0x0, SDMRA1B); - writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ - writel(0x0, SDMRA1B); - writel(0x0, SDMRA2B); - } - - writel(0x88800004, &sbsc->sdmrtmpcr); - writel(0x00000004, &sbsc->sdmrtmpmsk); - writel(0xa55a0032, &sbsc->rtcor); - writel(0xa55a000c, &sbsc->rtcorh); - writel(0xa55a2048, &sbsc->rtcsr); - writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); - writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); - writel(0xfff20000, &sbsc->zqccr); - - /* SCBS2 only */ - if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { - writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); - writel(0xa5390000, &sbsc->dphycnt1); - writel(0x00001200, &sbsc->dphycnt0); - writel(0x07ce0000, &sbsc->dphycnt1); - writel(0x00001247, &sbsc->dphycnt0); - cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); - writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); - } -} - -void s_init(void) -{ - struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; - struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; - struct sh73a0_sbsc_cpg_srcr *cpg_srcr = - (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; - struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; - struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; - struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; - struct sh73a0_hpb_bscr *hpb_bscr = - (struct sh73a0_hpb_bscr *)HPBSCR_BASE; - - /* Watchdog init */ - writew(0xA507, &rwdt->rwtcsra0); - - /* Secure control register Init */ - #define LIFEC_SEC_SRC_BIT (1 << 15) - writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); - - clrbits_le32(&cpg->smstpcr3, (1 << 15)); - clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); - clrbits_le32(&cpg->smstpcr2, (1 << 18)); - clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); - writel(0x0, &cpg->pllecr); - - cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - - writel(0x2D000000, &cpg->pll0cr); - writel(0x17100000, &cpg->pll1cr); - writel(0x96235880, &cpg->frqcrb); - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - - writel(0xB, &cpg->flckcr); - clrbits_le32(&cpg->smstpcr0, (1 << 1)); - - clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); - writel(0x0514, &hpb_bscr->smgpiotime); - writel(0x0514, &hpb_bscr->smcmt2time); - writel(0x0514, &hpb_bscr->smcpgtime); - writel(0x0514, &hpb_bscr->smsysctime); - - writel(0x00092000, &cpg->dvfscr4); - writel(0x000000DC, &cpg->dvfscr5); - writel(0x0, &cpg->pllecr); - cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); - - /* FRQCR Init */ - writel(0x0012453C, &cpg->frqcra); - writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */ - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - writel(0x00000B0B, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - - /* Clock Init */ - writel(0x00000003, PCLKCR); - writel(0x0000012F, &cpg->vclkcr1); - writel(0x00000119, &cpg->vclkcr2); - writel(0x00000119, &cpg->vclkcr3); - writel(0x00000002, &cpg->zbckcr); - writel(0x00000005, &cpg->flckcr); - writel(0x00000080, &cpg->sd0ckcr); - writel(0x00000080, &cpg->sd1ckcr); - writel(0x00000080, &cpg->sd2ckcr); - writel(0x0000003F, &cpg->fsiackcr); - writel(0x0000003F, &cpg->fsibckcr); - writel(0x00000080, &cpg->subckcr); - writel(0x0000000B, &cpg->spuackcr); - writel(0x0000000B, &cpg->spuvckcr); - writel(0x0000013F, &cpg->msuckcr); - writel(0x00000080, &cpg->hsickcr); - writel(0x0000003F, &cpg->mfck1cr); - writel(0x0000003F, &cpg->mfck2cr); - writel(0x00000107, &cpg->dsitckcr); - writel(0x00000313, &cpg->dsi0pckcr); - writel(0x0000130D, &cpg->dsi1pckcr); - writel(0x2A800E0E, &cpg->dsi0phycr); - writel(0x1E000000, &cpg->pll0cr); - writel(0x2D000000, &cpg->pll0cr); - writel(0x17100000, &cpg->pll1cr); - writel(0x27000080, &cpg->pll2cr); - writel(0x1D000000, &cpg->pll3cr); - writel(0x00080000, &cpg->pll0stpcr); - writel(0x000120C0, &cpg->pll1stpcr); - writel(0x00012000, &cpg->pll2stpcr); - writel(0x00000030, &cpg->pll3stpcr); - - writel(0x0000000B, &cpg->pllecr); - cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); - - writel(0x000120F0, &cpg->dvfscr3); - writel(0x00000020, &cpg->mpmode); - writel(0x0000028A, &cpg->vrefcr); - writel(0xE4628087, &cpg->rmstpcr0); - writel(0xFFFFFFFF, &cpg->rmstpcr1); - writel(0x53FFFFFF, &cpg->rmstpcr2); - writel(0xFFFFFFFF, &cpg->rmstpcr3); - writel(0x00800D3D, &cpg->rmstpcr4); - writel(0xFFFFF3FF, &cpg->rmstpcr5); - writel(0x00000000, &cpg->smstpcr2); - writel(0x00040000, &cpg_srcr->srcr2); - - clrbits_le32(&cpg->pllecr, (1 << 3)); - cmp_loop(&cpg->pllecr, 0x00000800, 0x0); - - writel(0x00000001, &hpb->hpbctrl6); - cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); - - writel(0x00001414, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - - writel(0x1d000000, &cpg->pll3cr); - setbits_le32(&cpg->pllecr, (1 << 3)); - cmp_loop(&cpg->pllecr, 0x800, 0x800); - - /* SBSC1 Init*/ - sbsc_init(sbsc1); - - /* SBSC2 Init*/ - sbsc_init(sbsc2); - - writel(0x00000b0b, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - writel(0xfffffffc, &cpg->cpgxxcs4); -} - -int board_early_init_f(void) -{ - struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; - struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; - struct sh73a0_sbsc_cpg_srcr *cpg_srcr = - (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; - - writel(CS0BCR_D, &bsc->cs0bcr); - writel(CS4BCR_D, &bsc->cs4bcr); - writel(CS0WCR_D, &bsc->cs0wcr); - writel(CS4WCR_D, &bsc->cs4wcr); - - clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); - - clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); - clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); - writel(VCLKCR1_D, &cpg->vclkcr1); - - /* Setup SCIF4 / workaround */ - writeb(0x12, PORT32CR); - writeb(0x22, PORT33CR); - writeb(0x12, PORT34CR); - writeb(0x22, PORT35CR); - - return 0; -} - -void adjust_core_voltage(void) -{ - u8 data; - - data = 0x35; - i2c_set_bus_num(0); - i2c_write(0x40, 3, 1, &data, 1); -} - -int board_init(void) -{ - adjust_core_voltage(); - sh73a0_pinmux_init(); - - /* SCIFA 4 */ - gpio_request(GPIO_FN_SCIFA4_TXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); - gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); - - /* Ethernet/SMSC */ - gpio_request(GPIO_PORT224, NULL); - gpio_direction_input(GPIO_PORT224); - - /* SMSC/USB */ - gpio_request(GPIO_FN_CS4_, NULL); - - /* MMCIF */ - gpio_request(GPIO_FN_MMCCLK0, NULL); - gpio_request(GPIO_FN_MMCCMD0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_1_PU, NULL); - gpio_request(GPIO_FN_MMCD0_2_PU, NULL); - gpio_request(GPIO_FN_MMCD0_3_PU, NULL); - gpio_request(GPIO_FN_MMCD0_4_PU, NULL); - gpio_request(GPIO_FN_MMCD0_5_PU, NULL); - gpio_request(GPIO_FN_MMCD0_6_PU, NULL); - gpio_request(GPIO_FN_MMCD0_7_PU, NULL); - - /* SDHI */ - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICD0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); - gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - gpio_request(GPIO_PORT15, NULL); - gpio_direction_output(GPIO_PORT15, 1); - - /* I2C */ - gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); - gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); - gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); - gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); - - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int ret = 0; -#ifdef CONFIG_SMC911X - ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return ret; -} - -void reset_cpu(void) -{ - /* Soft Power On Reset */ - writel((1 << 31), RESCNT2); -} diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index 9c4c5fdc4a..db1075a594 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -204,9 +204,6 @@ int board_eth_init(struct bd_info *bis) #ifdef CONFIG_USB_GADGET_ATMEL_USBA usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif #endif return rc; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 69ed715403..b944e44c1a 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -69,12 +69,3 @@ int checkboard(void) return 0; } #endif - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/warp/Kconfig b/board/warp/Kconfig deleted file mode 100644 index 9c2fc9df67..0000000000 --- a/board/warp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WARP - -config SYS_BOARD - default "warp" - -config SYS_CONFIG_NAME - default "warp" - -config IMX_CONFIG - default "board/warp/imximage.cfg" - -endif diff --git a/board/warp/MAINTAINERS b/board/warp/MAINTAINERS deleted file mode 100644 index ee2114d082..0000000000 --- a/board/warp/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WaRP BOARD -M: Otavio Salvador <otavio@ossystems.com.br> -S: Maintained -F: board/warp/ -F: include/configs/warp.h -F: configs/warp_defconfig diff --git a/board/warp/Makefile b/board/warp/Makefile deleted file mode 100644 index 3a2373d7bf..0000000000 --- a/board/warp/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2014 O.S. Systems Software LTDA. -# Copyright (C) 2014 Kynetics LLC. -# Copyright (C) 2014 Revolution Robotics, Inc. - -obj-y := warp.o diff --git a/board/warp/README b/board/warp/README deleted file mode 100644 index 3cfd22ec76..0000000000 --- a/board/warp/README +++ /dev/null @@ -1,56 +0,0 @@ -How to Update U-Boot on Warp board ----------------------------------- - -Required software on the host PC: - -- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader - -- dfu-util: http://dfu-util.sourceforge.net/releases/ - -Build U-Boot for Warp: - -$ make mrproper -$ make warp_config -$ make - -This will generate the U-Boot binary called u-boot.imx. - -Put warp board in USB download mode - -Connect a USB to serial adapter between the host PC and warp - -Connect a USB cable between the OTG warp port and the host PC - -Open a terminal program such as minicom - -Copy u-boot.imx to the imx_usb_loader folder. - -Load u-boot.imx via USB: - -$ sudo ./imx_usb u-boot.imx - -Then U-Boot should start and its messages will appear in the console program. - -Use the default environment variables: - -=> env default -f -a -=> saveenv - -Run the DFU command: -=> dfu 0 mmc 0 - -Transfer u-boot.imx that will be flashed into the eMMC: - -$ sudo dfu-util -D u-boot.imx -a boot - -Then on the U-Boot prompt the following message should be seen after a -successful upgrade: - -#DOWNLOAD ... OK -Ctrl+C to exit ... - -Remove power from the warp board. - -Put warp board into normal boot mode - -Power up the board and the new updated U-Boot should boot from eMMC diff --git a/board/warp/imximage.cfg b/board/warp/imximage.cfg deleted file mode 100644 index f6bc604c8b..0000000000 --- a/board/warp/imximage.cfg +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include <config.h> - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ - -BOOT_FROM sd - -/* - * Secure boot support - */ -#ifdef CONFIG_IMX_HAB -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x020c4018 0x00260324 - -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff - -DATA 4 0x020e0344 0x00003030 -DATA 4 0x020e0348 0x00003030 -DATA 4 0x020e034c 0x00003030 -DATA 4 0x020e0350 0x00003030 -DATA 4 0x020e030c 0x00000030 -DATA 4 0x020e0310 0x00000030 -DATA 4 0x020e0314 0x00000030 -DATA 4 0x020e0318 0x00000030 -DATA 4 0x020e0300 0x00000030 -DATA 4 0x020e031c 0x00000030 -DATA 4 0x020e0338 0x00000028 -DATA 4 0x020e0320 0x00000030 -DATA 4 0x020e032c 0x00000000 -DATA 4 0x020e033c 0x00000008 -DATA 4 0x020e0340 0x00000008 -DATA 4 0x020e05c4 0x00000030 -DATA 4 0x020e05cc 0x00000030 -DATA 4 0x020e05d4 0x00000030 -DATA 4 0x020e05d8 0x00000030 -DATA 4 0x020e05ac 0x00000030 -DATA 4 0x020e05c8 0x00000030 -DATA 4 0x020e05b0 0x00020000 -DATA 4 0x020e05b4 0x00000000 -DATA 4 0x020e05c0 0x00020000 -DATA 4 0x020e05d0 0x00080000 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b085c 0x1b4700c7 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x00400000 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b082c 0xf3333333 -DATA 4 0x021b0830 0xf3333333 -DATA 4 0x021b0834 0xf3333333 -DATA 4 0x021b0838 0xf3333333 -DATA 4 0x021b0848 0x4241444a -DATA 4 0x021b0850 0x3030312b -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x00000000 -DATA 4 0x021b08c0 0x24911492 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b000c 0x33374133 -DATA 4 0x021b0004 0x00020024 -DATA 4 0x021b0010 0x00100A82 -DATA 4 0x021b0014 0x00000093 -DATA 4 0x021b0018 0x00001688 -DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x009f0e10 -DATA 4 0x021b0038 0x00190778 -DATA 4 0x021b0008 0x00000000 -DATA 4 0x021b0040 0x0000004f -DATA 4 0x021b0000 0x83110000 -DATA 4 0x021b001c 0x003f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0x82018030 -DATA 4 0x021b001c 0x04028030 -DATA 4 0x021b001c 0x02038030 -DATA 4 0x021b001c 0xff0a8038 -DATA 4 0x021b001c 0x82018038 -DATA 4 0x021b001c 0x04028038 -DATA 4 0x021b001c 0x02038038 -DATA 4 0x021b0800 0xa1310003 -DATA 4 0x021b0020 0x00001800 -DATA 4 0x021b0818 0x00000000 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b0004 0x00025564 -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x00000000 diff --git a/board/warp/warp.c b/board/warp/warp.c deleted file mode 100644 index c03b648850..0000000000 --- a/board/warp/warp.c +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, 2015 O.S. Systems Software LTDA. - * Copyright (C) 2014 Kynetics LLC. - * Copyright (C) 2014 Revolution Robotics, Inc. - * - * Author: Otavio Salvador <otavio@ossystems.com.br> - */ - -#include <init.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/io.h> -#include <linux/sizes.h> -#include <common.h> -#include <watchdog.h> -#include <fsl_esdhc_imx.h> -#include <i2c.h> -#include <mmc.h> -#include <usb.h> -#include <power/pmic.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ - PAD_CTL_LVE) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ - PAD_CTL_LVE) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define CONFIG_POWER_MAX77696_I2C_ADDR 0x3C - -enum { - L01_CNFG1 = 0x43, - L01_CNFG2, - L02_CNFG1, - L02_CNFG2, - L03_CNFG1, - L03_CNFG2, - L04_CNFG1, - L04_CNFG2, - L05_CNFG1, - L05_CNFG2, - L06_CNFG1, - L06_CNFG2, - L07_CNFG1, - L07_CNFG2, - L08_CNFG1, - L08_CNFG2, - L09_CNFG1, - L09_CNFG2, - L10_CNFG1, - L10_CNFG2, - LDO_INT1, - LDO_INT2, - LDO_INT1M, - LDO_INT2M, - LDO_CNFG3, - SW1_CNTRL, - SW2_CNTRL, - SW3_CNTRL, - SW4_CNTRL, - EPDCNFG, - EPDINTS, - EPDINT, - EPDINTM, - EPDVCOM, - EPDVEE, - EPDVNEG, - EPDVPOS, - EPDVDDH, - EPDSEQ, - EPDOKINTS, - CID = 0x9c, - PMIC_NUM_OF_REGS, -}; - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static void setup_iomux_uart(void) -{ - static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR, 0, 0, 0, 1}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* Assume boot SD always present */ -} - -int board_mmc_init(struct bd_info *bis) -{ - static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -int board_usb_phy_mode(int port) -{ - return USB_INIT_DEVICE; -} - -/* I2C1 for PMIC */ -#define I2C_PMIC 0 -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .sda = { - .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, - .gp = IMX_GPIO_NR(3, 13), - }, - .scl = { - .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, - .gp = IMX_GPIO_NR(3, 12), - }, -}; - -static int power_max77696_init(unsigned char bus) -{ - static const char name[] = "MAX77696"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = PMIC_NUM_OF_REGS; - p->hw.i2c.addr = CONFIG_POWER_MAX77696_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - int ret; - unsigned int reg; - - ret = power_max77696_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("MAX77696"); - if (!p) - return -EINVAL; - - ret = pmic_reg_read(p, CID, ®); - if (ret) - return ret; - - printf("PMIC: MAX77696 detected, rev=0x%x\n", reg); - - return pmic_probe(p); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - - return 0; -} - -int board_late_init(void) -{ -#ifdef CONFIG_HW_WATCHDOG - hw_watchdog_init(); -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: WaRP Board\n"); - - return 0; -} diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 95b8e82dd1..ead52d5a49 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -66,19 +66,6 @@ int power_init_board(void) } #endif -int board_eth_init(struct bd_info *bis) -{ - int ret = 0; - -#ifdef CONFIG_USB_ETHER - ret = usb_eth_initialize(bis); - if (ret < 0) - printf("Error %d registering USB ether.\n", ret); -#endif - - return ret; -} - int board_init(void) { /* address of boot parameters */ diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 0e8c2aa00b..cc62719a89 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -21,8 +21,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 5b9f5a4469..b0e4bb8963 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -21,8 +21,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 0a061610c0..517c7d25ed 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -23,8 +23,8 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig deleted file mode 100644 index 7afb7a45ec..0000000000 --- a/configs/P3041DS_NAND_defconfig +++ /dev/null @@ -1,113 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_PCIE4=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xFFA00C21 -CONFIG_SYS_OR0_PRELIM=0xFFFC0796 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR2_PRELIM_BOOL=y -CONFIG_SYS_BR2_PRELIM=0xE8001001 -CONFIG_SYS_OR2_PRELIM=0xF8000F85 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_ELBC=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x100000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig deleted file mode 100644 index 35e2e4f161..0000000000 --- a/configs/P3041DS_SDCARD_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_PCIE4=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xD2000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig deleted file mode 100644 index 2e50dc44f7..0000000000 --- a/configs/P3041DS_SPIFLASH_defconfig +++ /dev/null @@ -1,110 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_PCIE4=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x110000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig deleted file mode 100644 index b494dfa822..0000000000 --- a/configs/P3041DS_defconfig +++ /dev/null @@ -1,105 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_PCIE4=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig deleted file mode 100644 index b872878888..0000000000 --- a/configs/P4080DS_SDCARD_defconfig +++ /dev/null @@ -1,105 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=4 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_LBA48=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xD2000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig deleted file mode 100644 index cdd956b9f9..0000000000 --- a/configs/P4080DS_SPIFLASH_defconfig +++ /dev/null @@ -1,107 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=4 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_LBA48=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x110000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig deleted file mode 100644 index 6b22602e67..0000000000 --- a/configs/P4080DS_defconfig +++ /dev/null @@ -1,102 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=4 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_LBA48=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig deleted file mode 100644 index b36f525cc1..0000000000 --- a/configs/P5040DS_NAND_defconfig +++ /dev/null @@ -1,113 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=3 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xFFA00C21 -CONFIG_SYS_OR0_PRELIM=0xFFFC0796 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR2_PRELIM_BOOL=y -CONFIG_SYS_BR2_PRELIM=0xE8001001 -CONFIG_SYS_OR2_PRELIM=0xF8000F85 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_ELBC=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x100000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig deleted file mode 100644 index 4111901fc4..0000000000 --- a/configs/P5040DS_SDCARD_defconfig +++ /dev/null @@ -1,107 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=3 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xD2000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig deleted file mode 100644 index 5d493ee89c..0000000000 --- a/configs/P5040DS_SPIFLASH_defconfig +++ /dev/null @@ -1,109 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=3 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x110000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig deleted file mode 100644 index dbcb02765d..0000000000 --- a/configs/P5040DS_defconfig +++ /dev/null @@ -1,104 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=3 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 22f5b632d6..65b20550c0 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -32,8 +32,6 @@ CONFIG_SPL_MTD_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NET=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig deleted file mode 100644 index 6a67c60dd4..0000000000 --- a/configs/armadillo-800eva_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0xE80C0000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board" -CONFIG_R8A7740=y -CONFIG_TARGET_ARMADILLO_800EVA=y -CONFIG_SYS_CLK_FREQ=50000000 -CONFIG_SYS_LOAD_ADDR=0x44000000 -CONFIG_ENV_ADDR=0x40000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe8083000 -CONFIG_SYS_MONITOR_BASE=0x00000000 -CONFIG_BOOTDELAY=3 -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=256 -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_SLEEP is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_MMC is not set -CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y -CONFIG_PHY_SMSC=y -CONFIG_SH_ETHER=y -CONFIG_SCIF_CONSOLE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig deleted file mode 100644 index f1b4b622cb..0000000000 --- a/configs/cm_t335_defconfig +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_AM33XX=y -CONFIG_TARGET_CM_T335=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 -CONFIG_TIMESTAMP=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_POWER=y -CONFIG_SPL_WATCHDOG=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_SYS_PROMPT="CM-T335 # " -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=1051 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_EEPROM_LAYOUT=y -CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_DNS2=y -CONFIG_SYS_DISABLE_AUTOLOAD=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:2m(spl),1m(u-boot),1m(u-boot-env),1m(dtb),4m(splash),6m(kernel),-(rootfs)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RETRY_COUNT=10 -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_CMD_PCA953X=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS_GPIO=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=64 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_OF_LIBFDT=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig deleted file mode 100644 index 1cd0ac020b..0000000000 --- a/configs/edminiv2_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_ORION5X=y -CONFIG_SYS_TEXT_BASE=0x00800000 -CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds" -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x2000 -CONFIG_SPL_TEXT_BASE=0xffff0000 -CONFIG_TARGET_EDMINIV2=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_IDENT_STRING=" EDMiniV2" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_ENV_ADDR=0xFFF84000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf40 -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_RESET_PHY_R=y -CONFIG_SPL_MAX_SIZE=0xfff0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000 -CONFIG_SPL_BSS_MAX_SIZE=0x1ffff -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x20000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x40000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x1ffff -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="EDMiniV2> " -CONFIG_SYS_PBSIZE=1051 -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_SYS_IDE_MAXBUS=1 -CONFIG_SYS_IDE_MAXDEVICE=1 -CONFIG_SYS_ATA_BASE_ADDR=0xf1080000 -CONFIG_SYS_ATA_STRIDE=4 -CONFIG_SYS_ATA_DATA_OFFSET=0x100 -CONFIG_SYS_ATA_REG_OFFSET=0x100 -CONFIG_SYS_ATA_ALT_OFFSET=0x100 -CONFIG_SYS_ATA_IDE0_OFFSET=0x4000 -CONFIG_LBA48=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_MAX_FLASH_SECT=11 -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 17c97ac27f..25eda11dd4 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -67,7 +67,7 @@ CONFIG_ENV_UBI_VOLUME="config" CONFIG_ENV_UBI_VOLUME_REDUND="config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_NET is not set CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y @@ -81,9 +81,6 @@ CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_MTD_UBI_FASTMAP=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 -CONFIG_SMC911X_32_BIT=y CONFIG_CONS_INDEX=3 CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig deleted file mode 100644 index 7c0ebefa69..0000000000 --- a/configs/kmtegr1_defconfig +++ /dev/null @@ -1,201 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xF0000000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="kmtegr1" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_ENV_ADDR=0xF0100000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_KMTEGR1=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_QUICC_MULT_FACTOR_3=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y -CONFIG_BAT0_DCACHE_INHIBITED=y -CONFIG_BAT0_DCACHE_GUARDED=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_4_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="KMBEC_FPGA" -CONFIG_BAT2_BASE=0xE8000000 -CONFIG_BAT2_LENGTH_128_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="FLASH" -CONFIG_BAT3_BASE=0xF0000000 -CONFIG_BAT3_LENGTH_256_MBYTES=y -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT3_DCACHE_INHIBITED=y -CONFIG_BAT3_DCACHE_GUARDED=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="STACK_IN_DCACHE" -CONFIG_BAT4_BASE=0xE6000000 -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="APP2" -CONFIG_BAT6_BASE=0xB0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_INHIBITED=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xF0000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_256_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE8000000 -CONFIG_LBLAW1_NAME="KMBEC_FPGA" -CONFIG_LBLAW1_LENGTH_128_MBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xB0000000 -CONFIG_LBLAW3_NAME="APP2" -CONFIG_LBLAW3_LENGTH_256_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xF0000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_256_MBYTES=y -CONFIG_OR0_SCY_5=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="KMBEC_FPGA" -CONFIG_BR1_OR1_BASE=0xE8000000 -CONFIG_OR1_AM_128_MBYTES=y -CONFIG_OR1_SCY_2=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="APP2" -CONFIG_BR3_OR3_BASE=0xB0000000 -CONFIG_BR3_PORTSIZE_16BIT=y -CONFIG_OR3_AM_256_MBYTES=y -CONFIG_OR3_SCY_5=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_ACR_APARK_MASTER=y -CONFIG_ACR_PARKM_USB_I2C1_BOOT=y -CONFIG_LCRR_EADC_1=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_83XX_PCICLK=0x3ef1480 -CONFIG_KM_DEF_NETDEV="eth1" -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_IMLS=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app" -CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),256k(qe-fw),128k(env),128k(envred),-(ubi0);app:-(ubi1);" -CONFIG_CMD_DIAG=y -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR_REDUND=0xF0120000 -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="UEC0" -CONFIG_VERSION_VARIABLE=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_DM_BOOTCOUNT=y -CONFIG_BOOTCOUNT_MEM=y -CONFIG_SYS_BOOTCOUNT_BE=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xF0001001 -CONFIG_SYS_OR0_PRELIM=0xF0000E55 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE8000801 -CONFIG_SYS_OR1_PRELIM=0xF8000E25 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xB0001001 -CONFIG_SYS_OR3_PRELIM=0xF0000050 -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_FIXED=y -CONFIG_DM_ETH_PHY=y -CONFIG_QE_UEC=y -# CONFIG_PCI is not set -# CONFIG_PINCTRL_FULL is not set -CONFIG_QE=y -CONFIG_SYS_QE_FW_ADDR=0xF00C0000 -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_BCH=y diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig deleted file mode 100644 index 58191c114c..0000000000 --- a/configs/kzm9g_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_LEN=0x60000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="KMC KZM-A9-GT" -CONFIG_TARGET_KZM9G=y -CONFIG_SYS_LOAD_ADDR=0x43000000 -CONFIG_ENV_ADDR=0x40000 -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/null console=ttySC4,115200" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="KZM-A9-GT# " -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=256 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_NFS_TIMEOUT=10000 -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SH=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x10000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_SCIF_CONSOLE=y -# CONFIG_FAT_WRITE is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index d7ff7e2970..ea95a68be2 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -95,7 +95,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 462fad1cd4..84f6578007 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -95,7 +95,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 63287ca533..1b49f53abe 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -125,7 +125,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index fc72f4cdaf..6a04b063aa 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 30cc15a12f..0ef4fe3db3 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -85,7 +85,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 172ab723c6..cf9fd13777 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -122,7 +122,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 447a51513f..cacd85e4cf 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -110,7 +110,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index b414d400e6..e057464544 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -94,7 +94,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 9bac24a27b..c67876b952 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -103,7 +103,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 3a71185b86..7a0b786be7 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -93,7 +93,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 35abfb323f..d582f61d4e 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 5316c80c83..9731b85b0c 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 8550190d22..bd58d3a90f 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -124,7 +124,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 049cf1e56f..0dca44a8b0 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -86,7 +86,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 6cdc78da3f..d023f53421 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -124,7 +124,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 68aae882a8..aed01d44f1 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -112,7 +112,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 7efa5cbebd..e8676e2ca1 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -94,7 +94,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 3846b95e71..8faeeb4773 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -104,7 +104,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig deleted file mode 100644 index b9c85d6160..0000000000 --- a/configs/mx28evk_auart_console_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_IMX_CONFIG="" -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x42000000 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_SPLASH_SCREEN=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig deleted file mode 100644 index 136c1d6069..0000000000 --- a/configs/mx28evk_nand_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_IMX_CONFIG="" -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x380000 -CONFIG_SYS_LOAD_ADDR=0x42000000 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_SPLASH_SCREEN=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig deleted file mode 100644 index ab8c34c8b1..0000000000 --- a/configs/mx28evk_spi_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_IMX_CONFIG="" -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x42000000 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_SPLASH_SCREEN=y -CONFIG_OF_LIBFDT=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig deleted file mode 100644 index 63f2f21a1e..0000000000 --- a/configs/warp_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_LEN=0x2300000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6SL=y -CONFIG_TARGET_WARP=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set -CONFIG_BOUNCE_BUFFER=y -CONFIG_DFU_MMC=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_MXC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y -CONFIG_FSL_USDHC=y -CONFIG_POWER_LEGACY=y -CONFIG_POWER_I2C=y -CONFIG_MXC_UART=y -CONFIG_USB=y -CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 -CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y diff --git a/doc/README.pblimage b/doc/README.pblimage index 7fdd26b71b..58202c14a2 100644 --- a/doc/README.pblimage +++ b/doc/README.pblimage @@ -61,7 +61,7 @@ Following steps describe it in detail. Board specific configuration file specifications: ------------------------------------------------ 1. Configuration files rcw.cfg and pbi.cfg must present in the -board/freescale/corenet_ds/, rcw.cfg is for RCW, pbi.cfg is for +board/freescale/<BOARD>/ directory, rcw.cfg is for RCW, pbi.cfg is for PBI instructions. File name must not be changed since they are used in Makefile. 2. These files can have empty lines and lines starting with "#" as first diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 53742b2904..6bbbadc5ee 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -7,7 +7,7 @@ config ETH def_bool y config DM_ETH - bool "Enable Driver Model for Ethernet drivers" + bool depends on DM help Enable driver model for Ethernet. @@ -18,7 +18,7 @@ config DM_ETH config DM_MDIO bool "Enable Driver Model for MDIO devices" - depends on DM_ETH && PHYLIB + depends on PHYLIB help Enable driver model for MDIO devices @@ -43,7 +43,7 @@ config DM_MDIO_MUX config DM_DSA bool "Enable Driver Model for DSA switches" - depends on DM_ETH && DM_MDIO + depends on DM_MDIO depends on PHY_FIXED help Enable driver model for DSA switches @@ -94,7 +94,7 @@ config DSA_SANDBOX menuconfig NETDEVICES bool "Network device support" depends on NET - default y if DM_ETH + select DM_ETH help You must select Y to enable any network device support Generally if you have any networking support this is a given @@ -112,7 +112,7 @@ config PHY_GIGE config AG7XXX bool "Atheros AG7xxx Ethernet MAC support" - depends on DM_ETH && ARCH_ATH79 + depends on ARCH_ATH79 select PHYLIB help This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is @@ -121,7 +121,6 @@ config AG7XXX config ALTERA_TSE bool "Altera Triple-Speed Ethernet MAC support" - depends on DM_ETH select PHYLIB help This driver supports the Altera Triple-Speed (TSE) Ethernet MAC. @@ -154,7 +153,7 @@ config BCM_SF2_ETH_GMAC config BCM6348_ETH bool "BCM6348 EMAC support" - depends on DM_ETH && ARCH_BMIPS + depends on ARCH_BMIPS select DMA select DMA_CHANNELS select MII @@ -164,7 +163,7 @@ config BCM6348_ETH config BCM6368_ETH bool "BCM6368 EMAC support" - depends on DM_ETH && ARCH_BMIPS + depends on ARCH_BMIPS select DMA select MII help @@ -172,21 +171,19 @@ config BCM6368_ETH config BCMGENET bool "BCMGENET V5 support" - depends on DM_ETH select PHYLIB help This driver supports the BCMGENET Ethernet MAC. config CORTINA_NI_ENET bool "Cortina-Access Ethernet driver" - depends on DM_ETH && CORTINA_PLATFORM + depends on CORTINA_PLATFORM help This driver supports the Cortina-Access Ethernet MAC for all supported CAxxxx SoCs. config CALXEDA_XGMAC bool "Calxeda XGMAC support" - depends on DM_ETH help This driver supports the XGMAC in Calxeda Highbank and Midway machines. @@ -198,7 +195,6 @@ config DRIVER_DM9000 config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" - depends on DM_ETH select PHYLIB help This driver supports the Synopsys Designware Ethernet QOS (Quality @@ -273,7 +269,7 @@ config EEPRO100 ethernet family of adapters. config ETH_SANDBOX - depends on DM_ETH && SANDBOX + depends on SANDBOX default y bool "Sandbox: Mocked Ethernet driver" help @@ -283,7 +279,7 @@ config ETH_SANDBOX This driver is particularly useful in the test/dm/eth.c tests config ETH_SANDBOX_RAW - depends on DM_ETH && SANDBOX + depends on SANDBOX default y bool "Sandbox: Bridge to Linux Raw Sockets" help @@ -303,7 +299,6 @@ config ETH_DESIGNWARE config ETH_DESIGNWARE_MESON8B bool "Amlogic Meson8b and later glue driver for Synopsys Designware Ethernet MAC" - depends on DM_ETH select ETH_DESIGNWARE help This provides glue layer to use Synopsys Designware Ethernet MAC @@ -314,7 +309,7 @@ config ETH_DESIGNWARE_SOCFPGA select SYSCON select DW_ALTDESCRIPTOR bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help The Altera SoCFPGA requires additional configuration of the Altera system manager to correctly interface with the PHY. @@ -322,7 +317,7 @@ config ETH_DESIGNWARE_SOCFPGA config ETH_DESIGNWARE_S700 bool "Actins S700 glue driver for Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help This provides glue layer to use Synopsys Designware Ethernet MAC present on Actions S700 SoC. @@ -386,7 +381,6 @@ config FTMAC100 config FTGMAC100 bool "Ftgmac100 Ethernet Support" - depends on DM_ETH select PHYLIB help This driver supports the Faraday's FTGMAC100 Gigabit SoC @@ -414,7 +408,6 @@ config SYS_DISCOVER_PHY config MCFFEC bool "ColdFire Ethernet Support" - depends on DM_ETH select PHYLIB select SYS_DISCOVER_PHY help @@ -427,7 +420,6 @@ config SYS_UNIFY_CACHE config FSLDMAFEC bool "ColdFire DMA Ethernet Support" - depends on DM_ETH select PHYLIB select SYS_DISCOVER_PHY help @@ -439,15 +431,6 @@ config KS8851_MLL help The Microchip KS8851 parallel bus external ethernet interface chip. -if KS8851_MLL -if !DM_ETH -config KS8851_MLL_BASEADDR - hex "Microchip KS8851-MLL Base Address" - help - Define this to hold the physical address of the device (I/O space) -endif #DM_ETH -endif #KS8851_MLL - config KSZ9477 bool "Microchip KSZ9477 I2C controller driver" depends on DM_DSA && DM_I2C @@ -455,15 +438,10 @@ config KSZ9477 This driver implements a DSA switch driver for the KSZ9477 family of GbE switches using the I2C interface. -config LPC32XX_ETH - bool "LPC32xx Ethernet MAC interface driver" - depends on ARCH_LPC32XX - default y - config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X - select PHYLIB if DM_ETH + select PHYLIB help This driver supports the network interface units in the Marvell Orion5x and Kirkwood SoCs @@ -568,7 +546,6 @@ config OCTEONTX2_CGX_INTF config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" - depends on DM_ETH select PHYLIB help This MAC is present in Intel Platform Controller Hub EG20T. It @@ -629,25 +606,14 @@ config SJA1105 config SMC911X bool "SMSC LAN911x and LAN921x controller driver" -if SMC911X - -if !DM_ETH -config SMC911X_BASE - hex "SMC911X Base Address" - help - Define this to hold the physical address - of the device (I/O space) -endif #DM_ETH - config SMC911X_32_BIT bool "Enable SMC911X 32-bit interface" + depends on SMC911X help Define this if data bus is 32 bits. If your processor use a narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit words, leave this to "n". -endif #SMC911X - config SUN7I_GMAC bool "Enable Allwinner GMAC Ethernet support" help @@ -663,14 +629,12 @@ config SUN7I_GMAC_FORCE_TXERR config SUN4I_EMAC bool "Allwinner Sun4i Ethernet MAC support" - depends on DM_ETH select PHYLIB help This driver supports the Allwinner based SUN4I Ethernet MAC. config SUN8I_EMAC bool "Allwinner Sun8i Ethernet MAC support" - depends on DM_ETH select PHYLIB select PHY_GIGE help @@ -692,7 +656,6 @@ config TULIP This driver supports DEC DC2114x Fast ethernet chips. config XILINX_AXIEMAC - depends on DM_ETH select PHYLIB select MII bool "Xilinx AXI Ethernet" @@ -700,7 +663,7 @@ config XILINX_AXIEMAC This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. config XILINX_AXIMRMAC - depends on DM_ETH && ARCH_VERSAL + depends on ARCH_VERSAL bool "Xilinx AXI MRMAC" help MRMAC is a high performance, low latency, adaptable Ethernet @@ -709,7 +672,6 @@ config XILINX_AXIMRMAC Versal designs. config XILINX_EMACLITE - depends on DM_ETH select PHYLIB select MII bool "Xilinx Ethernetlite" @@ -717,7 +679,6 @@ config XILINX_EMACLITE This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. config ZYNQ_GEM - depends on DM_ETH select PHYLIB bool "Xilinx Ethernet GEM" help @@ -725,7 +686,7 @@ config ZYNQ_GEM config PIC32_ETH bool "Microchip PIC32 Ethernet Support" - depends on DM_ETH && MACH_PIC32 + depends on MACH_PIC32 select PHYLIB help This driver implements 10/100 Mbps Ethernet and MAC layer for @@ -733,14 +694,14 @@ config PIC32_ETH config GMAC_ROCKCHIP bool "Rockchip Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help This driver provides Rockchip SoCs network support based on the Synopsys Designware driver. config RENESAS_RAVB bool "Renesas Ethernet AVB MAC" - depends on DM_ETH && RCAR_GEN3 + depends on RCAR_GEN3 select PHYLIB help This driver implements support for the Ethernet AVB block in @@ -758,7 +719,7 @@ config MPC8XX_FEC config SNI_AVE bool "Socionext AVE Ethernet support" - depends on DM_ETH && ARCH_UNIPHIER + depends on ARCH_UNIPHIER select PHYLIB select SYSCON select REGMAP @@ -768,7 +729,7 @@ config SNI_AVE config SNI_NETSEC bool "Socionext NETSEC Ethernet support" - depends on DM_ETH && SYNQUACER_SPI + depends on SYNQUACER_SPI select PHYLIB help This driver implements support for the Socionext SynQuacer NETSEC @@ -857,7 +818,6 @@ config TSEC_ENET config MEDIATEK_ETH bool "MediaTek Ethernet GMAC Driver" - depends on DM_ETH select PHYLIB select DM_GPIO select DM_RESET @@ -867,7 +827,6 @@ config MEDIATEK_ETH config HIGMACV300_ETH bool "HiSilicon Gigabit Ethernet Controller" - depends on DM_ETH select DM_RESET select PHYLIB help @@ -876,7 +835,7 @@ config HIGMACV300_ETH config FSL_ENETC bool "NXP ENETC Ethernet controller" - depends on DM_ETH && DM_MDIO + depends on DM_MDIO help This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 7b55063527..96b7678e98 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o -obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig index ae4c35799b..8fc34dc26f 100644 --- a/drivers/net/fsl-mc/Kconfig +++ b/drivers/net/fsl-mc/Kconfig @@ -6,6 +6,8 @@ menuconfig FSL_MC_ENET bool "NXP Management Complex" depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A default y + select DM_MDIO + select FSL_LS_MDIO select RESV_RAM help Enable Management Complex (MC) network diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 9dd9b33955..518548e3bb 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -28,9 +28,6 @@ * @extra_byte : number of extra byte prepended rx pkt. */ struct ks_net { -#ifndef CONFIG_DM_ETH - struct eth_device dev; -#endif phys_addr_t iobase; int bus_width; u16 sharedbus; @@ -505,77 +502,6 @@ static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6]) ks_wrreg16(ks, KS_MARL, addrl); } -#ifndef CONFIG_DM_ETH -static int ks8851_mll_init(struct eth_device *dev, struct bd_info *bd) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - return ks8851_mll_init_common(ks); -} - -static void ks8851_mll_halt(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - ks8851_mll_halt_common(ks); -} - -static int ks8851_mll_send(struct eth_device *dev, void *packet, int length) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - return ks8851_mll_send_common(ks, packet, length); -} - -static int ks8851_mll_recv(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - int ret; - - ret = ks8851_mll_recv_common(ks, net_rx_packets[0]); - if (ret) - net_process_received_packet(net_rx_packets[0], ret); - - return ret; -} - -static int ks8851_mll_write_hwaddr(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr); - - return 0; -} - -int ks8851_mll_initialize(u8 dev_num, int base_addr) -{ - struct ks_net *ks; - - ks = calloc(1, sizeof(*ks)); - if (!ks) - return -ENOMEM; - - ks->iobase = base_addr; - - /* Try to detect chip. Will fail if not present. */ - if (ks8851_mll_detect_chip(ks)) { - free(ks); - return -1; - } - - ks->dev.init = ks8851_mll_init; - ks->dev.halt = ks8851_mll_halt; - ks->dev.send = ks8851_mll_send; - ks->dev.recv = ks8851_mll_recv; - ks->dev.write_hwaddr = ks8851_mll_write_hwaddr; - sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num); - - eth_register(&ks->dev); - - return 0; -} -#else /* ifdef CONFIG_DM_ETH */ static int ks8851_start(struct udevice *dev) { struct ks_net *ks = dev_get_priv(dev); @@ -703,4 +629,3 @@ U_BOOT_DRIVER(ks8851) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c deleted file mode 100644 index 1a57343439..0000000000 --- a/drivers/net/lpc32xx_eth.c +++ /dev/null @@ -1,651 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * LPC32xx Ethernet MAC interface driver - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr> - */ - -#include <common.h> -#include <log.h> -#include <net.h> -#include <malloc.h> -#include <miiphy.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/types.h> -#include <asm/system.h> -#include <asm/byteorder.h> -#include <asm/arch/cpu.h> -#include <asm/arch/config.h> - -/* - * Notes: - * - * 1. Unless specified otherwise, all references to tables or paragraphs - * are to UM10326, "LPC32x0 and LPC32x0/01 User manual". - * - * 2. Only bitfield masks/values which are actually used by the driver - * are defined. - */ - -/* a single RX descriptor. The controller has an array of these */ -struct lpc32xx_eth_rxdesc { - u32 packet; /* Receive packet pointer */ - u32 control; /* Descriptor command status */ -}; - -#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc)) - -/* RX control bitfields/masks (see Table 330) */ -#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF -#define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800 -#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000 - -/* a single RX status. The controller has an array of these */ -struct lpc32xx_eth_rxstat { - u32 statusinfo; /* Transmit Descriptor status */ - u32 statushashcrc; /* Transmit Descriptor CRCs */ -}; - -#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat)) - -/* RX statusinfo bitfields/masks (see Table 333) */ -#define RX_STAT_RXSIZE 0x000007FF -/* Helper: OR of all errors except RANGE */ -#define RX_STAT_ERRORS 0x1B800000 - -/* a single TX descriptor. The controller has an array of these */ -struct lpc32xx_eth_txdesc { - u32 packet; /* Transmit packet pointer */ - u32 control; /* Descriptor control */ -}; - -#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc)) - -/* TX control bitfields/masks (see Table 335) */ -#define TX_CTRL_TXSIZE 0x000007FF -#define TX_CTRL_LAST 0x40000000 - -/* a single TX status. The controller has an array of these */ -struct lpc32xx_eth_txstat { - u32 statusinfo; /* Transmit Descriptor status */ -}; - -#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat)) - -/* Ethernet MAC interface registers (see Table 283) */ -struct lpc32xx_eth_registers { - /* MAC registers - 0x3106_0000 to 0x3106_01FC */ - u32 mac1; /* MAC configuration register 1 */ - u32 mac2; /* MAC configuration register 2 */ - u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */ - u32 ipgr; /* Non-back-to-back IPG register */ - u32 clrt; /* Collision Window / Retry register */ - u32 maxf; /* Maximum Frame register */ - u32 supp; /* Phy Support register */ - u32 test; - u32 mcfg; /* MII management configuration reg. */ - u32 mcmd; /* MII management command register */ - u32 madr; /* MII management address register */ - u32 mwtd; /* MII management wite data register */ - u32 mrdd; /* MII management read data register */ - u32 mind; /* MII management indicators register */ - u32 reserved1[2]; - u32 sa0; /* Station address register 0 */ - u32 sa1; /* Station address register 1 */ - u32 sa2; /* Station address register 2 */ - u32 reserved2[45]; - /* Control registers */ - u32 command; - u32 status; - u32 rxdescriptor; - u32 rxstatus; - u32 rxdescriptornumber; /* actually, number MINUS ONE */ - u32 rxproduceindex; /* head of rx desc fifo */ - u32 rxconsumeindex; /* tail of rx desc fifo */ - u32 txdescriptor; - u32 txstatus; - u32 txdescriptornumber; /* actually, number MINUS ONE */ - u32 txproduceindex; /* head of rx desc fifo */ - u32 txconsumeindex; /* tail of rx desc fifo */ - u32 reserved3[10]; - u32 tsv0; /* Transmit status vector register 0 */ - u32 tsv1; /* Transmit status vector register 1 */ - u32 rsv; /* Receive status vector register */ - u32 reserved4[3]; - u32 flowcontrolcounter; - u32 flowcontrolstatus; - u32 reserved5[34]; - /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */ - u32 rxfilterctrl; - u32 rxfilterwolstatus; - u32 rxfilterwolclear; - u32 reserved6; - u32 hashfilterl; - u32 hashfilterh; - u32 reserved7[882]; - /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */ - u32 intstatus; /* Interrupt status register */ - u32 intenable; - u32 intclear; - u32 intset; - u32 reserved8; - u32 powerdown; - u32 reserved9; -}; - -/* MAC1 register bitfields/masks and offsets (see Table 283) */ -#define MAC1_RECV_ENABLE 0x00000001 -#define MAC1_PASS_ALL_RX_FRAMES 0x00000002 -#define MAC1_SOFT_RESET 0x00008000 -/* Helper: general reset */ -#define MAC1_RESETS 0x0000CF00 - -/* MAC2 register bitfields/masks and offsets (see Table 284) */ -#define MAC2_FULL_DUPLEX 0x00000001 -#define MAC2_CRC_ENABLE 0x00000010 -#define MAC2_PAD_CRC_ENABLE 0x00000020 - -/* SUPP register bitfields/masks and offsets (see Table 290) */ -#define SUPP_SPEED 0x00000100 - -/* MCFG register bitfields/masks and offsets (see Table 292) */ -#define MCFG_RESET_MII_MGMT 0x00008000 -/* divide clock by 28 (see Table 293) */ -#define MCFG_CLOCK_SELECT_DIV28 0x0000001C - -/* MADR register bitfields/masks and offsets (see Table 295) */ -#define MADR_REG_MASK 0x0000001F -#define MADR_PHY_MASK 0x00001F00 -#define MADR_REG_OFFSET 0 -#define MADR_PHY_OFFSET 8 - -/* MIND register bitfields/masks (see Table 298) */ -#define MIND_BUSY 0x00000001 - -/* COMMAND register bitfields/masks and offsets (see Table 283) */ -#define COMMAND_RXENABLE 0x00000001 -#define COMMAND_TXENABLE 0x00000002 -#define COMMAND_PASSRUNTFRAME 0x00000040 -#define COMMAND_RMII 0x00000200 -#define COMMAND_FULL_DUPLEX 0x00000400 -/* Helper: general reset */ -#define COMMAND_RESETS 0x00000038 - -/* STATUS register bitfields/masks and offsets (see Table 283) */ -#define STATUS_RXSTATUS 0x00000001 -#define STATUS_TXSTATUS 0x00000002 - -/* RXFILTERCTRL register bitfields/masks (see Table 319) */ -#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002 -#define RXFILTERCTRL_ACCEPTPERFECT 0x00000020 - -/* Buffers and descriptors */ - -#define ATTRS(n) __aligned(n) - -#define TX_BUF_COUNT 4 -#define RX_BUF_COUNT 4 - -struct lpc32xx_eth_buffers { - ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT]; - ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT]; - ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN]; - ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT]; - ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT]; - ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN]; -}; - -/* port device data struct */ -struct lpc32xx_eth_device { - struct eth_device dev; - struct lpc32xx_eth_registers *regs; - struct lpc32xx_eth_buffers *bufs; - bool phy_rmii; -}; - -#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device)) - -/* generic macros */ -#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev) - -/* timeout for MII polling */ -#define MII_TIMEOUT 10000000 - -/* limits for PHY and register addresses */ -#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET) - -#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET) - -#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -/* - * mii_reg_read - miiphy_read callback function. - * - * Returns 16bit phy register value, or 0xffff on error - */ -static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad, - int reg_ofs) -{ - u16 data = 0; - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); - struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; - u32 mind_reg; - u32 timeout; - - /* check parameters */ - if (phy_adr > MII_MAX_PHY) { - printf("%s:%u: Invalid PHY address %d\n", - __func__, __LINE__, phy_adr); - return -EFAULT; - } - if (reg_ofs > MII_MAX_REG) { - printf("%s:%u: Invalid register offset %d\n", - __func__, __LINE__, reg_ofs); - return -EFAULT; - } - - /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - ®s->madr); - - /* write 1 to the MII command register to cause a read */ - writel(1, ®s->mcmd); - - /* wait till the MII is not busy */ - timeout = MII_TIMEOUT; - do { - /* read MII indicators register */ - mind_reg = readl(®s->mind); - if (--timeout == 0) - break; - } while (mind_reg & MIND_BUSY); - - /* write 0 to the MII command register to finish the read */ - writel(0, ®s->mcmd); - - if (timeout == 0) { - printf("%s:%u: MII busy timeout\n", __func__, __LINE__); - return -EFAULT; - } - - data = (u16) readl(®s->mrdd); - - debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr, - reg_ofs, data); - - return data; -} - -/* - * mii_reg_write - imiiphy_write callback function. - * - * Returns 0 if write succeed, -EINVAL on bad parameters - * -ETIME on timeout - */ -static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad, - int reg_ofs, u16 data) -{ - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); - struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; - u32 mind_reg; - u32 timeout; - - /* check parameters */ - if (phy_adr > MII_MAX_PHY) { - printf("%s:%u: Invalid PHY address %d\n", - __func__, __LINE__, phy_adr); - return -EFAULT; - } - if (reg_ofs > MII_MAX_REG) { - printf("%s:%u: Invalid register offset %d\n", - __func__, __LINE__, reg_ofs); - return -EFAULT; - } - - /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - ®s->madr); - - /* write data to the MII write register */ - writel(data, ®s->mwtd); - - /* wait till the MII is not busy */ - timeout = MII_TIMEOUT; - do { - /* read MII indicators register */ - mind_reg = readl(®s->mind); - if (--timeout == 0) - break; - } while (mind_reg & MIND_BUSY); - - if (timeout == 0) { - printf("%s:%u: MII busy timeout\n", __func__, - __LINE__); - return -EFAULT; - } - - /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, - reg_ofs, data);*/ - - return 0; -} -#endif - -/* - * Provide default Ethernet buffers base address if target did not. - * Locate buffers in SRAM at 0x00001000 to avoid cache issues and - * maximize throughput. - */ -#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE) -#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000 -#endif - -static struct lpc32xx_eth_device lpc32xx_eth = { - .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE, - .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE, -#if defined(CONFIG_RMII) - .phy_rmii = true, -#endif -}; - -#define TX_TIMEOUT 10000 - -static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int timeout, tx_index; - - /* time out if transmit descriptor array remains full too long */ - timeout = TX_TIMEOUT; - while ((readl(®s->status) & STATUS_TXSTATUS) && - (readl(®s->txconsumeindex) - == readl(®s->txproduceindex))) { - if (timeout-- == 0) - return -1; - } - - /* determine next transmit packet index to use */ - tx_index = readl(®s->txproduceindex); - - /* set up transmit packet */ - memcpy((void *)&bufs->tx_buf[tx_index * PKTSIZE_ALIGN], - (void *)dataptr, datasize); - writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE), - &bufs->tx_desc[tx_index].control); - writel(0, &bufs->tx_stat[tx_index].statusinfo); - - /* pass transmit packet to DMA engine */ - tx_index = (tx_index + 1) % TX_BUF_COUNT; - writel(tx_index, ®s->txproduceindex); - - /* transmission succeeded */ - return 0; -} - -#define RX_TIMEOUT 1000000 - -static int lpc32xx_eth_recv(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int timeout, rx_index; - - /* time out if receive descriptor array remains empty too long */ - timeout = RX_TIMEOUT; - while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) { - if (timeout-- == 0) - return -1; - } - - /* determine next receive packet index to use */ - rx_index = readl(®s->rxconsumeindex); - - /* if data was valid, pass it on */ - if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) { - net_process_received_packet( - &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]), - (bufs->rx_stat[rx_index].statusinfo - & RX_STAT_RXSIZE) + 1); - } - - /* pass receive slot back to DMA engine */ - rx_index = (rx_index + 1) % RX_BUF_COUNT; - writel(rx_index, ®s->rxconsumeindex); - - /* reception successful */ - return 0; -} - -static int lpc32xx_eth_write_hwaddr(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - - /* Save station address */ - writel((unsigned long) (dev->enetaddr[0] | - (dev->enetaddr[1] << 8)), ®s->sa2); - writel((unsigned long) (dev->enetaddr[2] | - (dev->enetaddr[3] << 8)), ®s->sa1); - writel((unsigned long) (dev->enetaddr[4] | - (dev->enetaddr[5] << 8)), ®s->sa0); - - return 0; -} - -static int lpc32xx_eth_init(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int index; - - /* Initial MAC initialization */ - writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1); - writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2); - writel(PKTSIZE_ALIGN, ®s->maxf); - - /* Retries: 15 (0xF). Collision window: 57 (0x37). */ - writel(0x370F, ®s->clrt); - - /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ - writel(0x0012, ®s->ipgr); - - /* pass runt (smaller than 64 bytes) frames */ - if (lpc32xx_eth_device->phy_rmii) - writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command); - else - writel(COMMAND_PASSRUNTFRAME, ®s->command); - - /* Configure Full/Half Duplex mode */ - if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) { - setbits_le32(®s->mac2, MAC2_FULL_DUPLEX); - setbits_le32(®s->command, COMMAND_FULL_DUPLEX); - writel(0x15, ®s->ipgt); - } else { - writel(0x12, ®s->ipgt); - } - - /* Configure 100MBit/10MBit mode */ - if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET) - writel(SUPP_SPEED, ®s->supp); - else - writel(0, ®s->supp); - - /* Save station address */ - writel((unsigned long) (dev->enetaddr[0] | - (dev->enetaddr[1] << 8)), ®s->sa2); - writel((unsigned long) (dev->enetaddr[2] | - (dev->enetaddr[3] << 8)), ®s->sa1); - writel((unsigned long) (dev->enetaddr[4] | - (dev->enetaddr[5] << 8)), ®s->sa0); - - /* set up transmit buffers */ - for (index = 0; index < TX_BUF_COUNT; index++) { - bufs->tx_desc[index].control = 0; - bufs->tx_stat[index].statusinfo = 0; - } - writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor); - writel((u32)(&bufs->tx_stat), ®s->txstatus); - writel(TX_BUF_COUNT-1, ®s->txdescriptornumber); - - /* set up receive buffers */ - for (index = 0; index < RX_BUF_COUNT; index++) { - bufs->rx_desc[index].packet = - (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN); - bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1; - bufs->rx_stat[index].statusinfo = 0; - bufs->rx_stat[index].statushashcrc = 0; - } - writel((u32)(&bufs->rx_desc), ®s->rxdescriptor); - writel((u32)(&bufs->rx_stat), ®s->rxstatus); - writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber); - - /* set up transmit buffers */ - for (index = 0; index < TX_BUF_COUNT; index++) - bufs->tx_desc[index].packet = - (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN); - - /* Enable broadcast and matching address packets */ - writel(RXFILTERCTRL_ACCEPTBROADCAST | - RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl); - - /* Clear and disable interrupts */ - writel(0xFFFF, ®s->intclear); - writel(0, ®s->intenable); - - /* Enable receive and transmit mode of MAC ethernet core */ - setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE); - setbits_le32(®s->mac1, MAC1_RECV_ENABLE); - - /* - * Perform a 'dummy' first send to work around Ethernet.1 - * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011). - * Use zeroed "index" variable as the dummy. - */ - - index = 0; - lpc32xx_eth_send(dev, &index, 4); - - return 0; -} - -static int lpc32xx_eth_halt(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - - /* Reset all MAC logic */ - writel(MAC1_RESETS, ®s->mac1); - writel(COMMAND_RESETS, ®s->command); - /* Let reset condition settle */ - udelay(2000); - - return 0; -} - -#if defined(CONFIG_PHYLIB) -int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct mii_dev *bus; - struct phy_device *phydev; - int ret; - - bus = mdio_alloc(); - if (!bus) { - printf("mdio_alloc failed\n"); - return -ENOMEM; - } - bus->read = mii_reg_read; - bus->write = mii_reg_write; - strcpy(bus->name, dev->name); - - ret = mdio_register(bus); - if (ret) { - printf("mdio_register failed\n"); - free(bus); - return -ENOMEM; - } - - if (lpc32xx_eth_device->phy_rmii) - phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII); - else - phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII); - - if (!phydev) { - printf("phy_connect failed\n"); - return -ENODEV; - } - - phy_config(phydev); - phy_startup(phydev); - - return 0; -} -#endif - -int lpc32xx_eth_initialize(struct bd_info *bis) -{ - struct eth_device *dev = &lpc32xx_eth.dev; - struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs; - - /* - * Set RMII management clock rate. With HCLK at 104 MHz and - * a divider of 28, this will be 3.72 MHz. - */ - writel(MCFG_RESET_MII_MGMT, ®s->mcfg); - writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg); - - /* Reset all MAC logic */ - writel(MAC1_RESETS, ®s->mac1); - writel(COMMAND_RESETS, ®s->command); - - /* wait 10 ms for the whole I/F to reset */ - udelay(10000); - - /* must be less than sizeof(dev->name) */ - strcpy(dev->name, "eth0"); - - dev->init = (void *)lpc32xx_eth_init; - dev->halt = (void *)lpc32xx_eth_halt; - dev->send = (void *)lpc32xx_eth_send; - dev->recv = (void *)lpc32xx_eth_recv; - dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr; - - /* Release SOFT reset to let MII talk to PHY */ - clrbits_le32(®s->mac1, MAC1_SOFT_RESET); - - /* register driver before talking to phy */ - eth_register(dev); - -#if defined(CONFIG_PHYLIB) - lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR); -#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = mii_reg_read; - mdiodev->write = mii_reg_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - - return 0; -} diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index bd0a10c9d2..8342c3389c 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -119,12 +119,10 @@ static void qe_sdma_init(void) */ static u8 thread_snum[] = { /* Evthreads 16-29 are not supported in MPC8309 */ -#if !defined(CONFIG_ARCH_MPC8309) 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, 0x34, 0x35, -#endif 0x88, 0x89, 0x98, 0x99, 0xa8, 0xa9, 0xb8, 0xb9, 0xc8, 0xc9, 0xd8, 0xd9, diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h deleted file mode 100644 index 42e507bac0..0000000000 --- a/include/configs/P3041DS.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -/* - * P3041 DS board configuration file - * - */ -#define CONFIG_SYS_DPAA_RMAN - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h deleted file mode 100644 index fd558398e4..0000000000 --- a/include/configs/P4080DS.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P4080 DS board configuration file - * Also supports P4040 DS - */ - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h deleted file mode 100644 index c8fc879d2f..0000000000 --- a/include/configs/P5040DS.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P5040 DS board configuration file - * - */ - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h deleted file mode 100644 index da02a96889..0000000000 --- a/include/configs/armadillo-800eva.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the bonito board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __ARMADILLO_800EVA_H -#define __ARMADILLO_800EVA_H - -#define CONFIG_SH_GPIO_PFC - -#include <asm/arch/rmobile.h> - -#define BOARD_LATE_INIT - -#define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) - -/* STACK */ -#define STACK_AREA_SIZE 0xC000 -#define LOW_LEVEL_MERAM_STACK \ - (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000 -#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define SCIF0_BASE 0xe6c40000 -#define SCIF1_BASE 0xe6c50000 -#define SCIF2_BASE 0xe6c60000 -#define SCIF4_BASE 0xe6c80000 -#define CONFIG_SCIF_A - -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* FLASH */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } - -/* ENV setting */ - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x0 -#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000 -#define CONFIG_SH_ETHER_SH7734_MII (0x01) -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - -#endif /* __ARMADILLO_800EVA_H */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h deleted file mode 100644 index 84b4271c36..0000000000 --- a/include/configs/cm_t335.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Config file for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich <ilya@compulab.co.il> - */ - -#ifndef __CONFIG_CM_T335_H -#define __CONFIG_CM_T335_H - -#include <configs/ti_am335x_common.h> - -#undef CONFIG_MAX_RAM_BANK_SIZE -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ - -/* Clock Defines */ -#define V_OSCK 25000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define MMCARGS \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ - "mmcrootfstype=ext4\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" - -#define NANDARGS \ - "nandroot=ubi0:rootfs rw\0" \ - "nandrootfstype=ubifs\0" \ - "nandargs=setenv bootargs console=${console} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} " \ - "ubi.mtd=${rootfs_name}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nboot ${loadaddr} nand0 900000; " \ - "bootm ${loadaddr}\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=82000000\0" \ - "console=ttyO0,115200n8\0" \ - "rootfs_name=rootfs\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - MMCARGS \ - NANDARGS - -/* Serial console configuration */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ - -/* I2C Configuration */ - -/* SPL */ - -/* Network. */ - -/* NAND support */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -/* GPIO pin + bank to pin ID mapping */ -#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) - -/* Status LED */ -/* Status LED polarity is inversed, so init it in the "off" state */ - -/* EEPROM */ - -/* - * Enable PCA9555 at I2C0-0x26. - * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. - */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } - -#endif /* __CONFIG_CM_T335_H */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h deleted file mode 100644 index d2f1cd5d5c..0000000000 --- a/include/configs/edminiv2.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * Based on original Kirkwood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - */ - -#ifndef _CONFIG_EDMINIV2_H -#define _CONFIG_EDMINIV2_H - -/* - * SPL - */ - -#define CONFIG_SYS_UBOOT_BASE 0xfff90000 -#define CONFIG_SYS_UBOOT_START 0x00800000 - -/* - * High Level Configuration Options (easy to change) - */ - -#include <asm/arch/orion5x.h> -/* - * CLKs configurations - */ - -/* - * Board-specific values for Orion5x MPP low level init: - * - MPPs 12 to 15 are SATA LEDs (mode 5) - * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for - * MPP16 to MPP19, mode 0 for others - */ - -#define ORION5X_MPP0_7 0x00000003 -#define ORION5X_MPP8_15 0x55550000 -#define ORION5X_MPP16_23 0x00005555 - -/* - * Board-specific values for Orion5x GPIO low level init: - * - GPIO3 is input (RTC interrupt) - * - GPIO16 is Power LED control (0 = on, 1 = off) - * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) - * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) - * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) - * - GPIO22 is SATA disk power status () - * - GPIO23 is supply status for SATA disk () - * - GPIO24 is supply control for board (write 1 to power off) - * Last GPIO is 25, further bits are supposed to be 0. - * Enable mask has ones for INPUT, 0 for OUTPUT. - * Default is LED ON, board ON :) - */ - -#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca -#define ORION5X_GPIO_OUT_VALUE 0x00000000 -#define ORION5X_GPIO_IN_POLARITY 0x000000d0 - -/* - * NS16550 Configuration - */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } - -/* - * FLASH configuration - */ - -#define CONFIG_SYS_FLASH_BASE 0xfff80000 - -/* auto boot */ - -/* - * Network - */ - -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ -#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ -#define CONFIG_PHY_BASE_ADR 0x8 -#endif - -/* - * IDE - */ -#ifdef CONFIG_IDE -#define __io -/* Data, registers and alternate blocks are at the same offset */ -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -/* A single bus, a single device */ -/* ATA registers base is at SATA controller base */ -/* ATA bus 0 is orion5x port 1 on ED Mini V2 */ -/* end of IDE defines */ -#endif /* CMD_IDE */ - -/* - * Common USB/EHCI configuration - */ -#ifdef CONFIG_CMD_USB -#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE -#endif /* CONFIG_CMD_USB */ - -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE -#endif - -/* - * Environment variables configurations - */ - -/* Enable command line editing */ - -/* provide extensive help */ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0 - -#endif /* _CONFIG_EDMINIV2_H */ diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h deleted file mode 100644 index 0468ed5e83..0000000000 --- a/include/configs/km/km-mpc8309.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * High Level Configuration Options - */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" - -/* QE microcode/firmware address */ -/* between the u-boot partition and env */ - -/* - * System IO Config - */ -/* 0x14000180 SICR_1 */ -#ifndef CONFIG_SYS_SICRL -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_GPIO \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) -#endif - -/* 0x00080400 SICR_2 */ -#define CONFIG_SYS_SICRH (0 \ - | SICR_2_FEC3_FEC3 \ - | SICR_2_HDLC1_A_HDLC1 \ - | SICR_2_ELBC_A_LA \ - | SICR_2_ELBC_B_LCLK \ - | SICR_2_HDLC2_A_HDLC2 \ - | SICR_2_USB_D_GPIO \ - | SICR_2_PCI_PCI \ - | SICR_2_HDLC1_B_HDLC1 \ - | SICR_2_HDLC1_C_HDLC1 \ - | SICR_2_HDLC2_B_GPIO \ - | SICR_2_HDLC2_C_HDLC2 \ - | SICR_2_QUIESCE_B \ - ) - -/* GPR_1 */ -#define CONFIG_SYS_GPR1 0x50008060 - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_RD_NEVER | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ - -/* ethernet port connected to piggy (UEC2) */ -#define CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h deleted file mode 100644 index bdd35cc7fb..0000000000 --- a/include/configs/kmtegr1.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada <peterb@logicpd.com> - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_HOSTNAME "kmtegr1" -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - -#define CONFIG_NAND_ECC_BCH -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 - -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_LCS \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc8309.h" - -/* must be after the include because KMBEC_FPGA is otherwise undefined */ -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h deleted file mode 100644 index 602c1c5391..0000000000 --- a/include/configs/kzm9g.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __KZM9G_H -#define __KZM9G_H - -#define CONFIG_SH73A0 - -#include <asm/arch/rmobile.h> - -/* MEMORY */ -#define KZM_SDRAM_BASE (0x40000000) -#define PHYS_SDRAM KZM_SDRAM_BASE -#define PHYS_SDRAM_SIZE (512 * 1024 * 1024) - -/* NOR Flash */ -#define KZM_FLASH_BASE (0x00000000) -#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) - -/* prompt */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ - -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000) -#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) -#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) -#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) - -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 - -/* FLASH */ -#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ - -/* Timeout for Flash erase operations (in ms) */ -/* Timeout for Flash write operations (in ms) */ -/* Timeout for Flash set sector lock bit operations (in ms) */ -/* Timeout for Flash clear lock bit operations (in ms) */ - -/* GPIO / PFC */ -#define CONFIG_SH_GPIO_PFC - -/* Clock */ -#define CONFIG_GLOBAL_TIMER -#define CONFIG_SYS_CPU_CLK (1196000000) -#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ - -#endif /* __KZM9G_H */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d9a973c13f..aaf28a346d 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -285,14 +285,6 @@ #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 - -#define CONFIG_FSL_SGMII_RISER 1 -#define SGMII_RISER_PHY_OFFSET 0x1b - -#ifdef CONFIG_FSL_SGMII_RISER -#define CONFIG_SYS_TBIPA_VALUE 8 -#endif - #endif #define CONFIG_PEN_ADDR_BIG_ENDIAN diff --git a/include/configs/warp.h b/include/configs/warp.h deleted file mode 100644 index d2c4391935..0000000000 --- a/include/configs/warp.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 O.S. Systems Software LTDA. - * Copyright (C) 2014 Kynetics LLC. - * Copyright (C) 2014 Revolution Robotics, Inc. - * - * Author: Otavio Salvador <otavio@ossystems.com.br> - * - * Configuration settings for the WaRP Board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* Watchdog */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -/* VDD voltage 1.65 - 1.95 */ -#define CONFIG_SYS_SD_VOLTAGE 0x00000080 - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#endif - -#define CONFIG_USBD_HS - -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* I2C Configs */ - -/* PMIC */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sl-warp.dtb\0" \ - "fdt_addr=0x88000000\0" \ - "initrd_addr=0x83800000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ - "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#endif /* __CONFIG_H */ diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 022771fff5..45307f51c1 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -16,7 +16,7 @@ #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309) +#elif defined(CONFIG_ARCH_MPC832X) #define QE_MURAM_SIZE 0x4000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 2181a90b59..5926c8090a 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -340,85 +340,6 @@ #define SICRH_TSOBI2_V3P3 (0 << 0) #define SICRH_TSOBI2_V2P5 (1 << 0) -#elif defined(CONFIG_ARCH_MPC8309) -/* SICR_1 */ -#define SICR_1_UART1_UART1S (0 << (30-2)) -#define SICR_1_UART1_UART1RTS (1 << (30-2)) -#define SICR_1_I2C_I2C (0 << (30-4)) -#define SICR_1_I2C_CKSTOP (1 << (30-4)) -#define SICR_1_IRQ_A_IRQ (0 << (30-6)) -#define SICR_1_IRQ_A_MCP (1 << (30-6)) -#define SICR_1_IRQ_B_IRQ (0 << (30-8)) -#define SICR_1_IRQ_B_CKSTOP (1 << (30-8)) -#define SICR_1_GPIO_A_GPIO (0 << (30-10)) -#define SICR_1_GPIO_A_SD (2 << (30-10)) -#define SICR_1_GPIO_A_DDR (3 << (30-10)) -#define SICR_1_GPIO_B_GPIO (0 << (30-12)) -#define SICR_1_GPIO_B_SD (2 << (30-12)) -#define SICR_1_GPIO_B_QE (3 << (30-12)) -#define SICR_1_GPIO_C_GPIO (0 << (30-14)) -#define SICR_1_GPIO_C_CAN (1 << (30-14)) -#define SICR_1_GPIO_C_DDR (2 << (30-14)) -#define SICR_1_GPIO_C_LCS (3 << (30-14)) -#define SICR_1_GPIO_D_GPIO (0 << (30-16)) -#define SICR_1_GPIO_D_CAN (1 << (30-16)) -#define SICR_1_GPIO_D_DDR (2 << (30-16)) -#define SICR_1_GPIO_D_LCS (3 << (30-16)) -#define SICR_1_GPIO_E_GPIO (0 << (30-18)) -#define SICR_1_GPIO_E_CAN (1 << (30-18)) -#define SICR_1_GPIO_E_DDR (2 << (30-18)) -#define SICR_1_GPIO_E_LCS (3 << (30-18)) -#define SICR_1_GPIO_F_GPIO (0 << (30-20)) -#define SICR_1_GPIO_F_CAN (1 << (30-20)) -#define SICR_1_GPIO_F_CK (2 << (30-20)) -#define SICR_1_USB_A_USBDR (0 << (30-22)) -#define SICR_1_USB_A_UART2S (1 << (30-22)) -#define SICR_1_USB_B_USBDR (0 << (30-24)) -#define SICR_1_USB_B_UART2S (1 << (30-24)) -#define SICR_1_USB_B_UART2RTS (2 << (30-24)) -#define SICR_1_USB_C_USBDR (0 << (30-26)) -#define SICR_1_USB_C_QE_EXT (3 << (30-26)) -#define SICR_1_FEC1_FEC1 (0 << (30-28)) -#define SICR_1_FEC1_GTM (1 << (30-28)) -#define SICR_1_FEC1_GPIO (2 << (30-28)) -#define SICR_1_FEC2_FEC2 (0 << (30-30)) -#define SICR_1_FEC2_GTM (1 << (30-30)) -#define SICR_1_FEC2_GPIO (2 << (30-30)) -/* SICR_2 */ -#define SICR_2_FEC3_FEC3 (0 << (30-0)) -#define SICR_2_FEC3_TMR (1 << (30-0)) -#define SICR_2_FEC3_GPIO (2 << (30-0)) -#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2)) -#define SICR_2_HDLC1_A_GPIO (1 << (30-2)) -#define SICR_2_HDLC1_A_TDM1 (2 << (30-2)) -#define SICR_2_ELBC_A_LA (0 << (30-4)) -#define SICR_2_ELBC_B_LCLK (0 << (30-6)) -#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8)) -#define SICR_2_HDLC2_A_GPIO (0 << (30-8)) -#define SICR_2_HDLC2_A_TDM2 (0 << (30-8)) -/* bits 10-11 unused */ -#define SICR_2_USB_D_USBDR (0 << (30-12)) -#define SICR_2_USB_D_GPIO (2 << (30-12)) -#define SICR_2_USB_D_QE_BRG (3 << (30-12)) -#define SICR_2_PCI_PCI (0 << (30-14)) -#define SICR_2_PCI_CPCI_HS (2 << (30-14)) -#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16)) -#define SICR_2_HDLC1_B_GPIO (1 << (30-16)) -#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16)) -#define SICR_2_HDLC1_B_TDM1 (3 << (30-16)) -#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18)) -#define SICR_2_HDLC1_C_GPIO (1 << (30-18)) -#define SICR_2_HDLC1_C_TDM1 (2 << (30-18)) -#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20)) -#define SICR_2_HDLC2_B_GPIO (1 << (30-20)) -#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20)) -#define SICR_2_HDLC2_B_TDM2 (3 << (30-20)) -#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22)) -#define SICR_2_HDLC2_C_GPIO (1 << (30-22)) -#define SICR_2_HDLC2_C_TDM2 (2 << (30-22)) -#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22)) -#define SICR_2_QUIESCE_B (0 << (30-24)) - #endif /* @@ -610,63 +531,6 @@ #define HRCWL_SVCOD_DIV_8 0x10000000 #define HRCWL_SVCOD_DIV_2 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 -#elif defined(CONFIG_ARCH_MPC8309) - -#define HRCWL_CEVCOD 0x000000C0 -#define HRCWL_CEVCOD_SHIFT 6 -/* - * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012 - * these are different than with 8360, 832x - */ -#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000 -#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040 -#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080 - -#define HRCWL_CEPDF 0x00000020 -#define HRCWL_CEPDF_SHIFT 5 -#define HRCWL_CE_PLL_DIV_1X1 0x00000000 -#define HRCWL_CE_PLL_DIV_2X1 0x00000020 - -#define HRCWL_CEPMF 0x0000001F -#define HRCWL_CEPMF_SHIFT 0 -#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 -#define HRCWL_CE_TO_PLL_1X2 0x00000002 -#define HRCWL_CE_TO_PLL_1X3 0x00000003 -#define HRCWL_CE_TO_PLL_1X4 0x00000004 -#define HRCWL_CE_TO_PLL_1X5 0x00000005 -#define HRCWL_CE_TO_PLL_1X6 0x00000006 -#define HRCWL_CE_TO_PLL_1X7 0x00000007 -#define HRCWL_CE_TO_PLL_1X8 0x00000008 -#define HRCWL_CE_TO_PLL_1X9 0x00000009 -#define HRCWL_CE_TO_PLL_1X10 0x0000000A -#define HRCWL_CE_TO_PLL_1X11 0x0000000B -#define HRCWL_CE_TO_PLL_1X12 0x0000000C -#define HRCWL_CE_TO_PLL_1X13 0x0000000D -#define HRCWL_CE_TO_PLL_1X14 0x0000000E -#define HRCWL_CE_TO_PLL_1X15 0x0000000F -#define HRCWL_CE_TO_PLL_1X16 0x00000010 -#define HRCWL_CE_TO_PLL_1X17 0x00000011 -#define HRCWL_CE_TO_PLL_1X18 0x00000012 -#define HRCWL_CE_TO_PLL_1X19 0x00000013 -#define HRCWL_CE_TO_PLL_1X20 0x00000014 -#define HRCWL_CE_TO_PLL_1X21 0x00000015 -#define HRCWL_CE_TO_PLL_1X22 0x00000016 -#define HRCWL_CE_TO_PLL_1X23 0x00000017 -#define HRCWL_CE_TO_PLL_1X24 0x00000018 -#define HRCWL_CE_TO_PLL_1X25 0x00000019 -#define HRCWL_CE_TO_PLL_1X26 0x0000001A -#define HRCWL_CE_TO_PLL_1X27 0x0000001B -#define HRCWL_CE_TO_PLL_1X28 0x0000001C -#define HRCWL_CE_TO_PLL_1X29 0x0000001D -#define HRCWL_CE_TO_PLL_1X30 0x0000001E -#define HRCWL_CE_TO_PLL_1X31 0x0000001F - -#define HRCWL_SVCOD 0x30000000 -#define HRCWL_SVCOD_SHIFT 28 -#define HRCWL_SVCOD_DIV_2 0x00000000 -#define HRCWL_SVCOD_DIV_4 0x10000000 -#define HRCWL_SVCOD_DIV_8 0x20000000 -#define HRCWL_SVCOD_DIV_1 0x30000000 #endif /* @@ -1027,21 +891,6 @@ #define SCCR_SATACM_1 0x00000055 #define SCCR_SATACM_2 0x000000aa #define SCCR_SATACM_3 0x000000ff -#elif defined(CONFIG_ARCH_MPC8309) -/* SCCR bits - MPC8309 specific */ -#define SCCR_SDHCCM 0x0c000000 -#define SCCR_SDHCCM_SHIFT 26 -#define SCCR_SDHCCM_0 0x00000000 -#define SCCR_SDHCCM_1 0x04000000 -#define SCCR_SDHCCM_2 0x08000000 -#define SCCR_SDHCCM_3 0x0c000000 - -#define SCCR_USBDRCM 0x00c00000 -#define SCCR_USBDRCM_SHIFT 22 -#define SCCR_USBDRCM_0 0x00000000 -#define SCCR_USBDRCM_1 0x00400000 -#define SCCR_USBDRCM_2 0x00800000 -#define SCCR_USBDRCM_3 0x00c00000 #endif #define SCCR_PCIEXP1CM 0x00300000 diff --git a/test/py/requirements.txt b/test/py/requirements.txt index 2d0fcc965c..ead92ed8b4 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -12,9 +12,9 @@ pluggy==0.13.0 py==1.10.0 pycryptodomex==3.9.8 pyelftools==0.27 -pygit2==0.28.2 +pygit2==1.9.2 pyparsing==2.4.2 -pytest==5.2.1 +pytest==6.2.5 python-mimeparse==1.6.0 python-subunit==1.3.0 requests==2.25.1 diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index bbdc6557c2..d3292e752a 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,7 +2,7 @@ # This Dockerfile is used to build an image containing basic stuff to be used # to build U-Boot and run our test suites. -FROM ubuntu:focal-20220302 +FROM ubuntu:jammy-20220801 MAINTAINER Tom Rini <trini@konsulko.com> LABEL Description=" This image is for building U-Boot inside a container" @@ -12,7 +12,7 @@ ENV DEBIAN_FRONTEND=noninteractive # Add LLVM repository RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/* RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - -RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-13 main | tee /etc/apt/sources.list.d/llvm.list +RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-13 main | tee /etc/apt/sources.list.d/llvm.list # Manually install the kernel.org "Crosstool" based toolchains for gcc-11.1.0 RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ @@ -117,16 +117,6 @@ RUN apt-get update && apt-get install -y \ # Make kernels readable for libguestfs tools to work correctly RUN chmod +r /boot/vmlinu* -# Manually install a new enough version of sbsigntools (must be v0.9.4 or later) -RUN git clone https://git.kernel.org/pub/scm/linux/kernel/git/jejb/sbsigntools.git /tmp/sbsigntools && \ - cd /tmp/sbsigntools && \ - git checkout -b latest v0.9.4 && \ - ./autogen.sh && \ - ./configure && \ - make && \ - make install && \ - rm -rf /tmp/sbsigntools - # Build GRUB UEFI targets for ARM & RISC-V, 32-bit and 64-bit RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ cd /tmp/grub && \ |