diff options
39 files changed, 751 insertions, 673 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 96b2ab4d75..06c46b681c 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -391,12 +391,12 @@ stages: grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi # the below corresponds to .gitlab-ci.yml "script" cd ${WORK_DIR} diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e6c6ab3586..cfd58513c3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -29,12 +29,12 @@ stages: - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi after_script: @@ -2152,7 +2152,7 @@ CHANGELOG: # Directories & files removed with 'make clean' CLEAN_DIRS += $(MODVERDIR) \ - $(foreach d, spl tpl, $(patsubst %,$d/%, \ + $(foreach d, spl tpl vpl, $(patsubst %,$d/%, \ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ @@ -2167,7 +2167,7 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ idbloader-spi.img lib/efi_loader/helloworld_efi.S # Directories & files removed with 'make mrproper' -MRPROPER_DIRS += include/config include/generated spl tpl \ +MRPROPER_DIRS += include/config include/generated spl tpl vpl \ .tmp_objdiff doc/output include/asm # Remove include/asm symlink created by U-Boot before v2014.01 diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..1d61eb8020 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb -dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts deleted file mode 100644 index c3f58e2d56..0000000000 --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021-2022 Microchip Technology Inc. - * Padmarao Begari <padmarao.begari@microchip.com> - */ - -/dts-v1/; - -#include "microchip-mpfs.dtsi" - -/* Clock frequency (in Hz) of the rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-reference-rtlv2210", - "microchip,mpfs-icicle-kit", "microchip,mpfs"; - - aliases { - serial1 = &uart1; - ethernet0 = &mac1; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial1"; - }; - - cpus { - timebase-frequency = <RTCCLK_FREQ>; - }; - - ddrc_cache_lo: memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - status = "okay"; - }; - - ddrc_cache_hi: memory@1040000000 { - device_type = "memory"; - reg = <0x10 0x40000000 0x0 0x40000000>; - status = "okay"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hss_payload: region@BFC00000 { - reg = <0x0 0xBFC00000 0x0 0x400000>; - no-map; - }; - }; -}; - -&refclk { - clock-frequency = <125000000>; -}; - -&uart1 { - status = "okay"; -}; - -&mmc { - status = "okay"; - - bus-width = <4>; - disable-wp; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - - pac193x: pac193x@10 { - compatible = "microchip,pac1934"; - reg = <0x10>; - samp-rate = <64>; - status = "okay"; - ch1: channel0 { - uohms-shunt-res = <10000>; - rail-name = "VDDREG"; - channel_enabled; - }; - ch2: channel1 { - uohms-shunt-res = <10000>; - rail-name = "VDDA25"; - channel_enabled; - }; - ch3: channel2 { - uohms-shunt-res = <10000>; - rail-name = "VDD25"; - channel_enabled; - }; - ch4: channel3 { - uohms-shunt-res = <10000>; - rail-name = "VDDA_REG"; - channel_enabled; - }; - }; -}; - -&mac1 { - status = "okay"; - phy-mode = "sgmii"; - phy-handle = <&phy1>; - phy1: ethernet-phy@9 { - reg = <9>; - ti,fifo-depth = <0x1>; - }; -}; - -&qspi { - status = "okay"; - num-cs = <1>; - - flash0: flash@0 { - compatible = "spi-nand"; - reg = <0x0>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-max-frequency = <20000000>; - spi-cpol; - spi-cpha; - }; -}; diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi new file mode 100644 index 0000000000..1069134f2e --- /dev/null +++ b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/ { + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; + + core_pwm0: pwm@40000000 { + compatible = "microchip,corepwm-rtl-v4"; + reg = <0x0 0x40000000 0x0 0xF0>; + microchip,sync-update-mask = /bits/ 32 <0>; + #pwm-cells = <3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; + status = "disabled"; + }; + + i2c2: i2c@40000200 { + compatible = "microchip,corei2c-rtl-v7"; + reg = <0x0 0x40000200 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; + interrupt-parent = <&plic>; + interrupts = <122>; + clock-frequency = <100000>; + status = "disabled"; + }; + + pcie: pcie@3000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; + clock-names = "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + refclk_ccc: cccrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi index f60283fb6b..f60283fb6b 100644 --- a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi +++ b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts new file mode 100644 index 0000000000..8aa5fb17d6 --- /dev/null +++ b/arch/riscv/dts/mpfs-icicle-kit.dts @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021-2022 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + model = "Microchip PolarFire-SoC Icicle Kit"; + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; + + aliases { + ethernet0 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + label = "led1"; + }; + + led-2 { + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + label = "led2"; + }; + + led-3 { + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_AMBER>; + label = "led3"; + }; + + led-4 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_AMBER>; + label = "led4"; + }; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1040000000 { + device_type = "memory"; + reg = <0x10 0x40000000 0x0 0x40000000>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss_payload: region@BFC00000 { + reg = <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&core_pwm0 { + status = "okay"; +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&mac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + status = "enabled"; +}; + +&mac1 { + phy-mode = "sgmii"; + phy-handle = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@9 { + reg = <9>; + }; + + phy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/riscv/dts/microchip-mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi index 891dd0918b..6012a28507 100644 --- a/arch/riscv/dts/microchip-mpfs.dtsi +++ b/arch/riscv/dts/mpfs.dtsi @@ -2,8 +2,6 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ #include "dt-bindings/clock/microchip-mpfs-clock.h" -#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h" -#include "dt-bindings/interrupt-controller/riscv-hart.h" / { #address-cells = <2>; @@ -11,9 +9,6 @@ model = "Microchip PolarFire SoC"; compatible = "microchip,mpfs"; - chosen { - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -28,12 +23,7 @@ riscv,isa = "rv64imac"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu0_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -59,13 +49,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -91,13 +77,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -123,13 +105,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -155,273 +133,322 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; }; - refclk: refclk { + refclk: mssrefclk { compatible = "fixed-clock"; #clock-cells = <0>; }; + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + mboxes = <&mbox 0>; + }; + soc { #address-cells = <2>; #size-cells = <2>; - compatible = "microchip,mpfs-soc", "simple-bus"; + compatible = "simple-bus"; ranges; - clint: clint@2000000 { - compatible = "sifive,clint0"; - reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = - <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER - &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER - &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER - &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER - &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>; - }; - - cachecontroller: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; + cctrllr: cache-controller@2010000 { + compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; reg = <0x0 0x2010000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_L2_METADATA_CORR - PLIC_INT_L2_METADATA_UNCORR - PLIC_INT_L2_DATA_CORR>; cache-block-size = <64>; cache-level = <2>; cache-sets = <1024>; cache-size = <2097152>; cache-unified; + interrupt-parent = <&plic>; + interrupts = <1>, <3>, <4>, <2>; }; - pdma: pdma@3000000 { - compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR - PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR - PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR - PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>; - #dma-cells = <1>; + clint: clint@2000000 { + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; }; plic: interrupt-controller@c000000 { - compatible = "sifive,plic-1.0.0"; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; + #address-cells = <0>; #interrupt-cells = <1>; - riscv,ndev = <186>; interrupt-controller; - interrupts-extended = <&cpu0_intc HART_INT_M_EXT - &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT - &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT - &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT - &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + riscv,ndev = <186>; + }; + + pdma: dma-controller@3000000 { + compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <5 6>, <7 8>, <9 10>, <11 12>; + dma-channels = <4>; + #dma-cells = <1>; }; clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - reg-names = "mss_sysreg"; clocks = <&refclk>; #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ - "i2c1", "can0", "can1", "usb", /* 16-19 */ - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ + #reset-cells = <1>; }; - /* Common node entry for eMMC/SD */ - mmc: mmc@20008000 { - compatible = "microchip,mpfs-sd4hc","cdns,sd4hc"; - reg = <0x0 0x20008000 0x0 0x1000>; - clocks = <&clkcfg CLK_MMC>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>; - max-frequency = <200000000>; + ccc_se: clock-controller@38010000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, + <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_ne: clock-controller@38040000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, + <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; + #clock-cells = <1>; status = "disabled"; }; - uart0: serial@20000000 { + ccc_nw: clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, + <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_sw: clock-controller@38400000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, + <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + mmuart0: serial@20000000 { compatible = "ns16550a"; reg = <0x0 0x20000000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART0>; + interrupts = <90>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART0>; status = "disabled"; /* Reserved for the HSS */ }; - uart1: serial@20100000 { + mmuart1: serial@20100000 { compatible = "ns16550a"; reg = <0x0 0x20100000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART1>; + interrupts = <91>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART1>; status = "disabled"; }; - uart2: serial@20102000 { + mmuart2: serial@20102000 { compatible = "ns16550a"; reg = <0x0 0x20102000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART2>; + interrupts = <92>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART2>; status = "disabled"; }; - uart3: serial@20104000 { + mmuart3: serial@20104000 { compatible = "ns16550a"; reg = <0x0 0x20104000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART3>; + interrupts = <93>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART3>; status = "disabled"; }; - uart4: serial@20106000 { + mmuart4: serial@20106000 { compatible = "ns16550a"; reg = <0x0 0x20106000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART4>; + interrupts = <94>; clocks = <&clkcfg CLK_MMUART4>; + current-speed = <115200>; + status = "disabled"; + }; + + /* Common node entry for emmc/sd */ + mmc: mmc@20008000 { + compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + clocks = <&clkcfg CLK_MMC>; + max-frequency = <200000000>; status = "disabled"; }; spi0: spi@20108000 { compatible = "microchip,mpfs-spi"; - reg = <0x0 0x20108000 0x0 0x1000>; - clocks = <&clkcfg CLK_SPI0>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_SPI0>; - num-cs = <8>; #address-cells = <1>; #size-cells = <0>; + reg = <0x0 0x20108000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <54>; + clocks = <&clkcfg CLK_SPI0>; status = "disabled"; }; spi1: spi@20109000 { compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0x0 0x20109000 0x0 0x1000>; - clocks = <&clkcfg CLK_SPI1>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_SPI1>; - num-cs = <8>; + interrupts = <55>; + clocks = <&clkcfg CLK_SPI1>; + status = "disabled"; + }; + + qspi: spi@21000000 { + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; #address-cells = <1>; #size-cells = <0>; + reg = <0x0 0x21000000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <85>; + clocks = <&clkcfg CLK_QSPI>; status = "disabled"; }; i2c0: i2c@2010a000 { - compatible = "microchip,mpfs-i2c"; + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; reg = <0x0 0x2010a000 0x0 0x1000>; - clocks = <&clkcfg CLK_I2C0>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_I2C0_MAIN>; #address-cells = <1>; #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + clock-frequency = <100000>; status = "disabled"; }; i2c1: i2c@2010b000 { - compatible = "microchip,mpfs-i2c"; + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; reg = <0x0 0x2010b000 0x0 0x1000>; - clocks = <&clkcfg CLK_I2C1>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_I2C1_MAIN>; #address-cells = <1>; #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + clock-frequency = <100000>; status = "disabled"; }; can0: can@2010c000 { - compatible = "microchip,mpfs-can-uio"; + compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; clocks = <&clkcfg CLK_CAN0>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_CAN0>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <56>; status = "disabled"; }; can1: can@2010d000 { - compatible = "microchip,mpfs-can-uio"; + compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; clocks = <&clkcfg CLK_CAN1>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_CAN1>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <57>; status = "disabled"; }; mac0: ethernet@20110000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MAC0_INT - PLIC_INT_MAC0_QUEUE1 - PLIC_INT_MAC0_QUEUE2 - PLIC_INT_MAC0_QUEUE3 - PLIC_INT_MAC0_EMAC - PLIC_INT_MAC0_MMSL>; + interrupts = <64>, <65>, <66>, <67>, <68>, <69>; local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC0>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; mac1: ethernet@20112000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MAC1_INT - PLIC_INT_MAC1_QUEUE1 - PLIC_INT_MAC1_QUEUE2 - PLIC_INT_MAC1_QUEUE3 - PLIC_INT_MAC1_EMAC - PLIC_INT_MAC1_MMSL>; + interrupts = <70>, <71>, <72>, <73>, <74>, <75>; local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC1>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; gpio0: gpio@20120000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20120000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO0>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO0>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -429,10 +456,11 @@ gpio1: gpio@20121000 { compatible = "microchip,mpfs-gpio"; - reg = <000 0x20121000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO1>; + reg = <0x0 0x20121000 0x0 0x1000>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -441,9 +469,10 @@ gpio2: gpio@20122000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20122000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO2>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -452,118 +481,31 @@ rtc: rtc@20124000 { compatible = "microchip,mpfs-rtc"; reg = <0x0 0x20124000 0x0 0x1000>; - clocks = <&clkcfg CLK_RTC>; - clock-names = "rtc"; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <80>, <81>; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; status = "disabled"; }; usb: usb@20201000 { - compatible = "microchip,mpfs-usb-host"; + compatible = "microchip,mpfs-musb"; reg = <0x0 0x20201000 0x0 0x1000>; - reg-names = "mc","control"; - clocks = <&clkcfg CLK_USB>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>; + interrupts = <86>, <87>; + clocks = <&clkcfg CLK_USB>; interrupt-names = "dma","mc"; - dr_mode = "host"; - status = "disabled"; - }; - - qspi: qspi@21000000 { - compatible = "microchip,mpfs-qspi"; - reg = <0x0 0x21000000 0x0 0x1000>; - clocks = <&clkcfg CLK_QSPI>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_QSPI>; - num-cs = <8>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_G5C_MESSAGE>; + interrupts = <96>; #mbox-cells = <1>; status = "disabled"; }; - - pcie: pcie@2000000000 { - compatible = "microchip,pcie-host-1.0"; - #address-cells = <0x3>; - #interrupt-cells = <0x1>; - #size-cells = <0x2>; - device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; - clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; - clock-names = "fic0", "fic1", "fic3"; - bus-range = <0x0 0x7f>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_FABRIC_F2H_2>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask = <0 0 0 7>; - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent = <&pcie>; - msi-controller; - mchp,axi-m-atr0 = <0x10 0x0>; - status = "disabled"; - pcie_intc: legacy-interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - syscontroller: syscontroller { - compatible = "microchip,mpfs-sys-controller"; - #address-cells = <1>; - #size-cells = <1>; - mboxes = <&mbox 0>; - }; - - hwrandom: hwrandom { - compatible = "microchip,mpfs-rng"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - serialnum: serialnum { - compatible = "microchip,mpfs-serial-number"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - fpgadigest: fpgadigest { - compatible = "microchip,mpfs-digest"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - devicecert: cert { - compatible = "microchip,mpfs-device-cert"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - signature: signature { - compatible = "microchip,mpfs-signature"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; }; }; diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h new file mode 100644 index 0000000000..f541fb4daa --- /dev/null +++ b/arch/riscv/include/asm/atomic.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2023 SiFive, Inc. + */ + +#ifndef __RISCV_ATOMIC_H +#define __RISCV_ATOMIC_H + +/* use the generic asm/atomic.h until we define a better one */ + +#include <asm/system.h> +#include <asm-generic/atomic.h> + +#endif diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index 536629bbec..35f1368b83 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -158,6 +158,9 @@ static inline unsigned long ffz(unsigned long word) #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) +#define test_and_set_bit __test_and_set_bit +#define test_and_clear_bit __test_and_clear_bit + #define ext2_set_bit test_and_set_bit #define ext2_clear_bit test_and_clear_bit #define ext2_test_bit test_bit diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 81fcfe0b36..769369997d 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -28,6 +28,9 @@ enum sbi_ext_id { SBI_EXT_HSM = 0x48534D, SBI_EXT_SRST = 0x53525354, SBI_EXT_PMU = 0x504D55, + SBI_EXT_DBCN = 0x4442434E, + SBI_EXT_SUSP = 0x53555350, + SBI_EXT_CPPC = 0x43505043, }; enum sbi_ext_base_fid { @@ -89,6 +92,12 @@ enum sbi_srst_reset_reason { SBI_SRST_RESET_REASON_SYS_FAILURE, }; +enum sbi_ext_dbcn_fid { + SBI_EXT_DBCN_CONSOLE_WRITE = 0, + SBI_EXT_DBCN_CONSOLE_READ, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE, +}; + #ifdef CONFIG_SBI_V01 #define SBI_EXT_SET_TIMER SBI_EXT_0_1_SET_TIMER #define SBI_FID_SET_TIMER 0 diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h index 9d8e43e394..ffa7649f3f 100644 --- a/arch/riscv/include/asm/system.h +++ b/arch/riscv/include/asm/system.h @@ -7,15 +7,24 @@ #ifndef __ASM_RISCV_SYSTEM_H #define __ASM_RISCV_SYSTEM_H +#include <asm/csr.h> + struct event; /* - * Interrupt configuring macros. - * - * TODO - * + * Interupt configuration macros */ +#define local_irq_save(__flags) \ + do { \ + __flags = csr_read_clear(CSR_SSTATUS, SR_SIE) & SR_SIE; \ + } while (0) + +#define local_irq_restore(__flags) \ + do { \ + csr_set(CSR_SSTATUS, __flags & SR_SIE); \ + } while (0) + /* Hook to set up the CPU (called from SPL too) */ int riscv_cpu_setup(void *ctx, struct event *event); diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 324eb445aa..7518408089 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -2,9 +2,10 @@ /* * Copyright (C) 2019, Rick Chen <rick@andestech.com> * - * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC). - * The PLIC block holds memory-mapped claim and pending registers - * associated with software interrupt. + * U-Boot syscon driver for Andes' PLICSW + * The PLICSW block is an Andes-specific design for software interrupts, + * contains memory-mapped priority, enable, claim and pending registers + * similar to RISC-V PLIC. */ #include <common.h> @@ -26,9 +27,13 @@ #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) +/* priority register */ +#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE) #define ENABLE_HART_IPI (0x01010101) #define SEND_IPI_TO_HART(hart) (0x1 << (hart)) +#define PLICSW_PRIORITY_BASE 0x4 +#define PLICSW_INTERRUPT_PER_HART 0x8 DECLARE_GLOBAL_DATA_PTR; @@ -43,9 +48,21 @@ static int enable_ipi(int hart) return 0; } +static void init_priority_ipi(int hart_num) +{ + uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw); + + for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) { + writel(1, &priority[i]); + } + + return; +} + int riscv_init_ipi(void) { int ret; + int hart_num = 0; long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW); ofnode node; struct udevice *dev; @@ -79,8 +96,10 @@ int riscv_init_ipi(void) ret = ofnode_read_u32(node, "reg", ®); if (ret == 0) enable_ipi(reg); + hart_num++; } + init_priority_ipi(hart_num); return 0; } diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index b6a88479b2..f810b4752f 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -18,4 +18,4 @@ PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) @: -clean-files := *.dtb +clean-files := *.dtb *.dtbo diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index e74c9fb03c..0f5f82924e 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -80,7 +80,7 @@ int board_late_init(void) char icicle_mac_addr[20]; void *blob = (void *)gd->fdt_blob; - node = fdt_path_offset(blob, "ethernet0"); + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); if (node < 0) { printf("No ethernet0 path offset\n"); return -ENODEV; @@ -88,7 +88,7 @@ int board_late_init(void) ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6); if (ret) { - printf("No local-mac-address property\n"); + printf("No local-mac-address property for ethernet@20112000\n"); return -EINVAL; } @@ -104,7 +104,7 @@ int board_late_init(void) ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); if (ret) { - printf("Error setting local-mac-address property\n"); + printf("Error setting local-mac-address property for ethernet@20112000\n"); return -ENODEV; } @@ -123,6 +123,15 @@ int board_late_init(void) mac_addr[5] = device_serial_number[0] + 1; + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + icicle_mac_addr[0] = '['; sprintf(&icicle_mac_addr[1], "%pM", mac_addr); diff --git a/cmd/Kconfig b/cmd/Kconfig index 02e54f1e50..c1941849f9 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1228,6 +1228,7 @@ config LOADS_ECHO config CMD_SAVES bool "saves - Save a file over serial in S-Record format" + depends on CMD_LOADS help Provides a way to save a binary file using the Motorola S-Record format over the serial line. diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 6f2cad4e7e..c4707fe520 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -46,6 +46,9 @@ static struct sbi_ext extensions[] = { { SBI_EXT_HSM, "Hart State Management Extension" }, { SBI_EXT_SRST, "System Reset Extension" }, { SBI_EXT_PMU, "Performance Monitoring Unit Extension" }, + { SBI_EXT_DBCN, "Debug Console Extension" }, + { SBI_EXT_SUSP, "System Suspend Extension" }, + { SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" }, }; static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/common/Kconfig b/common/Kconfig index bbabadb35e..42baca20a6 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -256,6 +256,7 @@ config SYS_CONSOLE_OVERWRITE_ROUTINE config SYS_CONSOLE_ENV_OVERWRITE bool "Update environment variables during console init" + depends on SYS_CONSOLE_IS_IN_ENV help The console environment variables (stdout, stdin, stderr) can be used to determine the correct console devices on start-up. This diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 865571d457..bee231b583 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1461,8 +1461,10 @@ config SPL_OPENSBI_SCRATCH_OPTIONS default 0x1 depends on SPL_OPENSBI help - Options passed to fw_dynamic, for example SBI_SCRATCH_NO_BOOT_PRINTS or - SBI_SCRATCH_DEBUG_PRINTS. + This bitmap of options is passed from U-Boot SPL to OpenSBI. + As of OpenSBI 1.3 the following bits are defined: + - SBI_SCRATCH_NO_BOOT_PRINTS = 0x1 (Disable prints during boot) + - SBI_SCRATCH_DEBUG_PRINTS = 0x2 (Enable runtime debug prints) config SPL_TARGET string "Addtional build targets for 'make'" diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl index 1874f9db4f..3d6cf1e59f 100644 --- a/common/spl/Kconfig.tpl +++ b/common/spl/Kconfig.tpl @@ -43,6 +43,7 @@ config TPL_FRAMEWORK config TPL_BANNER_PRINT bool "Enable output of the TPL banner 'U-Boot TPL ...'" + depends on DEBUG_UART && TPL_SERIAL default y help If this option is enabled, TPL will print the banner with version diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index faa22f9392..b3b69a642a 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -14,6 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 # CONFIG_GE_RTC is not set CONFIG_MX6QDL=y CONFIG_TARGET_GE_B1X5V2=y +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_SERIAL=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 6aa1d03e5b..589da3226d 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0xc0000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_SPL_SERIAL=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index c03c8ec6ec..fa49d3865f 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit" +CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MEM_TOP_HIDE=0x400000 CONFIG_SYS_LOAD_ADDR=0x80200000 diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 105b937efa..5f0746e4e2 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xf00000 CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500" CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SYS_CLK_FREQ=33000000 diff --git a/doc/board/microchip/mpfs_icicle.rst b/doc/board/microchip/mpfs_icicle.rst index 09c2c6a9c1..1464e536e9 100644 --- a/doc/board/microchip/mpfs_icicle.rst +++ b/doc/board/microchip/mpfs_icicle.rst @@ -134,7 +134,7 @@ Build OpenSBI .. code-block:: none make PLATFORM=generic FW_PAYLOAD_PATH=<u-boot-directory>/u-boot.bin - FW_FDT_PATH=<u-boot-directory>/arch/riscv/dts/microchip-mpfs-icicle-kit-.dtb + FW_FDT_PATH=<u-boot-directory>/arch/riscv/dts/mpfs-icicle-kit-.dtb 3. Output "fw_payload.bin" file available at "<opensbi-directory>/build/platform/generic/firmware/fw_payload.bin" @@ -277,14 +277,14 @@ load uImage (with initramfs). done Bytes transferred = 14482480 (dcfc30 hex) - RISC-V # tftpboot ${fdt_addr_r} microchip-mpfs-icicle-kit.dtb + RISC-V # tftpboot ${fdt_addr_r} mpfs-icicle-kit.dtb ethernet@20112000: PHY present at 9 ethernet@20112000: Starting autonegotiation... ethernet@20112000: Autonegotiation complete ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) Using ethernet@20112000 device TFTP from server 192.168.1.3; our IP address is 192.168.1.5 - Filename 'microchip-mpfs-icicle-kit.dtb'. + Filename 'mpfs-icicle-kit.dtb'. Load address: 0x82200000 Loading: # 2.5 MiB/s diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index 51348b1ddc..84859d92ab 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += sifive-prci.o - -obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o +obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o fu740-prci.o diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 02e6d9000e..7492b1f70d 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -185,7 +185,7 @@ static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll, PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1); PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv); PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv); - PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0); + PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1_mask, 0); PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON); if (set) { diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 03f7fdd597..bdbe2a9536 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -61,14 +61,14 @@ endif config POWEROFF_GPIO bool "Enable support for GPIO poweroff driver" - select DM_GPIO + depends on DM_GPIO help Support for system poweroff using a GPIO pin. This can be used for systems having a single GPIO to trigger a system poweroff. config SYSRESET_GPIO bool "Enable support for GPIO reset driver" - select DM_GPIO + depends on DM_GPIO help Reset support via GPIO pin connected reset logic. This is used for example on Microblaze where reset logic can be controlled via GPIO diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 66da5a8d6f..35e4b36a69 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -105,7 +105,7 @@ static int dwc3_generic_probe(struct udevice *dev, if (CONFIG_IS_ENABLED(DM_GPIO) && device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) { priv->ulpi_reset = devm_gpiod_get_optional(dev->parent, "reset", - GPIOD_ACTIVE_LOW); + GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); /* property is optional, don't return error! */ if (priv->ulpi_reset) { /* Toggle ulpi to reset the phy. */ diff --git a/dts/Makefile b/dts/Makefile index cb31113829..3437e54033 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -63,4 +63,6 @@ spl_dtbs: $(obj)/dt-$(SPL_NAME).dtb clean-files := dt.dtb.S # Let clean descend into dts directories -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts ../arch/riscv/dts +subdir- += ../arch/arc/dts ../arch/arm/dts ../arch/m68k/dts ../arch/microblaze/dts \ + ../arch/mips/dts ../arch/nios2/dts ../arch/powerpc/dts ../arch/riscv/dts \ + ../arch/sandbox/dts ../arch/sh/dts ../arch/x86/dts ../arch/xtensa/dts diff --git a/include/configs/ae350.h b/include/configs/ae350.h index b566ecf296..23e4801379 100644 --- a/include/configs/ae350.h +++ b/include/configs/ae350.h @@ -83,11 +83,15 @@ #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00080000\0" \ - "pxefile_addr_r=0x01f00000\0" \ - "scriptaddr=0x01f00000\0" \ - "fdt_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x02800000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x00600000\0" \ + "kernel_comp_addr_r=0x04600000\0" \ + "kernel_comp_size=0x04000000\0" \ + "pxefile_addr_r=0x08600000\0" \ + "scriptaddr=0x08700000\0" \ + "fdt_addr_r=0x08800000\0" \ + "ramdisk_addr_r=0x08900000\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h index c7ed0a8db7..79775a5134 100644 --- a/include/dt-bindings/clock/microchip-mpfs-clock.h +++ b/include/dt-bindings/clock/microchip-mpfs-clock.h @@ -1,7 +1,7 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2020 Microchip Technology Inc. - * Padmarao Begari <padmarao.begari@microchip.com> + * Daire McNamara,<daire.mcnamara@microchip.com> + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ @@ -45,4 +45,27 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +/* Clock Conditioning Circuitry Clock IDs */ + +#define CLK_CCC_PLL0 0 +#define CLK_CCC_PLL1 1 +#define CLK_CCC_DLL0 2 +#define CLK_CCC_DLL1 3 + +#define CLK_CCC_PLL0_OUT0 4 +#define CLK_CCC_PLL0_OUT1 5 +#define CLK_CCC_PLL0_OUT2 6 +#define CLK_CCC_PLL0_OUT3 7 + +#define CLK_CCC_PLL1_OUT0 8 +#define CLK_CCC_PLL1_OUT1 9 +#define CLK_CCC_PLL1_OUT2 10 +#define CLK_CCC_PLL1_OUT3 11 + +#define CLK_CCC_DLL0_OUT0 12 +#define CLK_CCC_DLL0_OUT1 13 + +#define CLK_CCC_DLL1_OUT0 14 +#define CLK_CCC_DLL1_OUT1 15 + #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h deleted file mode 100644 index eba1bac7df..0000000000 --- a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H - -#define PLIC_INT_INVALID 0 -#define PLIC_INT_L2_METADATA_CORR 1 -#define PLIC_INT_L2_METADATA_UNCORR 2 -#define PLIC_INT_L2_DATA_CORR 3 -#define PLIC_INT_L2_DATA_UNCORR 4 -#define PLIC_INT_DMA_CH0_DONE 5 -#define PLIC_INT_DMA_CH0_ERR 6 -#define PLIC_INT_DMA_CH1_DONE 7 -#define PLIC_INT_DMA_CH1_ERR 8 -#define PLIC_INT_DMA_CH2_DONE 9 -#define PLIC_INT_DMA_CH2_ERR 10 -#define PLIC_INT_DMA_CH3_DONE 11 -#define PLIC_INT_DMA_CH3_ERR 12 - -#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13 -#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14 -#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15 -#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16 -#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17 -#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18 -#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19 -#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20 -#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21 -#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22 -#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23 -#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24 -#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25 -#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26 -#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27 -#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28 -#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29 -#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30 -#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31 -#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32 -#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33 -#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34 -#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35 -#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36 -#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37 -#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38 -#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39 -#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40 -#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41 -#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42 -#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43 -#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44 -#define PLIC_INT_GPIO1_BIT18 45 -#define PLIC_INT_GPIO1_BIT19 46 -#define PLIC_INT_GPIO1_BIT20 47 -#define PLIC_INT_GPIO1_BIT21 48 -#define PLIC_INT_GPIO1_BIT22 49 -#define PLIC_INT_GPIO1_BIT23 50 -#define PLIC_INT_GPIO0_NON_DIRECT 51 -#define PLIC_INT_GPIO1_NON_DIRECT 52 -#define PLIC_INT_GPIO2_NON_DIRECT 53 -#define PLIC_INT_SPI0 54 -#define PLIC_INT_SPI1 55 -#define PLIC_INT_CAN0 56 -#define PLIC_INT_CAN1 57 -#define PLIC_INT_I2C0_MAIN 58 -#define PLIC_INT_I2C0_ALERT 59 -#define PLIC_INT_I2C0_SUS 60 -#define PLIC_INT_I2C1_MAIN 61 -#define PLIC_INT_I2C1_ALERT 62 -#define PLIC_INT_I2C1_SUS 63 -#define PLIC_INT_MAC0_INT 64 -#define PLIC_INT_MAC0_QUEUE1 65 -#define PLIC_INT_MAC0_QUEUE2 66 -#define PLIC_INT_MAC0_QUEUE3 67 -#define PLIC_INT_MAC0_EMAC 68 -#define PLIC_INT_MAC0_MMSL 69 -#define PLIC_INT_MAC1_INT 70 -#define PLIC_INT_MAC1_QUEUE1 71 -#define PLIC_INT_MAC1_QUEUE2 72 -#define PLIC_INT_MAC1_QUEUE3 73 -#define PLIC_INT_MAC1_EMAC 74 -#define PLIC_INT_MAC1_MMSL 75 -#define PLIC_INT_DDRC_TRAIN 76 -#define PLIC_INT_SCB_INTERRUPT 77 -#define PLIC_INT_ECC_ERROR 78 -#define PLIC_INT_ECC_CORRECT 79 -#define PLIC_INT_RTC_WAKEUP 80 -#define PLIC_INT_RTC_MATCH 81 -#define PLIC_INT_TIMER1 82 -#define PLIC_INT_TIMER2 83 -#define PLIC_INT_ENVM 84 -#define PLIC_INT_QSPI 85 -#define PLIC_INT_USB_DMA 86 -#define PLIC_INT_USB_MC 87 -#define PLIC_INT_MMC_MAIN 88 -#define PLIC_INT_MMC_WAKEUP 89 -#define PLIC_INT_MMUART0 90 -#define PLIC_INT_MMUART1 91 -#define PLIC_INT_MMUART2 92 -#define PLIC_INT_MMUART3 93 -#define PLIC_INT_MMUART4 94 -#define PLIC_INT_G5C_DEVRST 95 -#define PLIC_INT_G5C_MESSAGE 96 -#define PLIC_INT_USOC_VC_INTERRUPT 97 -#define PLIC_INT_USOC_SMB_INTERRUPT 98 -#define PLIC_INT_E51_0_MAINTENACE 99 -#define PLIC_INT_WDOG0_MRVP 100 -#define PLIC_INT_WDOG1_MRVP 101 -#define PLIC_INT_WDOG2_MRVP 102 -#define PLIC_INT_WDOG3_MRVP 103 -#define PLIC_INT_WDOG4_MRVP 104 -#define PLIC_INT_WDOG0_TOUT 105 -#define PLIC_INT_WDOG1_TOUT 106 -#define PLIC_INT_WDOG2_TOUT 107 -#define PLIC_INT_WDOG3_TOUT 108 -#define PLIC_INT_WDOG4_TOUT 109 -#define PLIC_INT_G5C_MSS_SPI 110 -#define PLIC_INT_VOLT_TEMP_ALARM 111 -#define PLIC_INT_ATHENA_COMPLETE 112 -#define PLIC_INT_ATHENA_ALARM 113 -#define PLIC_INT_ATHENA_BUS_ERROR 114 -#define PLIC_INT_USOC_AXIC_US 115 -#define PLIC_INT_USOC_AXIC_DS 116 -#define PLIC_INT_SPARE 117 -#define PLIC_INT_FABRIC_F2H_0 118 -#define PLIC_INT_FABRIC_F2H_1 119 -#define PLIC_INT_FABRIC_F2H_2 120 -#define PLIC_INT_FABRIC_F2H_3 121 -#define PLIC_INT_FABRIC_F2H_4 122 -#define PLIC_INT_FABRIC_F2H_5 123 -#define PLIC_INT_FABRIC_F2H_6 124 -#define PLIC_INT_FABRIC_F2H_7 125 -#define PLIC_INT_FABRIC_F2H_8 126 -#define PLIC_INT_FABRIC_F2H_9 127 -#define PLIC_INT_FABRIC_F2H_10 128 -#define PLIC_INT_FABRIC_F2H_11 129 -#define PLIC_INT_FABRIC_F2H_12 130 -#define PLIC_INT_FABRIC_F2H_13 131 -#define PLIC_INT_FABRIC_F2H_14 132 -#define PLIC_INT_FABRIC_F2H_15 133 -#define PLIC_INT_FABRIC_F2H_16 134 -#define PLIC_INT_FABRIC_F2H_17 135 -#define PLIC_INT_FABRIC_F2H_18 136 -#define PLIC_INT_FABRIC_F2H_19 137 -#define PLIC_INT_FABRIC_F2H_20 138 -#define PLIC_INT_FABRIC_F2H_21 139 -#define PLIC_INT_FABRIC_F2H_22 140 -#define PLIC_INT_FABRIC_F2H_23 141 -#define PLIC_INT_FABRIC_F2H_24 142 -#define PLIC_INT_FABRIC_F2H_25 143 -#define PLIC_INT_FABRIC_F2H_26 144 -#define PLIC_INT_FABRIC_F2H_27 145 -#define PLIC_INT_FABRIC_F2H_28 146 -#define PLIC_INT_FABRIC_F2H_29 147 -#define PLIC_INT_FABRIC_F2H_30 148 -#define PLIC_INT_FABRIC_F2H_31 149 -#define PLIC_INT_FABRIC_F2H_32 150 -#define PLIC_INT_FABRIC_F2H_33 151 -#define PLIC_INT_FABRIC_F2H_34 152 -#define PLIC_INT_FABRIC_F2H_35 153 -#define PLIC_INT_FABRIC_F2H_36 154 -#define PLIC_INT_FABRIC_F2H_37 155 -#define PLIC_INT_FABRIC_F2H_38 156 -#define PLIC_INT_FABRIC_F2H_39 157 -#define PLIC_INT_FABRIC_F2H_40 158 -#define PLIC_INT_FABRIC_F2H_41 159 -#define PLIC_INT_FABRIC_F2H_42 160 -#define PLIC_INT_FABRIC_F2H_43 161 -#define PLIC_INT_FABRIC_F2H_44 162 -#define PLIC_INT_FABRIC_F2H_45 163 -#define PLIC_INT_FABRIC_F2H_46 164 -#define PLIC_INT_FABRIC_F2H_47 165 -#define PLIC_INT_FABRIC_F2H_48 166 -#define PLIC_INT_FABRIC_F2H_49 167 -#define PLIC_INT_FABRIC_F2H_50 168 -#define PLIC_INT_FABRIC_F2H_51 169 -#define PLIC_INT_FABRIC_F2H_52 170 -#define PLIC_INT_FABRIC_F2H_53 171 -#define PLIC_INT_FABRIC_F2H_54 172 -#define PLIC_INT_FABRIC_F2H_55 173 -#define PLIC_INT_FABRIC_F2H_56 174 -#define PLIC_INT_FABRIC_F2H_57 175 -#define PLIC_INT_FABRIC_F2H_58 176 -#define PLIC_INT_FABRIC_F2H_59 177 -#define PLIC_INT_FABRIC_F2H_60 178 -#define PLIC_INT_FABRIC_F2H_61 179 -#define PLIC_INT_FABRIC_F2H_62 180 -#define PLIC_INT_FABRIC_F2H_63 181 -#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182 -#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183 -#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184 -#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185 -#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */ diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h deleted file mode 100644 index c4331b8521..0000000000 --- a/include/dt-bindings/interrupt-controller/riscv-hart.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H - -#define HART_INT_U_SOFT 0 -#define HART_INT_S_SOFT 1 -#define HART_INT_M_SOFT 3 -#define HART_INT_U_TIMER 4 -#define HART_INT_S_TIMER 5 -#define HART_INT_M_TIMER 7 -#define HART_INT_U_EXT 8 -#define HART_INT_S_EXT 9 -#define HART_INT_M_EXT 11 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */ diff --git a/test/py/tests/test_cleanup_build.py b/test/py/tests/test_cleanup_build.py new file mode 100644 index 0000000000..5206ff73ec --- /dev/null +++ b/test/py/tests/test_cleanup_build.py @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2023 Tobias Deiminger <tdmg@linutronix.de> + +"""Test for unexpected leftovers after make clean""" + +import itertools +import os +import pathlib +import shutil +import sys + +import pytest + +# pylint: disable=redefined-outer-name + + +@pytest.fixture +def tmp_copy_of_builddir(u_boot_config, tmp_path): + """For each test, provide a temporary copy of the initial build directory.""" + shutil.copytree( + u_boot_config.build_dir, + tmp_path, + symlinks=True, + dirs_exist_ok=True, + ) + return tmp_path + + +@pytest.fixture(scope="module") +def run_make(u_boot_log): + """Provide function to run and log make without connecting to u-boot console.""" + runner = u_boot_log.get_runner("make", sys.stdout) + + def _run_make(build_dir, target): + cmd = ["make", f"O={build_dir}", target] + runner.run(cmd) + + yield _run_make + runner.close() + + +@pytest.fixture(scope="module") +def most_generated_files(): + """Path.glob style patterns to describe what should be removed by 'make clean'.""" + return ( + "**/*.c", + "**/*.dtb", + "**/*.dtbo", + "**/*.o", + "**/*.py", + "**/*.pyc", + "**/*.so", + "**/*.srec", + "u-boot*", + "[svt]pl/u-boot*", + ) + + +@pytest.fixture(scope="module") +def all_generated_files(most_generated_files): + """Path.glob style patterns to describe what should be removed by 'make mrproper'.""" + return most_generated_files + (".config", "**/*.h") + + +def find_files(search_dir, include_patterns, exclude_dirs=None): + """Find files matching include_patterns, unless it's in one of exclude_dirs. + + include_patterns -- Path.glob style pattern relative to search dir + exclude_dir -- directories to exclude, expected relative to search dir + """ + matches = [] + exclude_dirs = [] if exclude_dirs is None else exclude_dirs + for abs_path in itertools.chain.from_iterable( + pathlib.Path(search_dir).glob(pattern) for pattern in include_patterns + ): + if abs_path.is_dir(): + continue + rel_path = pathlib.Path(os.path.relpath(abs_path, search_dir)) + if not any( + rel_path.is_relative_to(exclude_dir) for exclude_dir in exclude_dirs + ): + matches.append(rel_path) + return matches + + +def test_clean(run_make, tmp_copy_of_builddir, most_generated_files): + """Test if 'make clean' deletes most generated files.""" + run_make(tmp_copy_of_builddir, "clean") + leftovers = find_files( + tmp_copy_of_builddir, + most_generated_files, + exclude_dirs=["scripts", "test/overlay"], + ) + assert not leftovers, f"leftovers: {', '.join(map(str, leftovers))}" + + +def test_mrproper(run_make, tmp_copy_of_builddir, all_generated_files): + """Test if 'make mrproper' deletes current configuration and all generated files.""" + run_make(tmp_copy_of_builddir, "mrproper") + leftovers = find_files( + tmp_copy_of_builddir, + all_generated_files, + exclude_dirs=["test/overlay"], + ) + assert not leftovers, f"leftovers: {', '.join(map(str, leftovers))}" diff --git a/tools/.gitignore b/tools/.gitignore index cda3ea628c..941d38de21 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -34,6 +34,7 @@ /relocate-rela /spl_size_limit /sunxi-spl-image-builder +/tools/generated/**/*.c /update_octeon_header /version.h /xway-swap-bytes diff --git a/tools/Makefile b/tools/Makefile index a0cd87ff93..3d0c4b0dd6 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -48,20 +48,20 @@ hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo HOSTCFLAGS_bmp_logo.o := -pedantic hostprogs-$(BUILD_ENVCRC) += envcrc -envcrc-objs := envcrc.o lib/crc32.o env/embedded.o lib/sha1.o +envcrc-objs := envcrc.o generated/lib/crc32.o generated/env/embedded.o generated/lib/sha1.o hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr HOSTCFLAGS_gen_eth_addr.o := -pedantic hostprogs-$(CONFIG_CMD_NET) += gen_ethaddr_crc -gen_ethaddr_crc-objs := gen_ethaddr_crc.o lib/crc8.o +gen_ethaddr_crc-objs := gen_ethaddr_crc.o generated/lib/crc8.o HOSTCFLAGS_gen_ethaddr_crc.o := -pedantic hostprogs-$(CONFIG_CMD_LOADS) += img2srec HOSTCFLAGS_img2srec.o := -pedantic hostprogs-y += mkenvimage -mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o +mkenvimage-objs := mkenvimage.o os_support.o generated/lib/crc32.o hostprogs-y += dumpimage mkimage hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fit_info fit_check_sign @@ -71,30 +71,30 @@ ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_FWU_MDATA_GPT_BLK),) hostprogs-y += file2include endif -FIT_OBJS-y := fit_common.o fit_image.o image-host.o boot/image-fit.o -FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o boot/image-fit-sig.o -FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := boot/image-cipher.o +FIT_OBJS-y := fit_common.o fit_image.o image-host.o generated/boot/image-fit.o +FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o generated/boot/image-fit-sig.o +FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := generated/boot/image-cipher.o # The following files are synced with upstream DTC. # Use synced versions from scripts/dtc/libfdt/. LIBFDT_OBJS := $(addprefix libfdt/, fdt.o fdt_ro.o fdt_wip.o fdt_sw.o fdt_rw.o \ fdt_strerror.o fdt_empty_tree.o fdt_addresses.o fdt_overlay.o) -RSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/rsa/, \ +RSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/rsa/, \ rsa-sign.o rsa-verify.o \ rsa-mod-exp.o) -ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/ecdsa/, ecdsa-libcrypto.o) +ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/ecdsa/, ecdsa-libcrypto.o) -AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/aes/, \ +AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/aes/, \ aes-encrypt.o aes-decrypt.o) # Cryptographic helpers and image types that depend on openssl/libcrypto LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := \ - lib/fdt-libcrypto.o \ + generated/lib/fdt-libcrypto.o \ sunxi_toc0.o -ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o +ROCKCHIP_OBS = generated/lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o # common objs for dumpimage and mkimage dumpimage-mkimage-objs := aisimage.o \ @@ -102,20 +102,20 @@ dumpimage-mkimage-objs := aisimage.o \ $(FIT_OBJS-y) \ $(FIT_SIG_OBJS-y) \ $(FIT_CIPHER_OBJS-y) \ - boot/fdt_region.o \ - boot/bootm.o \ - lib/crc32.o \ + generated/boot/fdt_region.o \ + generated/boot/bootm.o \ + generated/lib/crc32.o \ default_image.o \ - lib/fdtdec_common.o \ - lib/fdtdec.o \ - boot/image.o \ - boot/image-host.o \ + generated/lib/fdtdec_common.o \ + generated/lib/fdtdec.o \ + generated/boot/image.o \ + generated/boot/image-host.o \ imagetool.o \ imximage.o \ imx8image.o \ imx8mimage.o \ kwbimage.o \ - lib/md5.o \ + generated/lib/md5.o \ lpc32xximage.o \ mxsimage.o \ omapimage.o \ @@ -128,12 +128,12 @@ dumpimage-mkimage-objs := aisimage.o \ $(ROCKCHIP_OBS) \ socfpgaimage.o \ sunxi_egon.o \ - lib/crc16-ccitt.o \ - lib/hash-checksum.o \ - lib/sha1.o \ - lib/sha256.o \ - lib/sha512.o \ - common/hash.o \ + generated/lib/crc16-ccitt.o \ + generated/lib/hash-checksum.o \ + generated/lib/sha1.o \ + generated/lib/sha256.o \ + generated/lib/sha512.o \ + generated/common/hash.o \ ublimage.o \ zynqimage.o \ zynqmpimage.o \ @@ -213,7 +213,7 @@ HOSTCFLAGS_mxsboot.o := -pedantic hostprogs-$(CONFIG_ARCH_SUNXI) += mksunxiboot hostprogs-$(CONFIG_ARCH_SUNXI) += sunxi-spl-image-builder -sunxi-spl-image-builder-objs := sunxi-spl-image-builder.o lib/bch.o +sunxi-spl-image-builder-objs := sunxi-spl-image-builder.o generated/lib/bch.o hostprogs-$(CONFIG_NETCONSOLE) += ncb @@ -221,16 +221,16 @@ hostprogs-$(CONFIG_ARCH_KIRKWOOD) += kwboot hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot hostprogs-y += proftool -proftool-objs = proftool.o lib/abuf.o +proftool-objs = proftool.o generated/lib/abuf.o hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela hostprogs-$(CONFIG_RISCV) += prelink-riscv hostprogs-$(CONFIG_ARCH_OCTEON) += update_octeon_header -update_octeon_header-objs := update_octeon_header.o lib/crc32.o +update_octeon_header-objs := update_octeon_header.o generated/lib/crc32.o hostprogs-y += fdtgrep -fdtgrep-objs += $(LIBFDT_OBJS) boot/fdt_region.o fdtgrep.o +fdtgrep-objs += $(LIBFDT_OBJS) generated/boot/fdt_region.o fdtgrep.o ifneq ($(TOOLS_ONLY),y) hostprogs-y += spl_size_limit @@ -251,7 +251,7 @@ HOSTLDLIBS_mkeficapsule += \ $(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid") hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule -mkfwumdata-objs := mkfwumdata.o lib/crc32.o +mkfwumdata-objs := mkfwumdata.o generated/lib/crc32.o HOSTLDLIBS_mkfwumdata += -luuid hostprogs-$(CONFIG_TOOLS_MKFWUMDATA) += mkfwumdata @@ -266,12 +266,12 @@ HOSTCFLAGS_sha256.o := -pedantic HOSTCFLAGS_sha512.o := -pedantic -DCONFIG_SHA512 -DCONFIG_SHA384 quiet_cmd_wrap = WRAP $@ -cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@ +cmd_wrap = echo "\#include <../$(patsubst $(obj)/generated/%,%,$@)>" >$@ -$(obj)/boot/%.c $(obj)/common/%.c $(obj)/env/%.c $(obj)/lib/%.c: +$(obj)/generated/%.c: $(call cmd,wrap) -clean-dirs := lib common +clean-dirs := generated always := $(hostprogs-y) diff --git a/tools/env/.gitignore b/tools/env/.gitignore index 8d28b2b70b..804abacc6e 100644 --- a/tools/env/.gitignore +++ b/tools/env/.gitignore @@ -1,3 +1,2 @@ -embedded.c fw_printenv fw_printenv_unstripped |