diff options
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager.c | 32 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 16 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/mailbox_s10.c | 17 |
4 files changed, 58 insertions, 11 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index be426a5cfb..9e645a4253 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -65,10 +65,38 @@ int set_cpu_clk_info(void) } #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +int cm_set_qspi_controller_clk_hz(u32 clk_hz) +{ + u32 reg; + u32 clk_khz; + + /* + * Store QSPI ref clock and set into sysmgr boot register. + * Only clock freq in kHz degree is accepted due to limited bits[27:0] + * is reserved for storing the QSPI clock freq into boot scratch cold0 + * register. + */ + if (clk_hz < 1000) + return -EINVAL; + + clk_khz = clk_hz / 1000; + printf("QSPI: Reference clock at %d kHz\n", clk_khz); + + reg = (readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) & + ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK); + + writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + + return 0; +} + unsigned int cm_get_qspi_controller_clk_hz(void) { - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + return (readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0) & + SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000; } #endif diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 9cf22375e3..2f9b471af3 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -13,6 +13,10 @@ void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void); unsigned int cm_get_qspi_controller_clk_hz(void); + +#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +int cm_set_qspi_controller_clk_hz(u32 clk_hz); +#endif #endif #if defined(CONFIG_TARGET_SOCFPGA_GEN5) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 1eb8e7a904..fc4e17821b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* store qspi ref clock */ +/* + * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 /* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 @@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0 + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 7dcdae8136..101af23855 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -5,14 +5,15 @@ */ #include <common.h> -#include <hang.h> -#include <wait_bit.h> -#include <asm/global_data.h> -#include <asm/io.h> +#include <asm/arch/clock_manager.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/system_manager.h> +#include <asm/global_data.h> +#include <asm/io.h> #include <asm/secure.h> #include <asm/system.h> +#include <hang.h> +#include <wait_bit.h> DECLARE_GLOBAL_DATA_PTR; @@ -384,10 +385,10 @@ int mbox_qspi_open(void) if (ret) goto error; - /* We are getting QSPI ref clock and set into sysmgr boot register */ - printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); - writel(resp_buf[0], - socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + /* Store QSPI controller ref clock frequency */ + ret = cm_set_qspi_controller_clk_hz(resp_buf[0]); + if (ret) + goto error; return 0; |