diff options
236 files changed, 3354 insertions, 454 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e3f3e5f0d8..2a281a9a0f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -182,6 +182,8 @@ F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c F: drivers/serial/serial_cortina.c F: drivers/mmc/ca_dw_mmc.c +F: drivers/i2c/i2c-cortina.c +F: drivers/i2c/i2c-cortina.h ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun <marek.behun@nic.cz> @@ -740,6 +742,8 @@ F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c F: drivers/serial/serial_cortina.c F: drivers/mmc/ca_dw_mmc.c +F: drivers/i2c/i2c-cortina.c +F: drivers/i2c/i2c-cortina.h MIPS MSCC M: Gregory CLEMENT <gregory.clement@bootlin.com> diff --git a/arch/arm/dts/armada-388-helios4-u-boot.dtsi b/arch/arm/dts/armada-388-helios4-u-boot.dtsi index f0da9f42de..0753889854 100644 --- a/arch/arm/dts/armada-388-helios4-u-boot.dtsi +++ b/arch/arm/dts/armada-388-helios4-u-boot.dtsi @@ -14,6 +14,9 @@ &spi1 { u-boot,dm-spl; + spi-flash@0 { + u-boot,dm-spl; + }; }; &w25q32 { @@ -21,6 +24,18 @@ u-boot,dm-spl; }; +&gpio0 { + u-boot,dm-spl; +}; + +&ahci0 { + u-boot,dm-spl; +}; + +&ahci1 { + u-boot,dm-spl; +}; + &sdhci { u-boot,dm-spl; }; diff --git a/arch/arm/dts/armada-388-helios4.dts b/arch/arm/dts/armada-388-helios4.dts index a154e0f4f4..fb49df2a3b 100644 --- a/arch/arm/dts/armada-388-helios4.dts +++ b/arch/arm/dts/armada-388-helios4.dts @@ -140,11 +140,6 @@ soc { internal-regs { i2c@11000 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - /* * PCA9655 GPIO expander, up to 1MHz clock. * 0-Board Revision bit 0 # @@ -187,8 +182,7 @@ gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; input; - line-name = - "usb-overcurrent-status"; + line-name = "usb-overcurrent-status"; }; }; @@ -248,7 +242,7 @@ bus-width = <4>; cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; no-1-8-v; - pinctrl-0 = <µsom_sdhci_pins + pinctrl-0 = <&helios_sdhci_pins &helios_sdhci_cd_pins>; pinctrl-names = "default"; status = "okay"; @@ -286,6 +280,12 @@ marvell,pins = "mpp20"; marvell,function = "gpio"; }; + helios_sdhci_pins: helios-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; helios_led_pins: helios-led-pins { marvell,pins = "mpp24", "mpp25", "mpp49", "mpp50", diff --git a/arch/arm/dts/kirkwood-d2net-u-boot.dtsi b/arch/arm/dts/kirkwood-d2net-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-d2net-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-is2-u-boot.dtsi b/arch/arm/dts/kirkwood-is2-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-is2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-net2big-u-boot.dtsi b/arch/arm/dts/kirkwood-net2big-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-net2big-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-ns2-u-boot.dtsi b/arch/arm/dts/kirkwood-ns2-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-ns2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi b/arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-ns2max-u-boot.dtsi b/arch/arm/dts/kirkwood-ns2max-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-ns2max-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi b/arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi new file mode 100644 index 0000000000..1f3b185479 --- /dev/null +++ b/arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h new file mode 100644 index 0000000000..9ac16f599e --- /dev/null +++ b/arch/arm/include/asm/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARM_MMU_H +#define __ASM_ARM_MMU_H + +void init_addr_map(void); + +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index b8c1b4ea74..37c1bfd726 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -207,7 +207,7 @@ int __asm_invalidate_l3_icache(void); void __asm_switch_ttbr(u64 new_ttbr); /* - * Switch from EL3 to EL2 for ARMv8 + * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8 * * @args: For loading 64-bit OS, fdt address. * For loading 32-bit OS, zero. @@ -222,7 +222,7 @@ void __asm_switch_ttbr(u64 new_ttbr); void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, u64 arg4, u64 entry_point, u64 es_flag); /* - * Switch from EL2 to EL1 for ARMv8 + * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8 * * @args: For loading 64-bit OS, fdt address. * For loading 32-bit OS, zero. @@ -248,11 +248,12 @@ void flush_l3_cache(void); void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); /* - *Issue a secure monitor call in accordance with ARM "SMC Calling convention", + * smc_call() - issue a secure monitor call + * + * Issue a secure monitor call in accordance with ARM "SMC Calling convention", * DEN0028A * * @args: input and output arguments - * */ void smc_call(struct pt_regs *args); @@ -521,10 +522,12 @@ enum { #endif /** + * mmu_page_table_flush() - register an update to page tables + * * Register an update to the page tables, and flush the TLB * - * \param start start address of update in page table - * \param stop stop address of update in page table + * @start: start address of update in page table + * @stop: stop address of update in page table */ void mmu_page_table_flush(unsigned long start, unsigned long stop); @@ -585,11 +588,26 @@ s32 psci_features(u32 function_id, u32 psci_fid); void save_boot_params_ret(void); /** + * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping + * + * Change the virt/phys mapping and cache settings for a region. + * + * @virt: virtual start address of memory region to change + * @phys: physical address for the memory region to set + * @size: size of memory region to change + * @option: dcache option to select + */ +void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, + size_t size, enum dcache_option option); + +/** + * mmu_set_region_dcache_behaviour() - set cache settings + * * Change the cache settings for a region. * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select + * @start: start address of memory region to change + * @size: size of memory region to change + * @option: dcache option to select */ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 1da2e92fe2..39717610d4 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -25,7 +25,8 @@ __weak void arm_init_domains(void) { } -void set_section_dcache(int section, enum dcache_option option) +static void set_section_phys(int section, phys_addr_t phys, + enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option) #endif /* Add the page offset */ - value |= ((u32)section << MMU_SECTION_SHIFT); + value |= phys; /* Add caching bits */ value |= option; @@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } +void set_section_dcache(int section, enum dcache_option option) +{ + set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option); +} + __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) { debug("%s: Warning: not implemented\n", __func__); } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) +void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, + size_t size, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, option); #endif - for (upto = start; upto < end; upto++) - set_section_dcache(upto, option); + for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE) + set_section_phys(upto, phys, option); /* * Make sure range is cache line aligned @@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, mmu_page_table_flush(startpt, stoppt); } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + mmu_set_region_dcache_behaviour_phys(start, start, size, option); +} + __weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index e6eb904e7f..b3287ce8bc 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae39852f..4ccaf69693 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -8,4 +8,12 @@ extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#include <addr_map.h> +#define phys_to_virt addrmap_phys_to_virt +#define virt_to_phys addrmap_virt_to_phys +#endif +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index cf4c5b245d..f2a5411623 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -146,6 +146,27 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE +#ifdef CONFIG_TARGET_RPI_4_32B +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL +#include <addr_map.h> +#include <asm/system.h> + +void init_addr_map(void) +{ + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + DCACHE_OFF); + + /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */ + addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0); + /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */ + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1); +} +#endif + void enable_caches(void) { dcache_enable(); diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 67a00cf1cf..2454730e6d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -533,7 +533,7 @@ struct op_params pex_and_usb3_tx_config_params3[] = { struct op_params pex_by4_config_params[] = { /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */ {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0}, - /* Lane Alignement enable */ + /* Lane Alignment enable */ {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0}, /* Max PLL phy config */ {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000}, @@ -672,12 +672,29 @@ struct op_params usb2_power_up_params[] = { {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, /* Phy0 register 3 - TX Channel control 0 */ {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0}, - /* check PLLCAL_DONE is set and IMPCAL_DONE is set */ + /* Decrease the amplitude of the low speed eye to meet the spec */ + {0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, + /* Change the High speed impedance threshold */ + {0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */ + {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + {0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, + /* Check PLLCAL_DONE is set and IMPCAL_DONE is set */ {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000}, - /* check REG_SQCAL_DONE is set */ + /* Check REG_SQCAL_DONE is set */ {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, - /* check PLL_READY is set */ - {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000} + /* Check PLL_READY is set */ + {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}, + /* Start calibrate of high seed impedance */ + {0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0}, + {0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0}, + /* De-assert the calibration signal */ + {0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0}, }; /* diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 0722e4a891..cbf0120adc 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -147,7 +147,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, /* Try bootm for legacy and FIT format image */ if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID) do_bootm(cmdtp, 0, 4, bootm_argv); - else if CONFIG_IS_ENABLED(CMD_BOOTZ) + else if (CONFIG_IS_ENABLED(CMD_BOOTZ)) do_bootz(cmdtp, 0, 4, bootm_argv); } diff --git a/arch/sandbox/include/asm/rtc.h b/arch/sandbox/include/asm/rtc.h index 1fbfea7999..5bb032f59f 100644 --- a/arch/sandbox/include/asm/rtc.h +++ b/arch/sandbox/include/asm/rtc.h @@ -21,6 +21,11 @@ enum { REG_RESET = 0x20, + REG_AUX0 = 0x30, + REG_AUX1, + REG_AUX2, + REG_AUX3, + REG_COUNT = 0x80, }; diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 11621256ae..3aa2a55676 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,6 +3,7 @@ # Copyright 2019 Google LLC obj-$(CONFIG_SPL_BUILD) += cpu_spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o obj-y += cpu_common.o @@ -11,7 +12,6 @@ obj-y += cpu.o obj-y += punit.o obj-y += fsp_bindings.o ifdef CONFIG_SPL_BUILD -obj-y += spl.o obj-y += fsp_m.o endif endif diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 435e50edad..d27324cb4e 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -363,6 +363,11 @@ static void setup_cpu_features(void) : : "i" (em_rst), "i" (mp_ne_set) : "eax"); } +void cpu_reinit_fpu(void) +{ + asm ("fninit\n"); +} + static void setup_identity(void) { /* identify CPU via cpuid and store the decoded info into gd->arch */ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 3e5d56d075..bd3f44014c 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -43,6 +43,14 @@ int x86_cpu_reinit_f(void); */ int x86_cpu_init_tpl(void); +/** + * cpu_reinit_fpu() - Reinit the FPU if something is wrong with it + * + * The FSP-M code can leave registers in use in the FPU. This functions reinits + * it so that the FPU can be used safely + */ +void cpu_reinit_fpu(void); + int cpu_init_f(void); void setup_gdt(struct global_data *id, u64 *gdt_addr); /* diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 6e23f3c95f..e8c1e07af1 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -117,6 +117,16 @@ err: return ret; } +static int fsp_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + + /* Set the maximum supported resolution */ + plat->size = 2560 * 1600 * 4; + + return 0; +} + static const struct udevice_id fsp_video_ids[] = { { .compatible = "fsp-fb" }, { } @@ -126,7 +136,9 @@ U_BOOT_DRIVER(fsp_video) = { .name = "fsp_video", .id = UCLASS_VIDEO, .of_match = fsp_video_ids, + .bind = fsp_video_bind, .probe = fsp_video_probe, + .flags = DM_FLAG_PRE_RELOC, }; static struct pci_device_id fsp_video_supported[] = { diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c index 1a758147b0..faf9c29aef 100644 --- a/arch/x86/lib/fsp2/fsp_meminit.c +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -85,6 +85,7 @@ int fsp_memory_init(bool s3wake, bool use_spi_flash) func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init); ret = func(&upd, &hob); bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M); + cpu_reinit_fpu(); if (ret) return log_msg_ret("SDRAM init fail\n", ret); diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS index 8fec70315f..7046e1b2c5 100644 --- a/board/LaCie/net2big_v2/MAINTAINERS +++ b/board/LaCie/net2big_v2/MAINTAINERS @@ -1,6 +1,12 @@ NET2BIG_V2 BOARD M: Simon Guinot <simon.guinot@sequanux.org> S: Maintained +F: arch/arm/dts/kirkwood-d2net.dts +F: arch/arm/dts/kirkwood-d2net-u-boot.dtsi +F: arch/arm/dts/kirkwood-d2net.dtsi +F: arch/arm/dts/kirkwood-net2big.dts +F: arch/arm/dts/kirkwood-net2big-u-boot.dtsi +F: arch/arm/dts/kirkwood-netxbig.dtsi F: board/LaCie/net2big_v2/ F: include/configs/lacie_kw.h F: configs/d2net_v2_defconfig diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index dbd8b5755d..e94c9a6dce 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -239,7 +239,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0", 8); + mv_phy_88e1116_init("ethernet-controller@72000", 8); } #endif diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS index 55fd50d4eb..1cc4f7108b 100644 --- a/board/LaCie/netspace_v2/MAINTAINERS +++ b/board/LaCie/netspace_v2/MAINTAINERS @@ -1,14 +1,21 @@ -NETSPACE_V2 BOARD +NETSPACE_V2 BOARDS M: Simon Guinot <simon.guinot@sequanux.org> S: Maintained +F: arch/arm/dts/kirkwood-is2.dts +F: arch/arm/dts/kirkwood-is2-u-boot.dtsi +F: arch/arm/dts/kirkwood-ns2-common.dtsi +F: arch/arm/dts/kirkwood-ns2.dts +F: arch/arm/dts/kirkwood-ns2lite.dts +F: arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi +F: arch/arm/dts/kirkwood-ns2max.dts +F: arch/arm/dts/kirkwood-ns2max-u-boot.dtsi +F: arch/arm/dts/kirkwood-ns2mini.dts +F: arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi +F: arch/arm/dts/kirkwood-ns2-u-boot.dtsi F: board/LaCie/netspace_v2/ F: include/configs/lacie_kw.h F: configs/inetspace_v2_defconfig -F: configs/netspace_max_v2_defconfig -F: configs/netspace_v2_defconfig - -NETSPACE_LITE_V2 BOARD -#M: - -S: Maintained F: configs/netspace_lite_v2_defconfig +F: configs/netspace_max_v2_defconfig F: configs/netspace_mini_v2_defconfig +F: configs/netspace_v2_defconfig diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 011cc563d1..33246b2015 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -100,9 +100,9 @@ int misc_init_r(void) void reset_phy(void) { #if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) - mv_phy_88e1318_init("egiga0", 0); + mv_phy_88e1318_init("ethernet-controller@72000", 0); #else - mv_phy_88e1116_init("egiga0", 8); + mv_phy_88e1116_init("ethernet-controller@72000", 8); #endif } #endif diff --git a/cmd/Kconfig b/cmd/Kconfig index 2b823dd260..846c905c9c 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1739,6 +1739,12 @@ config CMD_DATE Enable the 'date' command for getting/setting the time/date in RTC devices. +config CMD_RTC + bool "rtc" + depends on DM_RTC + help + Enable the 'rtc' command for low-level access to RTC devices. + config CMD_TIME bool "time" help diff --git a/cmd/Makefile b/cmd/Makefile index 7008dd42dc..dc412d1106 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -122,6 +122,7 @@ obj-$(CONFIG_CMD_REISER) += reiser.o obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o obj-$(CONFIG_CMD_RNG) += rng.o obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o +obj-$(CONFIG_CMD_RTC) += rtc.o obj-$(CONFIG_SANDBOX) += host.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_CMD_NVME) += nvme.o diff --git a/cmd/rtc.c b/cmd/rtc.c new file mode 100644 index 0000000000..b4f61b2e83 --- /dev/null +++ b/cmd/rtc.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <command.h> +#include <dm.h> +#include <hexdump.h> +#include <i2c.h> +#include <mapmem.h> +#include <rtc.h> + +#define MAX_RTC_BYTES 32 + +static int do_rtc_read(struct udevice *dev, int argc, char * const argv[]) +{ + u8 buf[MAX_RTC_BYTES]; + int reg, len, ret, r; + + if (argc < 2 || argc > 3) + return CMD_RET_USAGE; + + reg = simple_strtoul(argv[0], NULL, 16); + len = simple_strtoul(argv[1], NULL, 16); + + if (argc == 3) { + u8 *addr; + + addr = map_sysmem(simple_strtoul(argv[2], NULL, 16), len); + ret = dm_rtc_read(dev, reg, addr, len); + unmap_sysmem(addr); + if (ret) { + printf("dm_rtc_read() failed: %d\n", ret); + return CMD_RET_FAILURE; + } + return CMD_RET_SUCCESS; + } + + while (len) { + r = min_t(int, len, sizeof(buf)); + ret = dm_rtc_read(dev, reg, buf, r); + if (ret) { + printf("dm_rtc_read() failed: %d\n", ret); + return CMD_RET_FAILURE; + } + print_buffer(reg, buf, 1, r, 0); + len -= r; + reg += r; + } + + return CMD_RET_SUCCESS; +} + +static int do_rtc_write(struct udevice *dev, int argc, char * const argv[]) +{ + u8 buf[MAX_RTC_BYTES]; + int reg, len, ret; + const char *s; + int slen; + + if (argc < 2 || argc > 3) + return CMD_RET_USAGE; + + reg = simple_strtoul(argv[0], NULL, 16); + + if (argc == 3) { + u8 *addr; + + len = simple_strtoul(argv[1], NULL, 16); + addr = map_sysmem(simple_strtoul(argv[2], NULL, 16), len); + ret = dm_rtc_write(dev, reg, addr, len); + unmap_sysmem(addr); + if (ret) { + printf("dm_rtc_write() failed: %d\n", ret); + return CMD_RET_FAILURE; + } + return CMD_RET_SUCCESS; + } + + s = argv[1]; + slen = strlen(s); + + if (slen % 2) { + printf("invalid hex string\n"); + return CMD_RET_FAILURE; + } + + while (slen) { + len = min_t(int, slen / 2, sizeof(buf)); + if (hex2bin(buf, s, len)) { + printf("invalid hex string\n"); + return CMD_RET_FAILURE; + } + + ret = dm_rtc_write(dev, reg, buf, len); + if (ret) { + printf("dm_rtc_write() failed: %d\n", ret); + return CMD_RET_FAILURE; + } + s += 2 * len; + slen -= 2 * len; + } + + return CMD_RET_SUCCESS; +} + +int do_rtc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + static int curr_rtc; + struct udevice *dev; + int ret, idx; + + if (argc < 2) + return CMD_RET_USAGE; + + argc--; + argv++; + + if (!strcmp(argv[0], "list")) { + struct uclass *uc; + + idx = 0; + uclass_id_foreach_dev(UCLASS_RTC, dev, uc) { + printf("RTC #%d - %s\n", idx++, dev->name); + } + if (!idx) { + printf("*** no RTC devices available ***\n"); + return CMD_RET_FAILURE; + } + return CMD_RET_SUCCESS; + } + + idx = curr_rtc; + if (!strcmp(argv[0], "dev") && argc >= 2) + idx = simple_strtoul(argv[1], NULL, 10); + + ret = uclass_get_device(UCLASS_RTC, idx, &dev); + if (ret) { + printf("Cannot find RTC #%d: err=%d\n", idx, ret); + return CMD_RET_FAILURE; + } + + if (!strcmp(argv[0], "dev")) { + /* Show the existing or newly selected RTC */ + if (argc >= 2) + curr_rtc = idx; + printf("RTC #%d - %s\n", idx, dev->name); + return CMD_RET_SUCCESS; + } + + if (!strcmp(argv[0], "read")) + return do_rtc_read(dev, argc - 1, argv + 1); + + if (!strcmp(argv[0], "write")) + return do_rtc_write(dev, argc - 1, argv + 1); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + rtc, 5, 0, do_rtc, + "RTC subsystem", + "list - show available rtc devices\n" + "rtc dev [n] - show or set current rtc device\n" + "rtc read <reg> <count> - read and display 8-bit registers starting at <reg>\n" + "rtc read <reg> <count> <addr> - read 8-bit registers starting at <reg> to memory <addr>\n" + "rtc write <reg> <hexstring> - write 8-bit registers starting at <reg>\n" + "rtc write <reg> <count> <addr> - write from memory <addr> to 8-bit registers starting at <reg>\n" +); diff --git a/common/console.c b/common/console.c index 7b9816979a..07c483f820 100644 --- a/common/console.c +++ b/common/console.c @@ -229,18 +229,34 @@ static void console_putc(int file, const char c) } } -static void console_puts_noserial(int file, const char *s) +/** + * console_puts_select() - Output a string to all console devices + * + * @file: File number to output to (e,g, stdout, see stdio.h) + * @serial_only: true to output only to serial, false to output to everything + * else + * @s: String to output + */ +static void console_puts_select(int file, bool serial_only, const char *s) { int i; struct stdio_dev *dev; for (i = 0; i < cd_count[file]; i++) { + bool is_serial; + dev = console_devices[file][i]; - if (dev->puts != NULL && !console_dev_is_serial(dev)) + is_serial = console_dev_is_serial(dev); + if (dev->puts && serial_only == is_serial) dev->puts(dev, s); } } +void console_puts_select_stderr(bool serial_only, const char *s) +{ + console_puts_select(stderr, serial_only, s); +} + static void console_puts(int file, const char *s) { int i; @@ -275,9 +291,9 @@ static inline void console_putc(int file, const char c) stdio_devices[file]->putc(stdio_devices[file], c); } -static inline void console_puts_noserial(int file, const char *s) +void console_puts_select(int file, bool serial_only, const char *s) { - if (!console_dev_is_serial(stdio_devices[file])) + if (serial_only == console_dev_is_serial(stdio_devices[file])) stdio_devices[file]->puts(stdio_devices[file], s); } @@ -489,7 +505,7 @@ static void print_pre_console_buffer(int flushpoint) puts(buf_out); break; case PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL: - console_puts_noserial(stdout, buf_out); + console_puts_select(stdout, false, buf_out); break; } } @@ -776,7 +792,7 @@ int console_announce_r(void) display_options_get_banner(false, buf, sizeof(buf)); - console_puts_noserial(stdout, buf); + console_puts_select(stdout, false, buf); #endif return 0; diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig index 19fc741eb7..d7798ef3aa 100644 --- a/configs/Cyrus_P5020_defconfig +++ b/configs/Cyrus_P5020_defconfig @@ -42,4 +42,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig index 9c6919f387..39191debdf 100644 --- a/configs/Cyrus_P5040_defconfig +++ b/configs/Cyrus_P5040_defconfig @@ -42,4 +42,6 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 010e375740..6884754cac 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -46,3 +46,4 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y +CONFIG_ADDR_MAP=y diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig index 50912bf245..4053cb70f8 100644 --- a/configs/MPC8572DS_36BIT_defconfig +++ b/configs/MPC8572DS_36BIT_defconfig @@ -51,4 +51,5 @@ CONFIG_USB=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig index 1e643673ec..c75e665ad9 100644 --- a/configs/MPC8641HPCN_36BIT_defconfig +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -42,4 +42,6 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_KEYBOARD=y CONFIG_VIDEO=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=8 CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig index 7ce7891d14..b60813d048 100644 --- a/configs/MPC8641HPCN_defconfig +++ b/configs/MPC8641HPCN_defconfig @@ -42,4 +42,6 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_KEYBOARD=y CONFIG_VIDEO=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=8 CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig index c1044520d7..c4066672d5 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig @@ -57,6 +57,7 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 86c90dac27..a5ffbda7e4 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -83,3 +83,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig index 723f6ca2bb..c3cfaf1a73 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e6edd395e7..5a2dcaeea2 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -65,3 +65,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 2850e305f0..c8c7bedf5a 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -77,3 +77,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig index 9987cde995..8a13e3a622 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig @@ -58,6 +58,7 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 98ad4b6109..2aa476ca69 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -79,3 +79,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig index 66bdebbf99..1f2e969cce 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig @@ -57,6 +57,7 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index bd779aacf6..25fb606ef4 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -83,3 +83,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig index f2e40668ea..bbaec2beee 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index e85af32e2c..58f4430e80 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -65,3 +65,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 8559ffe3f3..137f613158 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -77,3 +77,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig index 50b5c5f1c5..63ac2f2b17 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig @@ -58,6 +58,7 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index fe503c1a6b..493597ee01 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -79,3 +79,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig index a9befd2e3f..1178c27599 100644 --- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig @@ -64,4 +64,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig index 7930af3b73..2385da49f6 100644 --- a/configs/P1020MBG-PC_36BIT_defconfig +++ b/configs/P1020MBG-PC_36BIT_defconfig @@ -52,4 +52,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index c148f4d592..00f9fb58a0 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -83,3 +83,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 7b40858de7..7ffac2e1f4 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -78,3 +78,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 7a7ae29bd7..b8e5e333c6 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -80,3 +80,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index f9a4b735ca..850a1525f4 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -67,3 +67,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig index a24f14a97f..36bb136c1b 100644 --- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig @@ -64,4 +64,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig index 968d3edbcf..47232d95e1 100644 --- a/configs/P1020UTM-PC_36BIT_defconfig +++ b/configs/P1020UTM-PC_36BIT_defconfig @@ -52,4 +52,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig index 353f4677f2..873243825e 100644 --- a/configs/P1021RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig @@ -81,4 +81,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig index 62cbbc016a..66c37f9407 100644 --- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig @@ -76,4 +76,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig index 7f71b52477..eaf45a6f3e 100644 --- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig @@ -78,4 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig index ca1be9c112..608a6d10b1 100644 --- a/configs/P1021RDB-PC_36BIT_defconfig +++ b/configs/P1021RDB-PC_36BIT_defconfig @@ -64,4 +64,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig index 5116fac64a..bb016af45e 100644 --- a/configs/P1024RDB_36BIT_defconfig +++ b/configs/P1024RDB_36BIT_defconfig @@ -58,4 +58,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig index 8eaddb1290..c096593c18 100644 --- a/configs/P1025RDB_36BIT_defconfig +++ b/configs/P1025RDB_36BIT_defconfig @@ -60,4 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index dff2afa344..13f16ef246 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -88,3 +88,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 700fabeef1..c11c304d8d 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -83,3 +83,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 6b6ab7e57d..2ea28e734c 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -85,3 +85,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 88e24c30ba..1140177bdd 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -72,3 +72,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 4670d823c2..af48fc5e98 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -65,3 +65,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index dc23e107b8..0fa5caa54b 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -64,3 +64,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig index 35a9d00e4b..e1b2ee0652 100644 --- a/configs/P2041RDB_SECURE_BOOT_defconfig +++ b/configs/P2041RDB_SECURE_BOOT_defconfig @@ -54,6 +54,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index bf8d9a2381..99611caf3b 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -65,3 +65,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig index dd5f2a4fc0..2832a86e54 100644 --- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig @@ -47,4 +47,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index bbf6ea61a3..cd05a7ae82 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -63,3 +63,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig index 8ab25373c9..c14a05b644 100644 --- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -53,6 +53,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 55613ccacd..f774e1f635 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -62,3 +62,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index b52068d050..89678ea1ef 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -61,3 +61,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig index d6cabebeb7..afb1aec5cc 100644 --- a/configs/P3041DS_SECURE_BOOT_defconfig +++ b/configs/P3041DS_SECURE_BOOT_defconfig @@ -51,6 +51,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 3af52b90e8..a5d881aa28 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -62,3 +62,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig index c34311b2f9..6c7b951654 100644 --- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig @@ -47,4 +47,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index cc3234c6b1..0a766c89f3 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -60,3 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 18ad56ac8d..c0d184e58f 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -60,3 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig index 22a6ebe89c..e4d494bdf9 100644 --- a/configs/P4080DS_SECURE_BOOT_defconfig +++ b/configs/P4080DS_SECURE_BOOT_defconfig @@ -50,6 +50,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 81a513bec9..f171d7cb21 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -61,3 +61,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig index a740bc4a7b..46aee4dee9 100644 --- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig @@ -45,4 +45,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 52db2e06c7..2980020d3e 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -59,3 +59,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig index 52efa92009..5f0c597cef 100644 --- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -54,6 +54,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig index baf7d835bc..b711f3bcc2 100644 --- a/configs/P5020DS_NAND_defconfig +++ b/configs/P5020DS_NAND_defconfig @@ -54,4 +54,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig index c5b424145c..b459047780 100644 --- a/configs/P5020DS_SDCARD_defconfig +++ b/configs/P5020DS_SDCARD_defconfig @@ -52,4 +52,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig index c08f9fffa6..79e8cc9bfa 100644 --- a/configs/P5020DS_SECURE_BOOT_defconfig +++ b/configs/P5020DS_SECURE_BOOT_defconfig @@ -51,6 +51,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig index 03d7a16a6d..3777c1d2d0 100644 --- a/configs/P5020DS_SPIFLASH_defconfig +++ b/configs/P5020DS_SPIFLASH_defconfig @@ -53,4 +53,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig index 7569364252..9b7cb68878 100644 --- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig @@ -47,4 +47,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig index a1b410c7b6..77fcf26e55 100644 --- a/configs/P5020DS_defconfig +++ b/configs/P5020DS_defconfig @@ -51,4 +51,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig index beab855eae..782b027ef3 100644 --- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -54,6 +54,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index efffb706fb..35584e251e 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -63,3 +63,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index fdd39acbaf..91c02855fb 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -61,3 +61,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig index 5d48206dc8..34e024af13 100644 --- a/configs/P5040DS_SECURE_BOOT_defconfig +++ b/configs/P5040DS_SECURE_BOOT_defconfig @@ -51,6 +51,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 3f4642f4e0..49a2b93066 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -62,3 +62,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index d2a2e02dcd..a797088d7c 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -60,3 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index 385dcb3947..2a544d78cf 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -74,4 +74,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index 825ab47f93..641b3929a3 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -71,4 +71,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index 34fe6e5e52..a9c9794410 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -58,6 +58,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index d537047d60..e30695e027 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -74,4 +74,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index 62cc129a31..3366ff0201 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -58,4 +58,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 0d38d6656f..2c5ae11e58 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -87,3 +87,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index d091d7c0ad..f9bf5acab1 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -84,3 +84,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index fe3d28b373..bbcf145a08 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -63,6 +63,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index cab645dfb2..d550959220 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -87,3 +87,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 46c857d6c5..20e85c12d2 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -72,3 +72,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig index 21875e6c15..17664daa1b 100644 --- a/configs/T1040D4RDB_NAND_defconfig +++ b/configs/T1040D4RDB_NAND_defconfig @@ -72,4 +72,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig index 07c4974c96..72440c61ef 100644 --- a/configs/T1040D4RDB_SDCARD_defconfig +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -69,4 +69,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig index 7adffb73ea..01fa29c1db 100644 --- a/configs/T1040D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -55,6 +55,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig index 8979ebf4b4..8abc3f74b7 100644 --- a/configs/T1040D4RDB_SPIFLASH_defconfig +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -72,4 +72,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig index eb25930ff7..dcf3dce0ee 100644 --- a/configs/T1040D4RDB_defconfig +++ b/configs/T1040D4RDB_defconfig @@ -56,4 +56,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig index b2c07d5f67..f08e03f424 100644 --- a/configs/T1040RDB_NAND_defconfig +++ b/configs/T1040RDB_NAND_defconfig @@ -73,4 +73,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig index 2c64794650..047fca3d02 100644 --- a/configs/T1040RDB_SDCARD_defconfig +++ b/configs/T1040RDB_SDCARD_defconfig @@ -70,4 +70,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index 910b984f47..aa22883e54 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -56,6 +56,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig index a7f9f7db19..19a0a8f8db 100644 --- a/configs/T1040RDB_SPIFLASH_defconfig +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -73,4 +73,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig index e8c5393b18..56d61ae93e 100644 --- a/configs/T1040RDB_defconfig +++ b/configs/T1040RDB_defconfig @@ -57,4 +57,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index f607973fcc..855f9a49d3 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -84,3 +84,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index e31d95aed9..81362a8ea9 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -81,3 +81,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index f460b17e4d..b9adcc0053 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -58,6 +58,8 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 11bbdb4321..e5e4fea1c5 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -84,3 +84,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 70ddffb3a7..2c6e8d00c1 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -69,3 +69,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig index a6878f5626..ffb65d2278 100644 --- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig @@ -79,6 +79,8 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index 5585517757..a048862a8d 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -77,4 +77,6 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index 4aadd90c7a..12e96a09ec 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -74,4 +74,6 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index b8a96cc173..56173ebaf0 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -77,4 +77,6 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index 07ad865b6e..4a9e5348ee 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -61,4 +61,6 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig index c5f39e82f6..2633b830ef 100644 --- a/configs/T1042RDB_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -55,6 +55,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig index c94730d79b..0755a95d10 100644 --- a/configs/T1042RDB_defconfig +++ b/configs/T1042RDB_defconfig @@ -56,4 +56,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 1de486f64b..d088e1189a 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -81,3 +81,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 0e2dce224d..c12a651eab 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -78,3 +78,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 9b3f709c87..35891cc01a 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -65,6 +65,8 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 49db2fec7c..901ad2cad0 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -81,3 +81,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 4958435ef4..38d947c8c2 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -58,3 +58,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 602bf577e0..a5bd06c5ac 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -66,3 +66,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 5ec264b9c3..da21b315a5 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -82,3 +82,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 05fa2d66c0..6e23c57d13 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -79,3 +79,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index 7d04a94116..1a89cd8899 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -57,6 +57,8 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index da562d222d..8af05eefe8 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -82,3 +82,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index a8f0a965c1..729edaa41a 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -50,4 +50,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 85e3b64ad3..d957e40cb3 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -66,3 +66,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig index bf2f36f1a4..d40fd6e561 100644 --- a/configs/T2081QDS_NAND_defconfig +++ b/configs/T2081QDS_NAND_defconfig @@ -72,4 +72,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig index f6ebc4814e..bc229284d0 100644 --- a/configs/T2081QDS_SDCARD_defconfig +++ b/configs/T2081QDS_SDCARD_defconfig @@ -69,4 +69,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig index cd8fa25b74..82bacdbf6d 100644 --- a/configs/T2081QDS_SPIFLASH_defconfig +++ b/configs/T2081QDS_SPIFLASH_defconfig @@ -72,4 +72,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig index a10f39b336..87cfb5f100 100644 --- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig @@ -48,4 +48,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig index 22ca08363c..c7ff58a958 100644 --- a/configs/T2081QDS_defconfig +++ b/configs/T2081QDS_defconfig @@ -56,4 +56,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig index f3c7e1ec57..70e6d92bcd 100644 --- a/configs/T4160RDB_defconfig +++ b/configs/T4160RDB_defconfig @@ -51,4 +51,6 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_OF_LIBFDT=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 85825da8f3..e916fbfcc6 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -72,3 +72,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index dfe8953af7..2d8ab6f50a 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -60,3 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 3d51ec9606..7e9a7a3cc3 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -62,10 +62,10 @@ CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y +CONFIG_VIDEO_COPY=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_VIDEO_IVYBRIDGE_IGD=y -CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y # CONFIG_GZIP is not set diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index c18cba9cf4..bf03cdeead 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -67,8 +67,8 @@ CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y +CONFIG_VIDEO_COPY=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y -CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_TPM=y # CONFIG_GZIP is not set diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig index 90fe803ac8..41785d09d0 100644 --- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig @@ -64,5 +64,6 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_ADDR_MAP=y CONFIG_TPM=y CONFIG_OF_LIBFDT=y diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig index 55a46c3c29..777f5aee41 100644 --- a/configs/controlcenterd_36BIT_SDCARD_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_defconfig @@ -64,5 +64,6 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_ADDR_MAP=y CONFIG_TPM=y CONFIG_OF_LIBFDT=y diff --git a/configs/cortina_presidio-asic-emmc_defconfig b/configs/cortina_presidio-asic-emmc_defconfig index e10008a2b7..e45e23c2a0 100644 --- a/configs/cortina_presidio-asic-emmc_defconfig +++ b/configs/cortina_presidio-asic-emmc_defconfig @@ -10,6 +10,7 @@ CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="G3#" +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_WDT=y @@ -24,6 +25,8 @@ CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" # CONFIG_NET is not set CONFIG_DM=y CONFIG_CORTINA_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CA=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_CORTINA=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index fe3c6c4762..31a5d91af2 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" D2 v2" +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="d2v2> " CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y +CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -39,15 +39,20 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_ENV_ADDR=0x70000 -CONFIG_MVSATA_IDE=y +CONFIG_DM=y +CONFIG_SATA_MV=y +CONFIG_BLK=y # CONFIG_MMC is not set -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 1edd832a1b..2085887adb 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -24,40 +25,47 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0x1 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_CMD_TLV_EEPROM=y +CONFIG_SPL_CMD_TLV_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y -CONFIG_SCSI_AHCI=y +CONFIG_AHCI_MVEBU=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_EEPROM=y +CONFIG_SPL_I2C_EEPROM=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_SPEED=104000000 CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_MII=y +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 6144eb5fad..b5973977a5 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" IS v2" +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y +CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -39,15 +39,20 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_ENV_ADDR=0x70000 -CONFIG_MVSATA_IDE=y +CONFIG_DM=y +CONFIG_SATA_MV=y +CONFIG_BLK=y # CONFIG_MMC is not set -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig index a0d2c1a726..cf54e9fd30 100644 --- a/configs/kmcoge4_defconfig +++ b/configs/kmcoge4_defconfig @@ -64,5 +64,7 @@ CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_FSL_ESPI=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_BCH=y CONFIG_OF_LIBFDT=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 40ed9e4120..13d6edd08c 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -59,7 +59,7 @@ CONFIG_RTL8169=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y +CONFIG_VIDEO_COPY=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_11B=y -CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_FRAMEBUFFER_VESA_MODE_118=y # CONFIG_GZIP is not set diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 1389d30900..bba8503049 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" 2Big v2" +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="2big2> " CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y +CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -39,15 +39,20 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_ENV_ADDR=0x70000 -CONFIG_MVSATA_IDE=y +CONFIG_DM=y +CONFIG_SATA_MV=y +CONFIG_BLK=y # CONFIG_MMC is not set -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index c744d2c58e..bfa93dbd1c 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" NS v2 Lite" +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y +CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -39,15 +39,21 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_ENV_ADDR=0x70000 -CONFIG_MVSATA_IDE=y +CONFIG_DM=y +CONFIG_SATA_MV=y +CONFIG_BLK=y # CONFIG_MMC is not set -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 8602729fcb..d0f750369a 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" NS Max v2" +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y +CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -39,15 +39,21 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_ENV_ADDR=0x70000 -CONFIG_MVSATA_IDE=y +CONFIG_DM=y +CONFIG_SATA_MV=y +CONFIG_BLK=y # CONFIG_MMC is not set -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index ba9301de4d..6cfaccf51d 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" NS v2 Mini" +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y +CONFIG_CMD_SATA=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -37,12 +37,16 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_ENV_ADDR=0x70000 -CONFIG_MVSATA_IDE=y +CONFIG_DM=y +CONFIG_SATA_MV=y +CONFIG_BLK=y # CONFIG_MMC is not set -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 6ba1ef423e..1bd148f9b5 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" NS v2" +# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y +CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -39,15 +39,20 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_ENV_ADDR=0x70000 -CONFIG_MVSATA_IDE=y +CONFIG_DM=y +CONFIG_SATA_MV=y +CONFIG_BLK=y # CONFIG_MMC is not set -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index ab4bc5d327..ba2ee27658 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -27,5 +27,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_ADDR_MAP=y CONFIG_PANIC_HANG=y CONFIG_OF_LIBFDT=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 0df5c17d6e..db7b781976 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x4000 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" @@ -26,6 +30,9 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_BCMGENET=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_BRCMSTB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_DM_RESET=y @@ -33,6 +40,8 @@ CONFIG_DM_RESET=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 @@ -45,4 +54,6 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=2 CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index ac604b57b6..dcf2f44b58 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -60,6 +60,7 @@ CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_ETHSW=y CONFIG_CMD_BMP=y CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_SOUND=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 8cf2ad5fe4..9b74e404bb 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -69,6 +69,7 @@ CONFIG_CMD_ETHSW=y CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_SOUND=y @@ -219,6 +220,7 @@ CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_COPY=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index dfcc43532a..4158b9b86d 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_SOUND=y diff --git a/doc/device-tree-bindings/i2c/i2c-cortina.txt b/doc/device-tree-bindings/i2c/i2c-cortina.txt new file mode 100644 index 0000000000..59d523582a --- /dev/null +++ b/doc/device-tree-bindings/i2c/i2c-cortina.txt @@ -0,0 +1,18 @@ +* I2C for Cortina platforms + +Required properties : +- compatible : Must be "cortina,ca-i2c" +- reg : Offset and length of the register set for the device + +Recommended properties : +- clock-frequency : desired I2C bus clock frequency in Hz. If not specified, + default value is 100000. Possible values are 100000, + 400000 and 1000000. + +Examples : + + i2c: i2c@f4329120 { + compatible = "cortina,ca-i2c"; + reg = <0x0 0xf4329120 0x28>; + clock-frequency = <400000>; + }; diff --git a/doc/device-tree-bindings/i2c/octeon-i2c.txt b/doc/device-tree-bindings/i2c/octeon-i2c.txt new file mode 100644 index 0000000000..9c1908ec2c --- /dev/null +++ b/doc/device-tree-bindings/i2c/octeon-i2c.txt @@ -0,0 +1,24 @@ +* I2C controller embedded in Marvell Octeon platforms + +Required properties : +- compatible : Must be "cavium,octeon-7890-twsi" or a compatible string +- reg : Offset and length of the register set for the device +- clocks: Must contain the input clock of the I2C instance +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties : +- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, + the default 100 kHz frequency will be used. As only Normal, Fast and Fast+ + modes are implemented, possible values are 100000, 400000 and 1000000. + +Example : + + i2c0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + clock-frequency = <100000>; + clocks = <&sclk>; + }; diff --git a/doc/device-tree-bindings/pwm/pwm-sifive.txt b/doc/device-tree-bindings/pwm/pwm-sifive.txt new file mode 100644 index 0000000000..9a988372c4 --- /dev/null +++ b/doc/device-tree-bindings/pwm/pwm-sifive.txt @@ -0,0 +1,31 @@ +SiFive PWM controller + +Unlike most other PWM controllers, the SiFive PWM controller currently only +supports one period for all channels in the PWM. All PWMs need to run at +the same period. The period also has significant restrictions on the values +it can achieve, which the driver rounds to the nearest achievable period. +PWM RTL that corresponds to the IP block version numbers can be found +here: + +https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm + +Required properties: +- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". + Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive + PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the + SiFive PWM v0 IP block with no chip integration tweaks. +- reg: physical base address and length of the controller's registers +- clocks: Should contain a clock identifier for the PWM's parent clock. +- #pwm-cells: Should be 3. +- interrupts: one interrupt per PWM channel + +Examples: + +pwm: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + clocks = <&tlclk>; + interrupt-parent = <&plic>; + interrupts = <42 43 44 45>; + #pwm-cells = <3>; +}; diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index df832ac6dc..58ffb20507 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -11,7 +11,7 @@ #define VREF_MAX_INDEX 7 #define MAX_VALUE (1024 - 1) #define MIN_VALUE (-MAX_VALUE) -#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf) +#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f) u32 ca_delay; int ddr3_tip_centr_skip_min_win_check = 0; @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) min_read_sample = read_sample[cs_num]; } - min_read_sample = min_read_sample - 1; - max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1; + min_read_sample = min_read_sample + 2; + max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1; if (min_read_sample >= 0xf) min_read_sample = 0xf; if (max_read_sample >= 0x1f) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index f8b18de8f3..87d11b663c 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -93,6 +93,14 @@ config SYS_I2C_CADENCE Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq. +config SYS_I2C_CA + tristate "Cortina-Access I2C Controller" + depends on DM_I2C && CORTINA_PLATFORM + default n + help + Add support for the Cortina Access I2C host controller. + Say yes here to select Cortina-Access I2C Host Controller. + config SYS_I2C_DAVINCI bool "Davinci I2C Controller" depends on (ARCH_KEYSTONE || ARCH_DAVINCI) @@ -374,6 +382,16 @@ config SYS_I2C_SANDBOX bus. Devices can be attached to the bus using the device tree which specifies the driver to use. See sandbox.dts as an example. +config SYS_I2C_OCTEON + bool "Octeon II/III/TX/TX2 I2C driver" + depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C + default y + help + Add support for the Marvell Octeon I2C driver. This is used with + various Octeon parts such as Octeon II/III and OcteonTX/TX2. All + chips have several I2C ports and all are provided, controlled by + the device tree. + config SYS_I2C_S3C24X0 bool "Samsung I2C driver" depends on ARCH_EXYNOS4 && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 62935b7ebc..174081e252 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o +obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o ifdef CONFIG_DM_PCI @@ -27,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o +obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o diff --git a/drivers/i2c/i2c-cortina.c b/drivers/i2c/i2c-cortina.c new file mode 100644 index 0000000000..036fc4282b --- /dev/null +++ b/drivers/i2c/i2c-cortina.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 + * Arthur Li, Cortina Access, arthur.li@cortina-access.com. + */ + +#include <common.h> +#include <i2c.h> +#include <log.h> +#include <asm/io.h> +#include <dm.h> +#include <mapmem.h> +#include "i2c-cortina.h" + +static void set_speed(struct i2c_regs *regs, int i2c_spd) +{ + union ca_biw_cfg i2c_cfg; + + i2c_cfg.wrd = readl(®s->i2c_cfg); + i2c_cfg.bf.core_en = 0; + writel(i2c_cfg.wrd, ®s->i2c_cfg); + + switch (i2c_spd) { + case IC_SPEED_MODE_FAST_PLUS: + i2c_cfg.bf.prer = CORTINA_PER_IO_FREQ / + (5 * I2C_SPEED_FAST_PLUS_RATE) - 1; + break; + + case IC_SPEED_MODE_STANDARD: + i2c_cfg.bf.prer = CORTINA_PER_IO_FREQ / + (5 * I2C_SPEED_STANDARD_RATE) - 1; + break; + + case IC_SPEED_MODE_FAST: + default: + i2c_cfg.bf.prer = CORTINA_PER_IO_FREQ / + (5 * I2C_SPEED_FAST_RATE) - 1; + break; + } + + i2c_cfg.bf.core_en = 1; + writel(i2c_cfg.wrd, ®s->i2c_cfg); +} + +static int ca_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct ca_i2c *priv = dev_get_priv(bus); + int i2c_spd; + + if (speed >= I2C_SPEED_FAST_PLUS_RATE) { + i2c_spd = IC_SPEED_MODE_FAST_PLUS; + priv->speed = I2C_SPEED_FAST_PLUS_RATE; + } else if (speed >= I2C_SPEED_FAST_RATE) { + i2c_spd = IC_SPEED_MODE_FAST; + priv->speed = I2C_SPEED_FAST_RATE; + } else { + i2c_spd = IC_SPEED_MODE_STANDARD; + priv->speed = I2C_SPEED_STANDARD_RATE; + } + + set_speed(priv->regs, i2c_spd); + + return 0; +} + +static int ca_i2c_get_bus_speed(struct udevice *bus) +{ + struct ca_i2c *priv = dev_get_priv(bus); + + return priv->speed; +} + +static void ca_i2c_init(struct i2c_regs *regs) +{ + union ca_biw_cfg i2c_cfg; + + i2c_cfg.wrd = readl(®s->i2c_cfg); + i2c_cfg.bf.core_en = 0; + i2c_cfg.bf.biw_soft_reset = 1; + writel(i2c_cfg.wrd, ®s->i2c_cfg); + mdelay(10); + i2c_cfg.bf.biw_soft_reset = 0; + writel(i2c_cfg.wrd, ®s->i2c_cfg); + + set_speed(regs, IC_SPEED_MODE_STANDARD); + + i2c_cfg.wrd = readl(®s->i2c_cfg); + i2c_cfg.bf.core_en = 1; + writel(i2c_cfg.wrd, ®s->i2c_cfg); +} + +static int i2c_wait_complete(struct i2c_regs *regs) +{ + union ca_biw_ctrl i2c_ctrl; + unsigned long start_time_bb = get_timer(0); + + i2c_ctrl.wrd = readl(®s->i2c_ctrl); + + while (i2c_ctrl.bf.biwdone == 0) { + i2c_ctrl.wrd = readl(®s->i2c_ctrl); + + if (get_timer(start_time_bb) > + (unsigned long)(I2C_BYTE_TO_BB)) { + printf("%s not done!!!\n", __func__); + return -ETIMEDOUT; + } + } + + /* Clear done bit */ + writel(i2c_ctrl.wrd, ®s->i2c_ctrl); + + return 0; +} + +static void i2c_setaddress(struct i2c_regs *regs, unsigned int i2c_addr, + int write_read) +{ + writel(i2c_addr | write_read, ®s->i2c_txr); + + writel(BIW_CTRL_START | BIW_CTRL_WRITE, + ®s->i2c_ctrl); + + i2c_wait_complete(regs); +} + +static int i2c_wait_for_bus_busy(struct i2c_regs *regs) +{ + union ca_biw_ack i2c_ack; + unsigned long start_time_bb = get_timer(0); + + i2c_ack.wrd = readl(®s->i2c_ack); + + while (i2c_ack.bf.biw_busy) { + i2c_ack.wrd = readl(®s->i2c_ack); + + if (get_timer(start_time_bb) > + (unsigned long)(I2C_BYTE_TO_BB)) { + printf("%s: timeout!\n", __func__); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int i2c_xfer_init(struct i2c_regs *regs, uint8_t chip, uint addr, + int alen, int write_read) +{ + int addr_len = alen; + + if (i2c_wait_for_bus_busy(regs)) + return 1; + + /* First cycle must write addr + offset */ + chip = ((chip & 0x7F) << 1); + if (alen == 0 && write_read == I2C_CMD_RD) + i2c_setaddress(regs, chip, I2C_CMD_RD); + else + i2c_setaddress(regs, chip, I2C_CMD_WT); + + while (alen) { + alen--; + writel(addr, ®s->i2c_txr); + if (write_read == I2C_CMD_RD) + writel(BIW_CTRL_WRITE | BIW_CTRL_STOP, + ®s->i2c_ctrl); + else + writel(BIW_CTRL_WRITE, ®s->i2c_ctrl); + i2c_wait_complete(regs); + } + + /* Send address again with Read flag if it's read command */ + if (write_read == I2C_CMD_RD && addr_len > 0) + i2c_setaddress(regs, chip, I2C_CMD_RD); + + return 0; +} + +static int i2c_xfer_finish(struct i2c_regs *regs) +{ + /* Dummy read makes bus free */ + writel(BIW_CTRL_READ | BIW_CTRL_STOP, ®s->i2c_ctrl); + i2c_wait_complete(regs); + + if (i2c_wait_for_bus_busy(regs)) { + printf("Timed out waiting for bus\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int ca_i2c_read(struct i2c_regs *regs, uint8_t chip, uint addr, + int alen, uint8_t *buffer, int len) +{ + unsigned long start_time_rx; + int rc = 0; + + rc = i2c_xfer_init(regs, chip, addr, alen, I2C_CMD_RD); + if (rc) + return rc; + + start_time_rx = get_timer(0); + while (len) { + /* ACK_IN is ack value to send during read. + * ack high only on the very last byte! + */ + if (len == 1) + writel(BIW_CTRL_READ | BIW_CTRL_ACK_IN | BIW_CTRL_STOP, + ®s->i2c_ctrl); + else + writel(BIW_CTRL_READ, ®s->i2c_ctrl); + + rc = i2c_wait_complete(regs); + udelay(1); + + if (rc == 0) { + *buffer++ = + (uchar) readl(®s->i2c_rxr); + len--; + start_time_rx = get_timer(0); + + } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { + return -ETIMEDOUT; + } + } + i2c_xfer_finish(regs); + return rc; +} + +static int ca_i2c_write(struct i2c_regs *regs, uint8_t chip, uint addr, + int alen, uint8_t *buffer, int len) +{ + int rc, nb = len; + unsigned long start_time_tx; + + rc = i2c_xfer_init(regs, chip, addr, alen, I2C_CMD_WT); + if (rc) + return rc; + + start_time_tx = get_timer(0); + while (len) { + writel(*buffer, ®s->i2c_txr); + if (len == 1) + writel(BIW_CTRL_WRITE | BIW_CTRL_STOP, + ®s->i2c_ctrl); + else + writel(BIW_CTRL_WRITE, ®s->i2c_ctrl); + + rc = i2c_wait_complete(regs); + + if (rc == 0) { + len--; + buffer++; + start_time_tx = get_timer(0); + } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { + return -ETIMEDOUT; + } + } + + return 0; +} + +static int ca_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct ca_i2c *priv = dev_get_priv(bus); + int ret; + u32 tmp; + + /* Try to read the first location of the chip */ + ret = ca_i2c_read(priv->regs, chip_addr, 0, 1, (uchar *)&tmp, 1); + if (ret) + ca_i2c_init(priv->regs); + + return ret; +} + +static int ca_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct ca_i2c *priv = dev_get_priv(bus); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) + ret = ca_i2c_read(priv->regs, msg->addr, 0, 0, + msg->buf, msg->len); + else + ret = ca_i2c_write(priv->regs, msg->addr, 0, 0, + msg->buf, msg->len); + + if (ret) { + printf("i2c_xfer: %s error\n", + msg->flags & I2C_M_RD ? "read" : "write"); + return ret; + } + } + + return 0; +} + +static const struct dm_i2c_ops ca_i2c_ops = { + .xfer = ca_i2c_xfer, + .probe_chip = ca_i2c_probe_chip, + .set_bus_speed = ca_i2c_set_bus_speed, + .get_bus_speed = ca_i2c_get_bus_speed, +}; + +static const struct udevice_id ca_i2c_ids[] = { + { .compatible = "cortina,ca-i2c", }, + { } +}; + +static int ca_i2c_probe(struct udevice *bus) +{ + struct ca_i2c *priv = dev_get_priv(bus); + + ca_i2c_init(priv->regs); + + return 0; +} + +static int ca_i2c_ofdata_to_platdata(struct udevice *bus) +{ + struct ca_i2c *priv = dev_get_priv(bus); + + priv->regs = map_sysmem(dev_read_addr(bus), sizeof(struct i2c_regs)); + if (!priv->regs) { + printf("I2C: base address is invalid\n"); + return -EINVAL; + } + + return 0; +} + +U_BOOT_DRIVER(i2c_cortina) = { + .name = "i2c_cortina", + .id = UCLASS_I2C, + .of_match = ca_i2c_ids, + .ofdata_to_platdata = ca_i2c_ofdata_to_platdata, + .probe = ca_i2c_probe, + .priv_auto_alloc_size = sizeof(struct ca_i2c), + .ops = &ca_i2c_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/i2c/i2c-cortina.h b/drivers/i2c/i2c-cortina.h new file mode 100644 index 0000000000..7e406b580e --- /dev/null +++ b/drivers/i2c/i2c-cortina.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 + * Cortina Access, <www.cortina-access.com> + */ + +#ifndef __CA_I2C_H_ +#define __CA_I2C_H_ + +#include <linux/bitops.h> +#include <linux/delay.h> + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) +struct i2c_regs { + u32 i2c_cfg; + u32 i2c_ctrl; + u32 i2c_txr; + u32 i2c_rxr; + u32 i2c_ack; + u32 i2c_ie0; + u32 i2c_int0; + u32 i2c_ie1; + u32 i2c_int1; + u32 i2c_stat; +}; + +union ca_biw_cfg { + struct biw_cfg { + u32 core_en : 1; + u32 biw_soft_reset : 1; + u32 busywait_en : 1; + u32 stretch_en : 1; + u32 arb_en : 1; + u32 clksync_en : 1; + u32 rsrvd1 : 2; + u32 spike_cnt : 4; + u32 rsrvd2 : 4; + u32 prer : 16; + } bf; + unsigned int wrd; +}; + +union ca_biw_ctrl { + struct biw_ctrl { + u32 biwdone : 1; + u32 rsrvd1 : 2; + u32 ack_in : 1; + u32 write : 1; + u32 read : 1; + u32 stop : 1; + u32 start : 1; + u32 rsrvd2 : 24; + } bf; + unsigned int wrd; +}; + +union ca_biw_ack { + struct biw_ack { + u32 al :1; + u32 biw_busy :1; + u32 ack_out :1; + u32 rsrvd1 :29; + } bf; + unsigned int wrd; +}; +#endif /* !__ASSEMBLER__*/ + +struct ca_i2c { + struct i2c_regs *regs; + unsigned int speed; +}; + +#define I2C_CMD_WT 0 +#define I2C_CMD_RD 1 + +#define BIW_CTRL_DONE BIT(0) +#define BIW_CTRL_ACK_IN BIT(3) +#define BIW_CTRL_WRITE BIT(4) +#define BIW_CTRL_READ BIT(5) +#define BIW_CTRL_STOP BIT(6) +#define BIW_CTRL_START BIT(7) + +#define I2C_BYTE_TO (CONFIG_SYS_HZ / 500) +#define I2C_STOPDET_TO (CONFIG_SYS_HZ / 500) +#define I2C_BYTE_TO_BB (10) + +#endif /* __CA_I2C_H_ */ diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index c8e42e05f5..b7b2aafc7f 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -97,7 +97,8 @@ static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs) static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len) { - struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); + struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base); lpi2c_status_t result = LPI2C_SUCESS; /* empty tx */ @@ -118,7 +119,8 @@ static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len) static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len) { - struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); + struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base); lpi2c_status_t result = LPI2C_SUCESS; u32 val; ulong start_time = get_timer(0); @@ -162,8 +164,8 @@ static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len) static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir) { lpi2c_status_t result; - struct imx_lpi2c_reg *regs = - (struct imx_lpi2c_reg *)devfdt_get_addr(bus); + struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base); u32 val; result = imx_lpci2c_check_busy_bus(regs); @@ -199,8 +201,8 @@ static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir) static int bus_i2c_stop(struct udevice *bus) { lpi2c_status_t result; - struct imx_lpi2c_reg *regs = - (struct imx_lpi2c_reg *)devfdt_get_addr(bus); + struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base); u32 status; ulong start_time; @@ -271,7 +273,7 @@ u32 __weak imx_get_i2cclk(u32 i2c_num) static int bus_i2c_set_bus_speed(struct udevice *bus, int speed) { struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); - struct imx_lpi2c_reg *regs; + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base); u32 val; u32 preescale = 0, best_pre = 0, clkhi = 0; u32 best_clkhi = 0, abs_error = 0, rate; @@ -280,8 +282,6 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed) bool mode; int i; - regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); - if (IS_ENABLED(CONFIG_CLK)) { clock_rate = clk_get_rate(&i2c_bus->per_clk); if (clock_rate <= 0) { @@ -348,11 +348,11 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed) static int bus_i2c_init(struct udevice *bus, int speed) { - struct imx_lpi2c_reg *regs; u32 val; int ret; - regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus); + struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base); /* reset peripheral */ writel(LPI2C_MCR_RST_MASK, ®s->mcr); writel(0x0, ®s->mcr); diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c new file mode 100644 index 0000000000..c11d6ff93d --- /dev/null +++ b/drivers/i2c/octeon_i2c.c @@ -0,0 +1,847 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <i2c.h> +#include <pci_ids.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <linux/compat.h> +#include <linux/delay.h> + +#define TWSI_SW_TWSI 0x00 +#define TWSI_TWSI_SW 0x08 +#define TWSI_INT 0x10 +#define TWSI_SW_TWSI_EXT 0x18 + +#define TWSI_SW_DATA_MASK GENMASK_ULL(31, 0) +#define TWSI_SW_EOP_IA_MASK GENMASK_ULL(34, 32) +#define TWSI_SW_IA_MASK GENMASK_ULL(39, 35) +#define TWSI_SW_ADDR_MASK GENMASK_ULL(49, 40) +#define TWSI_SW_SCR_MASK GENMASK_ULL(51, 50) +#define TWSI_SW_SIZE_MASK GENMASK_ULL(54, 52) +#define TWSI_SW_SOVR BIT_ULL(55) +#define TWSI_SW_R BIT_ULL(56) +#define TWSI_SW_OP_MASK GENMASK_ULL(60, 57) +#define TWSI_SW_EIA GENMASK_ULL(61) +#define TWSI_SW_SLONLY BIT_ULL(62) +#define TWSI_SW_V BIT_ULL(63) + +#define TWSI_INT_SDA_OVR BIT_ULL(8) +#define TWSI_INT_SCL_OVR BIT_ULL(9) +#define TWSI_INT_SDA BIT_ULL(10) +#define TWSI_INT_SCL BIT_ULL(11) + +enum { + TWSI_OP_WRITE = 0, + TWSI_OP_READ = 1, +}; + +enum { + TWSI_EOP_SLAVE_ADDR = 0, + TWSI_EOP_CLK_CTL = 3, + TWSI_SW_EOP_IA = 6, +}; + +enum { + TWSI_SLAVEADD = 0, + TWSI_DATA = 1, + TWSI_CTL = 2, + TWSI_CLKCTL = 3, + TWSI_STAT = 3, + TWSI_SLAVEADD_EXT = 4, + TWSI_RST = 7, +}; + +enum { + TWSI_CTL_AAK = BIT(2), + TWSI_CTL_IFLG = BIT(3), + TWSI_CTL_STP = BIT(4), + TWSI_CTL_STA = BIT(5), + TWSI_CTL_ENAB = BIT(6), + TWSI_CTL_CE = BIT(7), +}; + +/* + * Internal errors. When debugging is enabled, the driver will report the + * error number and the user / developer can check the table below for the + * detailed error description. + */ +enum { + /** Bus error */ + TWSI_STAT_BUS_ERROR = 0x00, + /** Start condition transmitted */ + TWSI_STAT_START = 0x08, + /** Repeat start condition transmitted */ + TWSI_STAT_RSTART = 0x10, + /** Address + write bit transmitted, ACK received */ + TWSI_STAT_TXADDR_ACK = 0x18, + /** Address + write bit transmitted, /ACK received */ + TWSI_STAT_TXADDR_NAK = 0x20, + /** Data byte transmitted in master mode, ACK received */ + TWSI_STAT_TXDATA_ACK = 0x28, + /** Data byte transmitted in master mode, ACK received */ + TWSI_STAT_TXDATA_NAK = 0x30, + /** Arbitration lost in address or data byte */ + TWSI_STAT_TX_ARB_LOST = 0x38, + /** Address + read bit transmitted, ACK received */ + TWSI_STAT_RXADDR_ACK = 0x40, + /** Address + read bit transmitted, /ACK received */ + TWSI_STAT_RXADDR_NAK = 0x48, + /** Data byte received in master mode, ACK transmitted */ + TWSI_STAT_RXDATA_ACK_SENT = 0x50, + /** Data byte received, NACK transmitted */ + TWSI_STAT_RXDATA_NAK_SENT = 0x58, + /** Slave address received, sent ACK */ + TWSI_STAT_SLAVE_RXADDR_ACK = 0x60, + /** + * Arbitration lost in address as master, slave address + write bit + * received, ACK transmitted + */ + TWSI_STAT_TX_ACK_ARB_LOST = 0x68, + /** General call address received, ACK transmitted */ + TWSI_STAT_RX_GEN_ADDR_ACK = 0x70, + /** + * Arbitration lost in address as master, general call address + * received, ACK transmitted + */ + TWSI_STAT_RX_GEN_ADDR_ARB_LOST = 0x78, + /** Data byte received after slave address received, ACK transmitted */ + TWSI_STAT_SLAVE_RXDATA_ACK = 0x80, + /** Data byte received after slave address received, /ACK transmitted */ + TWSI_STAT_SLAVE_RXDATA_NAK = 0x88, + /** + * Data byte received after general call address received, ACK + * transmitted + */ + TWSI_STAT_GEN_RXADDR_ACK = 0x90, + /** + * Data byte received after general call address received, /ACK + * transmitted + */ + TWSI_STAT_GEN_RXADDR_NAK = 0x98, + /** STOP or repeated START condition received in slave mode */ + TWSI_STAT_STOP_MULTI_START = 0xa0, + /** Slave address + read bit received, ACK transmitted */ + TWSI_STAT_SLAVE_RXADDR2_ACK = 0xa8, + /** + * Arbitration lost in address as master, slave address + read bit + * received, ACK transmitted + */ + TWSI_STAT_RXDATA_ACK_ARB_LOST = 0xb0, + /** Data byte transmitted in slave mode, ACK received */ + TWSI_STAT_SLAVE_TXDATA_ACK = 0xb8, + /** Data byte transmitted in slave mode, /ACK received */ + TWSI_STAT_SLAVE_TXDATA_NAK = 0xc0, + /** Last byte transmitted in slave mode, ACK received */ + TWSI_STAT_SLAVE_TXDATA_END_ACK = 0xc8, + /** Second address byte + write bit transmitted, ACK received */ + TWSI_STAT_TXADDR2DATA_ACK = 0xd0, + /** Second address byte + write bit transmitted, /ACK received */ + TWSI_STAT_TXADDR2DATA_NAK = 0xd8, + /** No relevant status information */ + TWSI_STAT_IDLE = 0xf8 +}; + +#define CONFIG_SYS_I2C_OCTEON_SLAVE_ADDR 0x77 + +enum { + PROBE_PCI = 0, /* PCI based probing */ + PROBE_DT, /* DT based probing */ +}; + +enum { + CLK_METHOD_OCTEON = 0, + CLK_METHOD_OCTEONTX2, +}; + +/** + * struct octeon_i2c_data - SoC specific data of this driver + * + * @probe: Probing of this SoC (DT vs PCI) + * @reg_offs: Register offset + * @thp: THP define for divider calculation + * @clk_method: Clock calculation method + */ +struct octeon_i2c_data { + int probe; + u32 reg_offs; + int thp; + int clk_method; +}; + +/** + * struct octeon_twsi - Private data of this driver + * + * @base: Base address of i2c registers + * @data: Pointer to SoC specific data struct + */ +struct octeon_twsi { + void __iomem *base; + const struct octeon_i2c_data *data; + struct clk clk; +}; + +static void twsi_unblock(void *base); +static int twsi_stop(void *base); + +/** + * Returns true if we lost arbitration + * + * @code status code + * @final_read true if this is the final read operation + * @return true if arbitration has been lost, false if it hasn't been lost. + */ +static int twsi_i2c_lost_arb(u8 code, int final_read) +{ + switch (code) { + case TWSI_STAT_TX_ARB_LOST: + case TWSI_STAT_TX_ACK_ARB_LOST: + case TWSI_STAT_RX_GEN_ADDR_ARB_LOST: + case TWSI_STAT_RXDATA_ACK_ARB_LOST: + /* Arbitration lost */ + return -EAGAIN; + + case TWSI_STAT_SLAVE_RXADDR_ACK: + case TWSI_STAT_RX_GEN_ADDR_ACK: + case TWSI_STAT_GEN_RXADDR_ACK: + case TWSI_STAT_GEN_RXADDR_NAK: + /* Being addressed as slave, should back off and listen */ + return -EIO; + + case TWSI_STAT_SLAVE_RXDATA_ACK: + case TWSI_STAT_SLAVE_RXDATA_NAK: + case TWSI_STAT_STOP_MULTI_START: + case TWSI_STAT_SLAVE_RXADDR2_ACK: + case TWSI_STAT_SLAVE_TXDATA_ACK: + case TWSI_STAT_SLAVE_TXDATA_NAK: + case TWSI_STAT_SLAVE_TXDATA_END_ACK: + /* Core busy as slave */ + return -EIO; + + case TWSI_STAT_RXDATA_ACK_SENT: + /* Ack allowed on pre-terminal bytes only */ + if (!final_read) + return 0; + return -EAGAIN; + + case TWSI_STAT_RXDATA_NAK_SENT: + /* NAK allowed on terminal byte only */ + if (!final_read) + return 0; + return -EAGAIN; + + case TWSI_STAT_TXDATA_NAK: + case TWSI_STAT_TXADDR_NAK: + case TWSI_STAT_RXADDR_NAK: + case TWSI_STAT_TXADDR2DATA_NAK: + return -EAGAIN; + } + + return 0; +} + +/** + * Writes to the MIO_TWS(0..5)_SW_TWSI register + * + * @base Base address of i2c registers + * @val value to write + * @return 0 for success, otherwise error + */ +static u64 twsi_write_sw(void __iomem *base, u64 val) +{ + unsigned long start = get_timer(0); + + val &= ~TWSI_SW_R; + val |= TWSI_SW_V; + + debug("%s(%p, 0x%llx)\n", __func__, base, val); + writeq(val, base + TWSI_SW_TWSI); + do { + val = readq(base + TWSI_SW_TWSI); + } while ((val & TWSI_SW_V) && (get_timer(start) < 50)); + + if (val & TWSI_SW_V) + debug("%s: timed out\n", __func__); + return val; +} + +/** + * Reads the MIO_TWS(0..5)_SW_TWSI register + * + * @base Base address of i2c registers + * @val value for eia and op, etc. to read + * @return value of the register + */ +static u64 twsi_read_sw(void __iomem *base, u64 val) +{ + unsigned long start = get_timer(0); + + val |= TWSI_SW_R | TWSI_SW_V; + + debug("%s(%p, 0x%llx)\n", __func__, base, val); + writeq(val, base + TWSI_SW_TWSI); + + do { + val = readq(base + TWSI_SW_TWSI); + } while ((val & TWSI_SW_V) && (get_timer(start) < 50)); + + if (val & TWSI_SW_V) + debug("%s: Error writing 0x%llx\n", __func__, val); + + debug("%s: Returning 0x%llx\n", __func__, val); + return val; +} + +/** + * Write control register + * + * @base Base address for i2c registers + * @data data to write + */ +static void twsi_write_ctl(void __iomem *base, u8 data) +{ + u64 val; + + debug("%s(%p, 0x%x)\n", __func__, base, data); + val = data | FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CTL) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); + twsi_write_sw(base, val); +} + +/** + * Reads the TWSI Control Register + * + * @base Base address for i2c + * @return 8-bit TWSI control register + */ +static u8 twsi_read_ctl(void __iomem *base) +{ + u64 val; + + val = FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CTL) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); + val = twsi_read_sw(base, val); + + debug("%s(%p): 0x%x\n", __func__, base, (u8)val); + return (u8)val; +} + +/** + * Read i2c status register + * + * @base Base address of i2c registers + * @return value of status register + */ +static u8 twsi_read_status(void __iomem *base) +{ + u64 val; + + val = FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_STAT) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); + + return twsi_read_sw(base, val); +} + +/** + * Waits for an i2c operation to complete + * + * @param base Base address of registers + * @return 0 for success, 1 if timeout + */ +static int twsi_wait(void __iomem *base) +{ + unsigned long start = get_timer(0); + u8 twsi_ctl; + + debug("%s(%p)\n", __func__, base); + do { + twsi_ctl = twsi_read_ctl(base); + twsi_ctl &= TWSI_CTL_IFLG; + } while (!twsi_ctl && get_timer(start) < 50); + + debug(" return: %u\n", !twsi_ctl); + return !twsi_ctl; +} + +/** + * Unsticks the i2c bus + * + * @base base address of registers + */ +static int twsi_start_unstick(void __iomem *base) +{ + twsi_stop(base); + twsi_unblock(base); + + return 0; +} + +/** + * Sends an i2c start condition + * + * @base base address of registers + * @return 0 for success, otherwise error + */ +static int twsi_start(void __iomem *base) +{ + int ret; + u8 stat; + + debug("%s(%p)\n", __func__, base); + twsi_write_ctl(base, TWSI_CTL_STA | TWSI_CTL_ENAB); + ret = twsi_wait(base); + if (ret) { + stat = twsi_read_status(base); + debug("%s: ret: 0x%x, status: 0x%x\n", __func__, ret, stat); + switch (stat) { + case TWSI_STAT_START: + case TWSI_STAT_RSTART: + return 0; + case TWSI_STAT_RXADDR_ACK: + default: + return twsi_start_unstick(base); + } + } + + debug("%s: success\n", __func__); + return 0; +} + +/** + * Sends an i2c stop condition + * + * @base register base address + * @return 0 for success, -1 if error + */ +static int twsi_stop(void __iomem *base) +{ + u8 stat; + + twsi_write_ctl(base, TWSI_CTL_STP | TWSI_CTL_ENAB); + + stat = twsi_read_status(base); + if (stat != TWSI_STAT_IDLE) { + debug("%s: Bad status on bus@%p\n", __func__, base); + return -1; + } + + return 0; +} + +/** + * Writes data to the i2c bus + * + * @base register base address + * @slave_addr address of slave to write to + * @buffer Pointer to buffer to write + * @length Number of bytes in buffer to write + * @return 0 for success, otherwise error + */ +static int twsi_write_data(void __iomem *base, u8 slave_addr, + u8 *buffer, unsigned int length) +{ + unsigned int curr = 0; + u64 val; + int ret; + + debug("%s(%p, 0x%x, %p, 0x%x)\n", __func__, base, slave_addr, + buffer, length); + ret = twsi_start(base); + if (ret) { + debug("%s: Could not start BUS transaction\n", __func__); + return -1; + } + + ret = twsi_wait(base); + if (ret) { + debug("%s: wait failed\n", __func__); + return ret; + } + + val = (u32)(slave_addr << 1) | TWSI_OP_WRITE | + FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); + twsi_write_sw(base, val); + twsi_write_ctl(base, TWSI_CTL_ENAB); + + debug("%s: Waiting\n", __func__); + ret = twsi_wait(base); + if (ret) { + debug("%s: Timed out writing slave address 0x%x to target\n", + __func__, slave_addr); + return ret; + } + + ret = twsi_read_status(base); + debug("%s: status: 0x%x\n", __func__, ret); + if (ret != TWSI_STAT_TXADDR_ACK) { + debug("%s: status: 0x%x\n", __func__, ret); + twsi_stop(base); + return twsi_i2c_lost_arb(ret, 0); + } + + while (curr < length) { + val = buffer[curr++] | + FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); + twsi_write_sw(base, val); + twsi_write_ctl(base, TWSI_CTL_ENAB); + + debug("%s: Writing 0x%llx\n", __func__, val); + + ret = twsi_wait(base); + if (ret) { + debug("%s: Timed out writing data to 0x%x\n", + __func__, slave_addr); + return ret; + } + ret = twsi_read_status(base); + debug("%s: status: 0x%x\n", __func__, ret); + } + + debug("%s: Stopping\n", __func__); + return twsi_stop(base); +} + +/** + * Manually clear the I2C bus and send a stop + * + * @base register base address + */ +static void twsi_unblock(void __iomem *base) +{ + int i; + + for (i = 0; i < 9; i++) { + writeq(0, base + TWSI_INT); + udelay(5); + writeq(TWSI_INT_SCL_OVR, base + TWSI_INT); + udelay(5); + } + writeq(TWSI_INT_SCL_OVR | TWSI_INT_SDA_OVR, base + TWSI_INT); + udelay(5); + writeq(TWSI_INT_SDA_OVR, base + TWSI_INT); + udelay(5); + writeq(0, base + TWSI_INT); + udelay(5); +} + +/** + * Performs a read transaction on the i2c bus + * + * @base Base address of twsi registers + * @slave_addr i2c bus address to read from + * @buffer buffer to read into + * @length number of bytes to read + * @return 0 for success, otherwise error + */ +static int twsi_read_data(void __iomem *base, u8 slave_addr, + u8 *buffer, unsigned int length) +{ + unsigned int curr = 0; + u64 val; + int ret; + + debug("%s(%p, 0x%x, %p, %u)\n", __func__, base, slave_addr, + buffer, length); + ret = twsi_start(base); + if (ret) { + debug("%s: start failed\n", __func__); + return ret; + } + + ret = twsi_wait(base); + if (ret) { + debug("%s: wait failed\n", __func__); + return ret; + } + + val = (u32)(slave_addr << 1) | TWSI_OP_READ | + FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_DATA) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA); + twsi_write_sw(base, val); + twsi_write_ctl(base, TWSI_CTL_ENAB); + + ret = twsi_wait(base); + if (ret) { + debug("%s: waiting for sending addr failed\n", __func__); + return ret; + } + + ret = twsi_read_status(base); + debug("%s: status: 0x%x\n", __func__, ret); + if (ret != TWSI_STAT_RXADDR_ACK) { + debug("%s: status: 0x%x\n", __func__, ret); + twsi_stop(base); + return twsi_i2c_lost_arb(ret, 0); + } + + while (curr < length) { + twsi_write_ctl(base, TWSI_CTL_ENAB | + ((curr < length - 1) ? TWSI_CTL_AAK : 0)); + + ret = twsi_wait(base); + if (ret) { + debug("%s: waiting for data failed\n", __func__); + return ret; + } + + val = twsi_read_sw(base, val); + buffer[curr++] = (u8)val; + } + + twsi_stop(base); + + return 0; +} + +/** + * Calculate the divisor values + * + * @speed Speed to set + * @m_div Pointer to M divisor + * @n_div Pointer to N divisor + * @return 0 for success, otherwise error + */ +static void twsi_calc_div(struct udevice *bus, ulong sclk, unsigned int speed, + int *m_div, int *n_div) +{ + struct octeon_twsi *twsi = dev_get_priv(bus); + int thp = twsi->data->thp; + int tclk, fsamp; + int ndiv, mdiv; + + if (twsi->data->clk_method == CLK_METHOD_OCTEON) { + tclk = sclk / (2 * (thp + 1)); + } else { + /* Refclk src in mode register defaults to 100MHz clock */ + sclk = 100000000; /* 100 Mhz */ + tclk = sclk / (thp + 2); + } + debug("%s( io_clock %lu tclk %u)\n", __func__, sclk, tclk); + + /* + * Compute the clocks M divider: + * + * TWSI freq = (core freq) / (10 x (M+1) x 2 * (thp+1) x 2^N) + * M = ((core freq) / (10 x (TWSI freq) x 2 * (thp+1) x 2^N)) - 1 + * + * For OcteonTX2 - + * TWSI freq = (core freq) / (10 x (M+1) x (thp+2) x 2^N) + * M = ((core freq) / (10 x (TWSI freq) x (thp+2) x 2^N)) - 1 + */ + for (ndiv = 0; ndiv < 8; ndiv++) { + fsamp = tclk / (1 << ndiv); + mdiv = fsamp / speed / 10; + mdiv -= 1; + if (mdiv < 16) + break; + } + + *m_div = mdiv; + *n_div = ndiv; +} + +/** + * Init I2C controller + * + * @base Base address of twsi registers + * @slave_addr I2C slave address to configure this controller to + * @return 0 for success, otherwise error + */ +static int twsi_init(void __iomem *base, int slaveaddr) +{ + u64 val; + + debug("%s (%p, 0x%x)\n", __func__, base, slaveaddr); + + val = slaveaddr << 1 | + FIELD_PREP(TWSI_SW_EOP_IA_MASK, 0) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) | + TWSI_SW_V; + twsi_write_sw(base, val); + + /* Set slave address */ + val = slaveaddr | + FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_EOP_SLAVE_ADDR) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) | + TWSI_SW_V; + twsi_write_sw(base, val); + + return 0; +} + +/** + * Transfers data over the i2c bus + * + * @bus i2c bus to transfer data over + * @msg Array of i2c messages + * @nmsgs Number of messages to send/receive + * @return 0 for success, otherwise error + */ +static int octeon_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + struct octeon_twsi *twsi = dev_get_priv(bus); + int ret; + int i; + + debug("%s: %d messages\n", __func__, nmsgs); + for (i = 0; i < nmsgs; i++, msg++) { + debug("%s: chip=0x%x, len=0x%x\n", __func__, msg->addr, + msg->len); + + if (msg->flags & I2C_M_RD) { + debug("%s: Reading data\n", __func__); + ret = twsi_read_data(twsi->base, msg->addr, + msg->buf, msg->len); + } else { + debug("%s: Writing data\n", __func__); + ret = twsi_write_data(twsi->base, msg->addr, + msg->buf, msg->len); + } + if (ret) { + debug("%s: error sending\n", __func__); + return -EREMOTEIO; + } + } + + return 0; +} + +/** + * Set I2C bus speed + * + * @bus i2c bus to transfer data over + * @speed Speed in Hz to set + * @return 0 for success, otherwise error + */ +static int octeon_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct octeon_twsi *twsi = dev_get_priv(bus); + int m_div, n_div; + ulong clk_rate; + u64 val; + + debug("%s(%p, %u)\n", __func__, bus, speed); + + clk_rate = clk_get_rate(&twsi->clk); + if (IS_ERR_VALUE(clk_rate)) + return -EINVAL; + + twsi_calc_div(bus, clk_rate, speed, &m_div, &n_div); + if (m_div >= 16) + return -1; + + val = (u32)(((m_div & 0xf) << 3) | ((n_div & 0x7) << 0)) | + FIELD_PREP(TWSI_SW_EOP_IA_MASK, TWSI_CLKCTL) | + FIELD_PREP(TWSI_SW_OP_MASK, TWSI_SW_EOP_IA) | + TWSI_SW_V; + /* Only init non-slave ports */ + writeq(val, twsi->base + TWSI_SW_TWSI); + + debug("%s: Wrote 0x%llx to sw_twsi\n", __func__, val); + return 0; +} + +/** + * Driver probe function + * + * @dev I2C device to probe + * @return 0 for success, otherwise error + */ +static int octeon_i2c_probe(struct udevice *dev) +{ + struct octeon_twsi *twsi = dev_get_priv(dev); + u32 i2c_slave_addr; + int ret; + + twsi->data = (const struct octeon_i2c_data *)dev_get_driver_data(dev); + + if (twsi->data->probe == PROBE_PCI) { + pci_dev_t bdf = dm_pci_get_bdf(dev); + + debug("TWSI PCI device: %x\n", bdf); + dev->req_seq = PCI_FUNC(bdf); + + twsi->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + } else { + twsi->base = dev_remap_addr(dev); + } + twsi->base += twsi->data->reg_offs; + + i2c_slave_addr = dev_read_u32_default(dev, "i2c-sda-hold-time-ns", + CONFIG_SYS_I2C_OCTEON_SLAVE_ADDR); + + ret = clk_get_by_index(dev, 0, &twsi->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&twsi->clk); + if (ret) + return ret; + + debug("TWSI bus %d at %p\n", dev->seq, twsi->base); + + /* Start with standard speed, real speed set via DT or cmd */ + return twsi_init(twsi->base, i2c_slave_addr); +} + +static const struct dm_i2c_ops octeon_i2c_ops = { + .xfer = octeon_i2c_xfer, + .set_bus_speed = octeon_i2c_set_bus_speed, +}; + +static const struct octeon_i2c_data i2c_octeon_data = { + .probe = PROBE_DT, + .reg_offs = 0x0000, + .thp = 3, + .clk_method = CLK_METHOD_OCTEON, +}; + +static const struct octeon_i2c_data i2c_octeontx_data = { + .probe = PROBE_PCI, + .reg_offs = 0x8000, + .thp = 3, + .clk_method = CLK_METHOD_OCTEON, +}; + +static const struct octeon_i2c_data i2c_octeontx2_data = { + .probe = PROBE_PCI, + .reg_offs = 0x8000, + .thp = 24, + .clk_method = CLK_METHOD_OCTEONTX2, +}; + +static const struct udevice_id octeon_i2c_ids[] = { + { .compatible = "cavium,octeon-7890-twsi", + .data = (ulong)&i2c_octeon_data }, + { .compatible = "cavium,thunder-8890-twsi", + .data = (ulong)&i2c_octeontx_data }, + { .compatible = "cavium,thunder2-99xx-twsi", + .data = (ulong)&i2c_octeontx2_data }, + { } +}; + +U_BOOT_DRIVER(octeon_pci_twsi) = { + .name = "i2c_octeon", + .id = UCLASS_I2C, + .of_match = octeon_i2c_ids, + .probe = octeon_i2c_probe, + .priv_auto_alloc_size = sizeof(struct octeon_twsi), + .ops = &octeon_i2c_ops, +}; + +static struct pci_device_id octeon_twsi_supported[] = { + { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_TWSI), + .driver_data = (ulong)&i2c_octeontx2_data }, + { }, +}; + +U_BOOT_PCI_DEVICE(octeon_pci_twsi, octeon_twsi_supported); diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index ada8f4095e..2f60911549 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -8,7 +8,9 @@ #include <dm.h> #include <i2c.h> #include <log.h> +#include <regmap.h> #include <reset.h> +#include <syscon.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -154,6 +156,7 @@ struct stm32_i2c_spec { * @fall_time: Fall time (ns) * @dnf: Digital filter coefficient (0-16) * @analog_filter: Analog filter delay (On/Off) + * @fmp_clr_offset: Fast Mode Plus clear register offset from set register */ struct stm32_i2c_setup { u32 speed_freq; @@ -162,6 +165,7 @@ struct stm32_i2c_setup { u32 fall_time; u8 dnf; bool analog_filter; + u32 fmp_clr_offset; }; /** @@ -181,11 +185,26 @@ struct stm32_i2c_timings { u8 scll; }; +/** + * struct stm32_i2c_priv - private data of the controller + * @regs: I2C registers address + * @clk: hw i2c clock + * @setup: I2C timing setup parameters + * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+ + * @regmap: holds SYSCFG phandle for Fast Mode Plus bit + * @regmap_sreg: register address for setting Fast Mode Plus bits + * @regmap_creg: register address for clearing Fast Mode Plus bits + * @regmap_mask: mask for Fast Mode Plus bits + */ struct stm32_i2c_priv { struct stm32_i2c_regs *regs; struct clk clk; struct stm32_i2c_setup *setup; u32 speed; + struct regmap *regmap; + u32 regmap_sreg; + u32 regmap_creg; + u32 regmap_mask; }; static const struct stm32_i2c_spec i2c_specs[] = { @@ -237,6 +256,14 @@ static const struct stm32_i2c_setup stm32f7_setup = { .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, }; +static const struct stm32_i2c_setup stm32mp15_setup = { + .rise_time = STM32_I2C_RISE_TIME_DEFAULT, + .fall_time = STM32_I2C_FALL_TIME_DEFAULT, + .dnf = STM32_I2C_DNF_DEFAULT, + .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, + .fmp_clr_offset = 0x40, +}; + static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) { struct stm32_i2c_regs *regs = i2c_priv->regs; @@ -761,6 +788,29 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, return 0; } +static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv) +{ + int ret; + bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE; + + /* Optional */ + if (IS_ERR_OR_NULL(i2c_priv->regmap)) + return 0; + + if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg) + ret = regmap_update_bits(i2c_priv->regmap, + i2c_priv->regmap_sreg, + i2c_priv->regmap_mask, + enable ? i2c_priv->regmap_mask : 0); + else + ret = regmap_write(i2c_priv->regmap, + enable ? i2c_priv->regmap_sreg : + i2c_priv->regmap_creg, + i2c_priv->regmap_mask); + + return ret; +} + static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) { struct stm32_i2c_regs *regs = i2c_priv->regs; @@ -775,6 +825,11 @@ static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) /* Disable I2C */ clrbits_le32(®s->cr1, STM32_I2C_CR1_PE); + /* Setup Fast mode plus if necessary */ + ret = stm32_i2c_write_fm_plus_bits(i2c_priv); + if (ret) + return ret; + /* Timing settings */ timing |= STM32_I2C_TIMINGR_PRESC(t.presc); timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel); @@ -850,6 +905,7 @@ static int stm32_ofdata_to_platdata(struct udevice *dev) { struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); u32 rise_time, fall_time; + int ret; i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev); if (!i2c_priv->setup) @@ -863,6 +919,22 @@ static int stm32_ofdata_to_platdata(struct udevice *dev) if (fall_time) i2c_priv->setup->fall_time = fall_time; + /* Optional */ + i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev, + "st,syscfg-fmp"); + if (!IS_ERR(i2c_priv->regmap)) { + u32 fmp[3]; + + ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3); + if (ret) + return ret; + + i2c_priv->regmap_sreg = fmp[1]; + i2c_priv->regmap_creg = fmp[1] + + i2c_priv->setup->fmp_clr_offset; + i2c_priv->regmap_mask = fmp[2]; + } + return 0; } @@ -873,6 +945,7 @@ static const struct dm_i2c_ops stm32_i2c_ops = { static const struct udevice_id stm32_i2c_of_match[] = { { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup }, + { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup }, {} }; diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index dc3dffb657..5cdf3c506f 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -210,7 +210,7 @@ static int bcm2835_sdhci_probe(struct udevice *dev) priv->last_write = 0; host->name = dev->name; - host->ioaddr = (void *)base; + host->ioaddr = (void *)(uintptr_t)base; host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT; host->max_clk = emmc_freq; diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 19b9375ee2..a5747a25ab 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -1263,6 +1263,7 @@ struct buffer_location { * can be enabled at once */ static struct buffer_location buffer_loc; +static int buffer_loc_init; /* * Page table entries are set to 1MB, or multiples of 1MB @@ -5247,40 +5248,44 @@ static int mvpp2_base_probe(struct udevice *dev) * be active. Make this area DMA-safe by disabling the D-cache */ - /* Align buffer area for descs and rx_buffers to 1MiB */ - bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); - mmu_set_region_dcache_behaviour((unsigned long)bd_space, - BD_SPACE, DCACHE_OFF); - - buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space; - size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE; - - buffer_loc.tx_descs = - (struct mvpp2_tx_desc *)((unsigned long)bd_space + size); - size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE; + if (!buffer_loc_init) { + /* Align buffer area for descs and rx_buffers to 1MiB */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((unsigned long)bd_space, + BD_SPACE, DCACHE_OFF); + + buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space; + size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE; + + buffer_loc.tx_descs = + (struct mvpp2_tx_desc *)((unsigned long)bd_space + size); + size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE; + + buffer_loc.rx_descs = + (struct mvpp2_rx_desc *)((unsigned long)bd_space + size); + size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE; + + for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { + buffer_loc.bm_pool[i] = + (unsigned long *)((unsigned long)bd_space + size); + if (priv->hw_version == MVPP21) + size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32); + else + size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64); + } - buffer_loc.rx_descs = - (struct mvpp2_rx_desc *)((unsigned long)bd_space + size); - size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE; + for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) { + buffer_loc.rx_buffer[i] = + (unsigned long *)((unsigned long)bd_space + size); + size += RX_BUFFER_SIZE; + } - for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { - buffer_loc.bm_pool[i] = - (unsigned long *)((unsigned long)bd_space + size); - if (priv->hw_version == MVPP21) - size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32); - else - size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64); - } + /* Clear the complete area so that all descriptors are cleared */ + memset(bd_space, 0, size); - for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) { - buffer_loc.rx_buffer[i] = - (unsigned long *)((unsigned long)bd_space + size); - size += RX_BUFFER_SIZE; + buffer_loc_init = 1; } - /* Clear the complete area so that all descriptors are cleared */ - memset(bd_space, 0, size); - /* Save base addresses for later use */ priv->base = (void *)devfdt_get_addr_index(dev, 0); if (IS_ERR(priv->base)) diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 6a9bc49978..fa29d69e85 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -22,6 +22,8 @@ * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz> */ +#define LOG_CATEGORY UCLASS_PCI + #include <common.h> #include <bios_emul.h> #include <bootstage.h> @@ -344,7 +346,16 @@ int vbe_setup_video_priv(struct vesa_mode_info *vesa, default: return -EPROTONOSUPPORT; } - plat->base = vesa->phys_base_ptr; + + /* Use double buffering if enabled */ + if (IS_ENABLED(CONFIG_VIDEO_COPY)) { + if (!plat->base) + return log_msg_ret("copy", -ENFILE); + plat->copy_base = vesa->phys_base_ptr; + } else { + plat->base = vesa->phys_base_ptr; + } + log_debug("base = %lx, copy_base = %lx\n", plat->base, plat->copy_base); plat->size = vesa->bytes_per_scanline * vesa->y_resolution; return 0; @@ -372,6 +383,15 @@ int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void)) ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat); if (ret) { + if (ret == -ENFILE) { + /* + * See video-uclass.c for how to set up reserved memory + * in your video driver + */ + log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n", + dev->driver->name); + } + debug("No video mode configured\n"); return ret; } diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index edb3f0f538..61eb468cde 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -47,6 +47,12 @@ config PWM_SANDBOX useful. The PWM can be enabled but is not connected to any outputs so this is not very useful. +config PWM_SIFIVE + bool "Enable support for SiFive PWM" + depends on DM_PWM + help + This PWM is found SiFive's FU540 and other SoCs. + config PWM_TEGRA bool "Enable support for the Tegra PWM" depends on DM_PWM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 2c3a069006..0f4e84b04d 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,5 +15,6 @@ obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o obj-$(CONFIG_PWM_MTK) += pwm-mtk.o obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o obj-$(CONFIG_PWM_SANDBOX) += sandbox_pwm.o +obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o obj-$(CONFIG_PWM_SUNXI) += sunxi_pwm.o diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c new file mode 100644 index 0000000000..77bc659fef --- /dev/null +++ b/drivers/pwm/pwm-sifive.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 SiFive, Inc + * For SiFive's PWM IP block documentation please refer Chapter 14 of + * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf + * + * Limitations: + * - When changing both duty cycle and period, we cannot prevent in + * software that the output might produce a period with mixed + * settings (new period length and old duty cycle). + * - The hardware cannot generate a 100% duty cycle. + * - The hardware generates only inverted output. + */ + +#include <common.h> +#include <clk.h> +#include <div64.h> +#include <dm.h> +#include <pwm.h> +#include <regmap.h> +#include <linux/io.h> +#include <linux/log2.h> +#include <linux/bitfield.h> + +/* PWMCFG fields */ +#define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0) +#define PWM_SIFIVE_PWMCFG_STICKY BIT(8) +#define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9) +#define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10) +#define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12) +#define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13) +#define PWM_SIFIVE_PWMCFG_CENTER BIT(16) +#define PWM_SIFIVE_PWMCFG_GANG BIT(24) +#define PWM_SIFIVE_PWMCFG_IP BIT(28) + +/* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */ +#define PWM_SIFIVE_SIZE_PWMCMP 4 +#define PWM_SIFIVE_CMPWIDTH 16 + +DECLARE_GLOBAL_DATA_PTR; + +struct pwm_sifive_regs { + unsigned long cfg; + unsigned long cnt; + unsigned long pwms; + unsigned long cmp0; +}; + +struct pwm_sifive_data { + struct pwm_sifive_regs regs; +}; + +struct pwm_sifive_priv { + void __iomem *base; + ulong freq; + const struct pwm_sifive_data *data; +}; + +static int pwm_sifive_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct pwm_sifive_priv *priv = dev_get_priv(dev); + const struct pwm_sifive_regs *regs = &priv->data->regs; + unsigned long scale_pow; + unsigned long long num; + u32 scale, val = 0, frac; + + debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns); + + /* + * The PWM unit is used with pwmzerocmp=0, so the only way to modify the + * period length is using pwmscale which provides the number of bits the + * counter is shifted before being feed to the comparators. A period + * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks. + * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period + */ + scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000); + scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf); + val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale); + + /* + * The problem of output producing mixed setting as mentioned at top, + * occurs here. To minimize the window for this problem, we are + * calculating the register values first and then writing them + * consecutively + */ + num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH); + frac = DIV_ROUND_CLOSEST_ULL(num, period_ns); + frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1); + + writel(val, priv->base + regs->cfg); + writel(frac, priv->base + regs->cmp0 + channel * + PWM_SIFIVE_SIZE_PWMCMP); + + return 0; +} + +static int pwm_sifive_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct pwm_sifive_priv *priv = dev_get_priv(dev); + const struct pwm_sifive_regs *regs = &priv->data->regs; + u32 val; + + debug("%s: Enable '%s'\n", __func__, dev->name); + + if (enable) { + val = readl(priv->base + regs->cfg); + val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS; + writel(val, priv->base + regs->cfg); + } else { + writel(0, priv->base + regs->cmp0 + channel * + PWM_SIFIVE_SIZE_PWMCMP); + } + + return 0; +} + +static int pwm_sifive_ofdata_to_platdata(struct udevice *dev) +{ + struct pwm_sifive_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static int pwm_sifive_probe(struct udevice *dev) +{ + struct pwm_sifive_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret = 0; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + debug("%s get clock fail!\n", __func__); + return -EINVAL; + } + + priv->freq = clk_get_rate(&clk); + priv->data = (struct pwm_sifive_data *)dev_get_driver_data(dev); + + return 0; +} + +static const struct pwm_ops pwm_sifive_ops = { + .set_config = pwm_sifive_set_config, + .set_enable = pwm_sifive_set_enable, +}; + +static const struct pwm_sifive_data pwm_data = { + .regs = { + .cfg = 0x00, + .cnt = 0x08, + .pwms = 0x10, + .cmp0 = 0x20, + }, +}; + +static const struct udevice_id pwm_sifive_ids[] = { + { .compatible = "sifive,pwm0", .data = (ulong)&pwm_data}, + { } +}; + +U_BOOT_DRIVER(pwm_sifive) = { + .name = "pwm_sifive", + .id = UCLASS_PWM, + .of_match = pwm_sifive_ids, + .ops = &pwm_sifive_ops, + .ofdata_to_platdata = pwm_sifive_ofdata_to_platdata, + .probe = pwm_sifive_probe, + .priv_auto_alloc_size = sizeof(struct pwm_sifive_priv), +}; diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c index a010af411b..7f78ff83cb 100644 --- a/drivers/rtc/i2c_rtc_emul.c +++ b/drivers/rtc/i2c_rtc_emul.c @@ -197,7 +197,8 @@ static int sandbox_i2c_rtc_xfer(struct udevice *emul, struct i2c_msg *msg, /* Write the register */ memcpy(plat->reg + offset, ptr, len); - if (offset == REG_RESET) + /* If the reset register was written to, do reset. */ + if (offset <= REG_RESET && REG_RESET < offset + len) reset_time(emul); } } diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c index c423960b34..88ff8c52c3 100644 --- a/drivers/rtc/pcf2127.c +++ b/drivers/rtc/pcf2127.c @@ -23,8 +23,7 @@ #define PCF2127_REG_MO 0x08 #define PCF2127_REG_YR 0x09 -static int pcf2127_read_reg(struct udevice *dev, uint offset, - u8 *buffer, int len) +static int pcf2127_rtc_read(struct udevice *dev, uint offset, u8 *buffer, uint len) { struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); struct i2c_msg msg; @@ -44,6 +43,12 @@ static int pcf2127_read_reg(struct udevice *dev, uint offset, return dm_i2c_xfer(dev, &msg, 1); } +static int pcf2127_rtc_write(struct udevice *dev, uint offset, + const u8 *buffer, uint len) +{ + return dm_i2c_write(dev, offset, buffer, len); +} + static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm) { uchar buf[7] = {0}; @@ -73,7 +78,7 @@ static int pcf2127_rtc_get(struct udevice *dev, struct rtc_time *tm) int ret = 0; uchar buf[10] = { PCF2127_REG_CTRL1 }; - ret = pcf2127_read_reg(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)); + ret = pcf2127_rtc_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)); if (ret < 0) return ret; @@ -110,6 +115,8 @@ static const struct rtc_ops pcf2127_rtc_ops = { .get = pcf2127_rtc_get, .set = pcf2127_rtc_set, .reset = pcf2127_rtc_reset, + .read = pcf2127_rtc_read, + .write = pcf2127_rtc_write, }; static const struct udevice_id pcf2127_rtc_ids[] = { diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c index 926cca234e..8035f7fe9c 100644 --- a/drivers/rtc/rtc-uclass.c +++ b/drivers/rtc/rtc-uclass.c @@ -40,24 +40,75 @@ int dm_rtc_reset(struct udevice *dev) return ops->reset(dev); } -int rtc_read8(struct udevice *dev, unsigned int reg) +int dm_rtc_read(struct udevice *dev, unsigned int reg, u8 *buf, unsigned int len) { struct rtc_ops *ops = rtc_get_ops(dev); assert(ops); + if (ops->read) + return ops->read(dev, reg, buf, len); if (!ops->read8) return -ENOSYS; - return ops->read8(dev, reg); + while (len--) { + int ret = ops->read8(dev, reg++); + + if (ret < 0) + return ret; + *buf++ = ret; + } + return 0; } -int rtc_write8(struct udevice *dev, unsigned int reg, int val) +int dm_rtc_write(struct udevice *dev, unsigned int reg, + const u8 *buf, unsigned int len) { struct rtc_ops *ops = rtc_get_ops(dev); assert(ops); + if (ops->write) + return ops->write(dev, reg, buf, len); if (!ops->write8) return -ENOSYS; - return ops->write8(dev, reg, val); + while (len--) { + int ret = ops->write8(dev, reg++, *buf++); + + if (ret < 0) + return ret; + } + return 0; +} + +int rtc_read8(struct udevice *dev, unsigned int reg) +{ + struct rtc_ops *ops = rtc_get_ops(dev); + + assert(ops); + if (ops->read8) + return ops->read8(dev, reg); + if (ops->read) { + u8 buf[1]; + int ret = ops->read(dev, reg, buf, 1); + + if (ret < 0) + return ret; + return buf[0]; + } + return -ENOSYS; +} + +int rtc_write8(struct udevice *dev, unsigned int reg, int val) +{ + struct rtc_ops *ops = rtc_get_ops(dev); + + assert(ops); + if (ops->write8) + return ops->write8(dev, reg, val); + if (ops->write) { + u8 buf[1] = { val }; + + return ops->write(dev, reg, buf, 1); + } + return -ENOSYS; } int rtc_read16(struct udevice *dev, unsigned int reg, u16 *valuep) diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c index b08d758a74..77065e49c7 100644 --- a/drivers/rtc/sandbox_rtc.c +++ b/drivers/rtc/sandbox_rtc.c @@ -14,55 +14,38 @@ static int sandbox_rtc_get(struct udevice *dev, struct rtc_time *time) { - time->tm_sec = dm_i2c_reg_read(dev, REG_SEC); - if (time->tm_sec < 0) - return time->tm_sec; - time->tm_min = dm_i2c_reg_read(dev, REG_MIN); - if (time->tm_min < 0) - return time->tm_min; - time->tm_hour = dm_i2c_reg_read(dev, REG_HOUR); - if (time->tm_hour < 0) - return time->tm_hour; - time->tm_mday = dm_i2c_reg_read(dev, REG_MDAY); - if (time->tm_mday < 0) - return time->tm_mday; - time->tm_mon = dm_i2c_reg_read(dev, REG_MON); - if (time->tm_mon < 0) - return time->tm_mon; - time->tm_year = dm_i2c_reg_read(dev, REG_YEAR); - if (time->tm_year < 0) - return time->tm_year; - time->tm_year += 1900; - time->tm_wday = dm_i2c_reg_read(dev, REG_WDAY); - if (time->tm_wday < 0) - return time->tm_wday; + u8 buf[7]; + int ret; + + ret = dm_i2c_read(dev, REG_SEC, buf, sizeof(buf)); + if (ret < 0) + return ret; + + time->tm_sec = buf[REG_SEC - REG_SEC]; + time->tm_min = buf[REG_MIN - REG_SEC]; + time->tm_hour = buf[REG_HOUR - REG_SEC]; + time->tm_mday = buf[REG_MDAY - REG_SEC]; + time->tm_mon = buf[REG_MON - REG_SEC]; + time->tm_year = buf[REG_YEAR - REG_SEC] + 1900; + time->tm_wday = buf[REG_WDAY - REG_SEC]; return 0; } static int sandbox_rtc_set(struct udevice *dev, const struct rtc_time *time) { + u8 buf[7]; int ret; - ret = dm_i2c_reg_write(dev, REG_SEC, time->tm_sec); - if (ret < 0) - return ret; - ret = dm_i2c_reg_write(dev, REG_MIN, time->tm_min); - if (ret < 0) - return ret; - ret = dm_i2c_reg_write(dev, REG_HOUR, time->tm_hour); - if (ret < 0) - return ret; - ret = dm_i2c_reg_write(dev, REG_MDAY, time->tm_mday); - if (ret < 0) - return ret; - ret = dm_i2c_reg_write(dev, REG_MON, time->tm_mon); - if (ret < 0) - return ret; - ret = dm_i2c_reg_write(dev, REG_YEAR, time->tm_year - 1900); - if (ret < 0) - return ret; - ret = dm_i2c_reg_write(dev, REG_WDAY, time->tm_wday); + buf[REG_SEC - REG_SEC] = time->tm_sec; + buf[REG_MIN - REG_SEC] = time->tm_min; + buf[REG_HOUR - REG_SEC] = time->tm_hour; + buf[REG_MDAY - REG_SEC] = time->tm_mday; + buf[REG_MON - REG_SEC] = time->tm_mon; + buf[REG_YEAR - REG_SEC] = time->tm_year - 1900; + buf[REG_WDAY - REG_SEC] = time->tm_wday; + + ret = dm_i2c_write(dev, REG_SEC, buf, sizeof(buf)); if (ret < 0) return ret; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 0cf13adc7d..89ad603d88 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -22,6 +22,37 @@ config BACKLIGHT This provides backlight uclass driver that enables basic panel backlight support. +config VIDEO_PCI_DEFAULT_FB_SIZE + hex "Default framebuffer size to use if no drivers request it" + depends on DM_VIDEO + default 0x1000000 if X86 && PCI + default 0 if !(X86 && PCI) + help + Generally, video drivers request the amount of memory they need for + the frame buffer when they are bound, by setting the size field in + struct video_uc_platdata. That memory is then reserved for use after + relocation. But PCI drivers cannot be bound before relocation unless + they are mentioned in the devicetree. + + With this value set appropriately, it is possible for PCI video + devices to have a framebuffer allocated by U-Boot. + + Note: the framebuffer needs to be large enough to store all pixels at + maximum resolution. For example, at 1920 x 1200 with 32 bits per + pixel, 2560 * 1600 * 32 / 8 = 0xfa0000 bytes are needed. + +config VIDEO_COPY + bool "Enable copying the frame buffer to a hardware copy" + depends on DM_VIDEO + help + On some machines (e.g. x86), reading from the frame buffer is very + slow because it is uncached. To improve performance, this feature + allows the frame buffer to be kept in cached memory (allocated by + U-Boot) and then copied to the hardware frame-buffer as needed. + + To use this, your video driver must set @copy_base in + struct video_uc_platdata. + config BACKLIGHT_PWM bool "Generic PWM based Backlight Driver" depends on BACKLIGHT && DM_PWM diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c index 8e8fe9d9b3..df6a761d2d 100644 --- a/drivers/video/broadwell_igd.c +++ b/drivers/video/broadwell_igd.c @@ -664,6 +664,7 @@ static int broadwell_igd_probe(struct udevice *dev) struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); bool is_broadwell; + ulong fbbase; int ret; if (!ll_boot_init()) { @@ -690,7 +691,8 @@ static int broadwell_igd_probe(struct udevice *dev) return ret; /* Use write-combining for the graphics memory, 256MB */ - ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20); + fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base; + ret = mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20); if (!ret) ret = mtrr_commit(true); if (ret && ret != -ENOSYS) { @@ -752,6 +754,17 @@ static int broadwell_igd_ofdata_to_platdata(struct udevice *dev) return 0; } +static int broadwell_igd_bind(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + + /* Set the maximum supported resolution */ + uc_plat->size = 2560 * 1600 * 4; + log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + + return 0; +} + static const struct video_ops broadwell_igd_ops = { }; @@ -766,6 +779,7 @@ U_BOOT_DRIVER(broadwell_igd) = { .of_match = broadwell_igd_ids, .ops = &broadwell_igd_ops, .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata, + .bind = broadwell_igd_bind, .probe = broadwell_igd_probe, .priv_auto_alloc_size = sizeof(struct broadwell_igd_priv), .platdata_auto_alloc_size = sizeof(struct broadwell_igd_plat), diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index c3f7ef8add..04f022491e 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -16,8 +16,9 @@ static int console_normal_set_row(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); - void *line; + void *line, *end; int pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize; + int ret; int i; line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * vid_priv->line_length; @@ -28,6 +29,7 @@ static int console_normal_set_row(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } case VIDEO_BPP16: @@ -36,6 +38,7 @@ static int console_normal_set_row(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } case VIDEO_BPP32: @@ -44,11 +47,15 @@ static int console_normal_set_row(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } default: return -ENOSYS; } + ret = vidconsole_sync_copy(dev, line, end); + if (ret) + return ret; return 0; } @@ -59,10 +66,15 @@ static int console_normal_move_rows(struct udevice *dev, uint rowdst, struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); void *dst; void *src; + int size; + int ret; dst = vid_priv->fb + rowdst * VIDEO_FONT_HEIGHT * vid_priv->line_length; src = vid_priv->fb + rowsrc * VIDEO_FONT_HEIGHT * vid_priv->line_length; - memmove(dst, src, VIDEO_FONT_HEIGHT * vid_priv->line_length * count); + size = VIDEO_FONT_HEIGHT * vid_priv->line_length * count; + ret = vidconsole_memmove(dev, dst, src, size); + if (ret) + return ret; return 0; } @@ -74,8 +86,13 @@ static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y, struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); int i, row; - void *line = vid_priv->fb + y * vid_priv->line_length + + void *start; + void *line; + int ret; + + start = vid_priv->fb + y * vid_priv->line_length + VID_TO_PIXEL(x_frac) * VNBYTES(vid_priv->bpix); + line = start; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; @@ -126,6 +143,9 @@ static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y, } line += vid_priv->line_length; } + ret = vidconsole_sync_copy(dev, start, line); + if (ret) + return ret; return VID_TO_POS(VIDEO_FONT_WIDTH); } diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index b485255598..36c8d0609d 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -15,11 +15,13 @@ static int console_set_row_1(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); int pbytes = VNBYTES(vid_priv->bpix); - void *line; + void *start, *line; int i, j; + int ret; - line = vid_priv->fb + vid_priv->line_length - + start = vid_priv->fb + vid_priv->line_length - (row + 1) * VIDEO_FONT_HEIGHT * pbytes; + line = start; for (j = 0; j < vid_priv->ysize; j++) { switch (vid_priv->bpix) { case VIDEO_BPP8: @@ -51,6 +53,9 @@ static int console_set_row_1(struct udevice *dev, uint row, int clr) } line += vid_priv->line_length; } + ret = vidconsole_sync_copy(dev, start, line); + if (ret) + return ret; return 0; } @@ -59,10 +64,10 @@ static int console_move_rows_1(struct udevice *dev, uint rowdst, uint rowsrc, uint count) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + int pbytes = VNBYTES(vid_priv->bpix); void *dst; void *src; - int pbytes = VNBYTES(vid_priv->bpix); - int j; + int j, ret; dst = vid_priv->fb + vid_priv->line_length - (rowdst + count) * VIDEO_FONT_HEIGHT * pbytes; @@ -70,7 +75,10 @@ static int console_move_rows_1(struct udevice *dev, uint rowdst, uint rowsrc, (rowsrc + count) * VIDEO_FONT_HEIGHT * pbytes; for (j = 0; j < vid_priv->ysize; j++) { - memmove(dst, src, VIDEO_FONT_HEIGHT * pbytes * count); + ret = vidconsole_memmove(dev, dst, src, + VIDEO_FONT_HEIGHT * pbytes * count); + if (ret) + return ret; src += vid_priv->line_length; dst += vid_priv->line_length; } @@ -83,14 +91,16 @@ static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); + uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT; int pbytes = VNBYTES(vid_priv->bpix); - int i, col; + int i, col, x, linenum, ret; int mask = 0x80; - void *line; - uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT; + void *start, *line; - line = vid_priv->fb + (VID_TO_PIXEL(x_frac) + 1) * - vid_priv->line_length - (y + 1) * pbytes; + linenum = VID_TO_PIXEL(x_frac) + 1; + x = y + 1; + start = vid_priv->fb + linenum * vid_priv->line_length - x * pbytes; + line = start; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; @@ -135,6 +145,10 @@ static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) line += vid_priv->line_length; mask >>= 1; } + /* We draw backwards from 'start, so account for the first line */ + ret = vidconsole_sync_copy(dev, start - vid_priv->line_length, line); + if (ret) + return ret; return VID_TO_POS(VIDEO_FONT_WIDTH); } @@ -143,12 +157,13 @@ static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) static int console_set_row_2(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); - void *line; + void *start, *line, *end; int pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize; - int i; + int i, ret; - line = vid_priv->fb + vid_priv->ysize * vid_priv->line_length - + start = vid_priv->fb + vid_priv->ysize * vid_priv->line_length - (row + 1) * VIDEO_FONT_HEIGHT * vid_priv->line_length; + line = start; switch (vid_priv->bpix) { case VIDEO_BPP8: if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { @@ -156,6 +171,7 @@ static int console_set_row_2(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } case VIDEO_BPP16: @@ -164,6 +180,7 @@ static int console_set_row_2(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } case VIDEO_BPP32: @@ -172,11 +189,15 @@ static int console_set_row_2(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } default: return -ENOSYS; } + ret = vidconsole_sync_copy(dev, start, end); + if (ret) + return ret; return 0; } @@ -194,7 +215,8 @@ static int console_move_rows_2(struct udevice *dev, uint rowdst, uint rowsrc, vid_priv->line_length; src = end - (rowsrc + count) * VIDEO_FONT_HEIGHT * vid_priv->line_length; - memmove(dst, src, VIDEO_FONT_HEIGHT * vid_priv->line_length * count); + vidconsole_memmove(dev, dst, src, + VIDEO_FONT_HEIGHT * vid_priv->line_length * count); return 0; } @@ -204,16 +226,16 @@ static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); - int i, row; - void *line; + int pbytes = VNBYTES(vid_priv->bpix); + int i, row, x, linenum, ret; + void *start, *line; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; - - line = vid_priv->fb + (vid_priv->ysize - y - 1) * - vid_priv->line_length + - (vid_priv->xsize - VID_TO_PIXEL(x_frac) - - VIDEO_FONT_WIDTH - 1) * VNBYTES(vid_priv->bpix); + linenum = vid_priv->ysize - y - 1; + x = vid_priv->xsize - VID_TO_PIXEL(x_frac) - 1; + start = vid_priv->fb + linenum * vid_priv->line_length + x * pbytes; + line = start; for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row; @@ -261,6 +283,10 @@ static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) } line -= vid_priv->line_length; } + /* Add 4 bytes to allow for the first pixel writen */ + ret = vidconsole_sync_copy(dev, start + 4, line); + if (ret) + return ret; return VID_TO_POS(VIDEO_FONT_WIDTH); } @@ -269,10 +295,11 @@ static int console_set_row_3(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); int pbytes = VNBYTES(vid_priv->bpix); - void *line; - int i, j; + void *start, *line; + int i, j, ret; - line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * pbytes; + start = vid_priv->fb + row * VIDEO_FONT_HEIGHT * pbytes; + line = start; for (j = 0; j < vid_priv->ysize; j++) { switch (vid_priv->bpix) { case VIDEO_BPP8: @@ -304,6 +331,9 @@ static int console_set_row_3(struct udevice *dev, uint row, int clr) } line += vid_priv->line_length; } + ret = vidconsole_sync_copy(dev, start, line); + if (ret) + return ret; return 0; } @@ -312,16 +342,19 @@ static int console_move_rows_3(struct udevice *dev, uint rowdst, uint rowsrc, uint count) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + int pbytes = VNBYTES(vid_priv->bpix); void *dst; void *src; - int pbytes = VNBYTES(vid_priv->bpix); - int j; + int j, ret; dst = vid_priv->fb + rowdst * VIDEO_FONT_HEIGHT * pbytes; src = vid_priv->fb + rowsrc * VIDEO_FONT_HEIGHT * pbytes; for (j = 0; j < vid_priv->ysize; j++) { - memmove(dst, src, VIDEO_FONT_HEIGHT * pbytes * count); + ret = vidconsole_memmove(dev, dst, src, + VIDEO_FONT_HEIGHT * pbytes * count); + if (ret) + return ret; src += vid_priv->line_length; dst += vid_priv->line_length; } @@ -334,17 +367,17 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch) struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); + uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT; int pbytes = VNBYTES(vid_priv->bpix); - int i, col; + int i, col, x, ret; int mask = 0x80; - void *line = vid_priv->fb + - (vid_priv->ysize - VID_TO_PIXEL(x_frac) - 1) * - vid_priv->line_length + y * pbytes; - uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT; + void *start, *line; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; - + x = vid_priv->ysize - VID_TO_PIXEL(x_frac) - 1; + start = vid_priv->fb + x * vid_priv->line_length + y * pbytes; + line = start; for (col = 0; col < VIDEO_FONT_HEIGHT; col++) { switch (vid_priv->bpix) { case VIDEO_BPP8: @@ -386,6 +419,10 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch) line -= vid_priv->line_length; mask >>= 1; } + /* Add a line to allow for the first pixels writen */ + ret = vidconsole_sync_copy(dev, start + vid_priv->line_length, line); + if (ret) + return ret; return VID_TO_POS(VIDEO_FONT_WIDTH); } diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index 5f7f03904b..22b2ea7191 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -127,9 +127,9 @@ static int console_truetype_set_row(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); struct console_tt_priv *priv = dev_get_priv(dev); - void *line; + void *end, *line; int pixels = priv->font_size * vid_priv->line_length; - int i; + int i, ret; line = vid_priv->fb + row * priv->font_size * vid_priv->line_length; switch (vid_priv->bpix) { @@ -139,6 +139,7 @@ static int console_truetype_set_row(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } #endif @@ -148,6 +149,7 @@ static int console_truetype_set_row(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } #endif @@ -157,12 +159,16 @@ static int console_truetype_set_row(struct udevice *dev, uint row, int clr) for (i = 0; i < pixels; i++) *dst++ = clr; + end = dst; break; } #endif default: return -ENOSYS; } + ret = vidconsole_sync_copy(dev, line, end); + if (ret) + return ret; return 0; } @@ -174,11 +180,14 @@ static int console_truetype_move_rows(struct udevice *dev, uint rowdst, struct console_tt_priv *priv = dev_get_priv(dev); void *dst; void *src; - int i, diff; + int i, diff, ret; dst = vid_priv->fb + rowdst * priv->font_size * vid_priv->line_length; src = vid_priv->fb + rowsrc * priv->font_size * vid_priv->line_length; - memmove(dst, src, priv->font_size * vid_priv->line_length * count); + ret = vidconsole_memmove(dev, dst, src, priv->font_size * + vid_priv->line_length * count); + if (ret) + return ret; /* Scroll up our position history */ diff = (rowsrc - rowdst) * priv->font_size; @@ -203,8 +212,8 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, struct pos_info *pos; u8 *bits, *data; int advance; - void *line; - int row; + void *start, *end, *line; + int row, ret; /* First get some basic metrics about this character */ stbtt_GetCodepointHMetrics(font, ch, &advance, &lsb); @@ -253,11 +262,12 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, /* Figure out where to write the character in the frame buffer */ bits = data; - line = vid_priv->fb + y * vid_priv->line_length + + start = vid_priv->fb + y * vid_priv->line_length + VID_TO_PIXEL(x) * VNBYTES(vid_priv->bpix); linenum = priv->baseline + yoff; if (linenum > 0) - line += linenum * vid_priv->line_length; + start += linenum * vid_priv->line_length; + line = start; /* * Write a row at a time, converting the 8bpp image into the colour @@ -286,6 +296,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, *dst++ &= out; bits++; } + end = dst; break; } #endif @@ -307,6 +318,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, *dst++ &= out; bits++; } + end = dst; break; } #endif @@ -317,6 +329,9 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, line += vid_priv->line_length; } + ret = vidconsole_sync_copy(dev, start, line); + if (ret) + return ret; free(data); return width_frac; @@ -340,12 +355,13 @@ static int console_truetype_erase(struct udevice *dev, int xstart, int ystart, int xend, int yend, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); - void *line; + void *start, *line; int pixels = xend - xstart; - int row, i; + int row, i, ret; - line = vid_priv->fb + ystart * vid_priv->line_length; - line += xstart * VNBYTES(vid_priv->bpix); + start = vid_priv->fb + ystart * vid_priv->line_length; + start += xstart * VNBYTES(vid_priv->bpix); + line = start; for (row = ystart; row < yend; row++) { switch (vid_priv->bpix) { #ifdef CONFIG_VIDEO_BPP8 @@ -380,6 +396,9 @@ static int console_truetype_erase(struct udevice *dev, int xstart, int ystart, } line += vid_priv->line_length; } + ret = vidconsole_sync_copy(dev, start, line); + if (ret) + return ret; return 0; } diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c index 4c57e311d1..2587f53ac1 100644 --- a/drivers/video/ivybridge_igd.c +++ b/drivers/video/ivybridge_igd.c @@ -11,6 +11,7 @@ #include <log.h> #include <pci_rom.h> #include <vbe.h> +#include <video.h> #include <asm/intel_regs.h> #include <asm/io.h> #include <asm/mtrr.h> @@ -722,7 +723,6 @@ static int gma_func0_init(struct udevice *dev) { struct udevice *nbridge; void *gtt_bar; - ulong base; u32 reg32; int ret; int rev; @@ -742,11 +742,6 @@ static int gma_func0_init(struct udevice *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; dm_pci_write_config32(dev, PCI_COMMAND, reg32); - /* Use write-combining for the graphics memory, 256MB */ - base = dm_pci_read_bar32(dev, 2); - mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20); - mtrr_commit(true); - gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0); debug("GT bar %p\n", gtt_bar); ret = gma_pm_init_pre_vbios(gtt_bar, rev); @@ -758,6 +753,8 @@ static int gma_func0_init(struct udevice *dev) static int bd82x6x_video_probe(struct udevice *dev) { + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + ulong fbbase; void *gtt_bar; int ret, rev; @@ -774,6 +771,22 @@ static int bd82x6x_video_probe(struct udevice *dev) if (ret) return ret; + /* Use write-combining for the graphics memory, 256MB */ + fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base; + mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20); + mtrr_commit(true); + + return 0; +} + +static int bd82x6x_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + + /* Set the maximum supported resolution */ + uc_plat->size = 2560 * 1600 * 4; + log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + return 0; } @@ -786,5 +799,6 @@ U_BOOT_DRIVER(bd82x6x_video) = { .name = "bd82x6x_video", .id = UCLASS_VIDEO, .of_match = bd82x6x_video_ids, + .bind = bd82x6x_video_bind, .probe = bd82x6x_video_probe, }; diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c index 20248e6607..f529a350fb 100644 --- a/drivers/video/sandbox_sdl.c +++ b/drivers/video/sandbox_sdl.c @@ -23,6 +23,7 @@ enum { static int sandbox_sdl_probe(struct udevice *dev) { + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); struct sandbox_sdl_plat *plat = dev_get_platdata(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct sandbox_state *state = state_get_current(); @@ -40,6 +41,8 @@ static int sandbox_sdl_probe(struct udevice *dev) uc_priv->rot = plat->rot; uc_priv->vidconsole_drv_name = plat->vidconsole_drv_name; uc_priv->font_size = plat->font_size; + if (IS_ENABLED(CONFIG_VIDEO_COPY)) + uc_plat->copy_base = uc_plat->base - uc_plat->size / 2; return 0; } @@ -53,8 +56,13 @@ static int sandbox_sdl_bind(struct udevice *dev) plat->xres = dev_read_u32_default(dev, "xres", LCD_MAX_WIDTH); plat->yres = dev_read_u32_default(dev, "yres", LCD_MAX_HEIGHT); plat->bpix = dev_read_u32_default(dev, "log2-depth", VIDEO_BPP16); + plat->rot = dev_read_u32_default(dev, "rotate", 0); uc_plat->size = plat->xres * plat->yres * (1 << plat->bpix) / 8; - debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + + /* Allow space for two buffers, the lower one being the copy buffer */ + log_debug("Frame buffer size %x\n", uc_plat->size); + if (IS_ENABLED(CONFIG_VIDEO_COPY)) + uc_plat->size *= 2; return ret; } diff --git a/drivers/video/vesa.c b/drivers/video/vesa.c index 6c03611e80..9656326bdb 100644 --- a/drivers/video/vesa.c +++ b/drivers/video/vesa.c @@ -5,12 +5,39 @@ #include <common.h> #include <dm.h> +#include <log.h> #include <pci.h> #include <vbe.h> +#include <video.h> +#include <asm/mtrr.h> static int vesa_video_probe(struct udevice *dev) { - return vbe_setup_video(dev, NULL); + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + ulong fbbase; + int ret; + + ret = vbe_setup_video(dev, NULL); + if (ret) + return log_ret(ret); + + /* Use write-combining for the graphics memory, 256MB */ + fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base; + mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20); + mtrr_commit(true); + + return 0; +} + +static int vesa_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + + /* Set the maximum supported resolution */ + uc_plat->size = 2560 * 1600 * 4; + log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + + return 0; } static const struct udevice_id vesa_video_ids[] = { @@ -22,6 +49,7 @@ U_BOOT_DRIVER(vesa_video) = { .name = "vesa_video", .id = UCLASS_VIDEO, .of_match = vesa_video_ids, + .bind = vesa_video_bind, .probe = vesa_video_probe, }; diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 3f20f70e9a..3a07f36ce2 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -9,12 +9,13 @@ #include <common.h> #include <command.h> +#include <console.h> #include <log.h> -#include <linux/ctype.h> #include <dm.h> #include <video.h> #include <video_console.h> #include <video_font.h> /* Bitmap font for code page 437 */ +#include <linux/ctype.h> /* * Structure to describe a console color @@ -556,16 +557,31 @@ int vidconsole_put_string(struct udevice *dev, const char *str) static void vidconsole_putc(struct stdio_dev *sdev, const char ch) { struct udevice *dev = sdev->priv; + int ret; - vidconsole_put_char(dev, ch); + ret = vidconsole_put_char(dev, ch); + if (ret) { +#ifdef DEBUG + console_puts_select_stderr(true, "[vc err: putc]"); +#endif + } video_sync(dev->parent, false); } static void vidconsole_puts(struct stdio_dev *sdev, const char *s) { struct udevice *dev = sdev->priv; + int ret; + + ret = vidconsole_put_string(dev, s); + if (ret) { +#ifdef DEBUG + char str[30]; - vidconsole_put_string(dev, s); + snprintf(str, sizeof(str), "[vc err: puts %d]", ret); + console_puts_select_stderr(true, str); +#endif + } video_sync(dev->parent, false); } @@ -613,6 +629,22 @@ UCLASS_DRIVER(vidconsole) = { .per_device_auto_alloc_size = sizeof(struct vidconsole_priv), }; +#ifdef CONFIG_VIDEO_COPY +int vidconsole_sync_copy(struct udevice *dev, void *from, void *to) +{ + struct udevice *vid = dev_get_parent(dev); + + return video_sync_copy(vid, from, to); +} + +int vidconsole_memmove(struct udevice *dev, void *dst, const void *src, + int size) +{ + memmove(dst, src, size); + return vidconsole_sync_copy(dev, dst, dst + size); +} +#endif + #if CONFIG_IS_ENABLED(CMD_VIDCONSOLE) void vidconsole_position_cursor(struct udevice *dev, unsigned col, unsigned row) { diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 1f2874554a..650891e49d 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <console.h> #include <cpu_func.h> #include <dm.h> #include <log.h> @@ -45,6 +46,19 @@ */ DECLARE_GLOBAL_DATA_PTR; +/** + * struct video_uc_priv - Information for the video uclass + * + * @video_ptr: Current allocation position of the video framebuffer pointer. + * While binding devices after relocation, this points to the next + * available address to use for a device's framebuffer. It starts at + * gd->video_top and works downwards, running out of space when it hits + * gd->video_bottom. + */ +struct video_uc_priv { + ulong video_ptr; +}; + void video_set_flush_dcache(struct udevice *dev, bool flush) { struct video_priv *priv = dev_get_uclass_priv(dev); @@ -83,6 +97,11 @@ int video_reserve(ulong *addrp) debug("%s: Reserving %lx bytes at %lx for video device '%s'\n", __func__, size, *addrp, dev->name); } + + /* Allocate space for PCI video devices in case there were not bound */ + if (*addrp == gd->video_top) + *addrp -= CONFIG_VIDEO_PCI_DEFAULT_FB_SIZE; + gd->video_bottom = *addrp; gd->fb_base = *addrp; debug("Video frame buffers from %lx to %lx\n", gd->video_bottom, @@ -94,6 +113,7 @@ int video_reserve(ulong *addrp) int video_clear(struct udevice *dev) { struct video_priv *priv = dev_get_uclass_priv(dev); + int ret; switch (priv->bpix) { case VIDEO_BPP16: @@ -118,6 +138,9 @@ int video_clear(struct udevice *dev) memset(priv->fb, priv->colour_bg, priv->fb_size); break; } + ret = video_sync_copy(dev, priv->fb, priv->fb + priv->fb_size); + if (ret) + return ret; return 0; } @@ -201,6 +224,59 @@ int video_get_ysize(struct udevice *dev) return priv->ysize; } +#ifdef CONFIG_VIDEO_COPY +int video_sync_copy(struct udevice *dev, void *from, void *to) +{ + struct video_priv *priv = dev_get_uclass_priv(dev); + + if (priv->copy_fb) { + long offset, size; + + /* Find the offset of the first byte to copy */ + if ((ulong)to > (ulong)from) { + size = to - from; + offset = from - priv->fb; + } else { + size = from - to; + offset = to - priv->fb; + } + + /* + * Allow a bit of leeway for valid requests somewhere near the + * frame buffer + */ + if (offset < -priv->fb_size || offset > 2 * priv->fb_size) { +#ifdef DEBUG + char str[80]; + + snprintf(str, sizeof(str), + "[sync_copy fb=%p, from=%p, to=%p, offset=%lx]", + priv->fb, from, to, offset); + console_puts_select_stderr(true, str); +#endif + return -EFAULT; + } + + /* + * Silently crop the memcpy. This allows callers to avoid doing + * this themselves. It is common for the end pointer to go a + * few lines after the end of the frame buffer, since most of + * the update algorithms terminate a line after their last write + */ + if (offset + size > priv->fb_size) { + size = priv->fb_size - offset; + } else if (offset < 0) { + size += offset; + offset = 0; + } + + memcpy(priv->copy_fb + offset, priv->fb + offset, size); + } + + return 0; +} +#endif + /* Set up the colour map */ static int video_pre_probe(struct udevice *dev) { @@ -239,6 +315,9 @@ static int video_post_probe(struct udevice *dev) priv->fb_size = priv->line_length * priv->ysize; + if (IS_ENABLED(CONFIG_VIDEO_COPY) && plat->copy_base) + priv->copy_fb = map_sysmem(plat->copy_base, plat->size); + /* Set up colors */ video_set_default_colors(dev, false); @@ -290,12 +369,21 @@ static int video_post_probe(struct udevice *dev) /* Post-relocation, allocate memory for the frame buffer */ static int video_post_bind(struct udevice *dev) { - ulong addr = gd->video_top; + struct video_uc_priv *uc_priv; + ulong addr; ulong size; /* Before relocation there is nothing to do here */ if (!(gd->flags & GD_FLG_RELOC)) return 0; + + /* Set up the video pointer, if this is the first device */ + uc_priv = dev->uclass->priv; + if (!uc_priv->video_ptr) + uc_priv->video_ptr = gd->video_top; + + /* Allocate framebuffer space for this device */ + addr = uc_priv->video_ptr; size = alloc_fb(dev, &addr); if (addr < gd->video_bottom) { /* Device tree node may need the 'u-boot,dm-pre-reloc' or @@ -307,7 +395,7 @@ static int video_post_bind(struct udevice *dev) } debug("%s: Claiming %lx bytes at %lx for video device '%s'\n", __func__, size, addr, dev->name); - gd->video_bottom = addr; + uc_priv->video_ptr = addr; return 0; } @@ -320,6 +408,7 @@ UCLASS_DRIVER(video) = { .pre_probe = video_pre_probe, .post_probe = video_post_probe, .pre_remove = video_pre_remove, + .priv_auto_alloc_size = sizeof(struct video_uc_priv), .per_device_auto_alloc_size = sizeof(struct video_priv), .per_device_platdata_auto_alloc_size = sizeof(struct video_uc_platdata), }; diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index 7d7f37b445..5a4d12c68d 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -192,7 +192,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, struct video_priv *priv = dev_get_uclass_priv(dev); ushort *cmap_base = NULL; int i, j; - uchar *fb; + uchar *start, *fb; struct bmp_image *bmp = map_sysmem(bmp_image, 0); uchar *bmap; ushort padded_width; @@ -201,6 +201,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, unsigned colours, bpix, bmp_bpix; struct bmp_color_table_entry *palette; int hdr_size; + int ret; if (!bmp || !(bmp->header.signature[0] == 'B' && bmp->header.signature[1] == 'M')) { @@ -261,8 +262,11 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, height = priv->ysize - y; bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset); - fb = (uchar *)(priv->fb + - (y + height - 1) * priv->line_length + x * bpix / 8); + start = (uchar *)(priv->fb + + (y + height) * priv->line_length + x * bpix / 8); + + /* Move back to the final line to be drawn */ + fb = start - priv->line_length; switch (bmp_bpix) { case 1: @@ -369,6 +373,12 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, break; }; + /* Find the position of the top left of the image in the framebuffer */ + fb = (uchar *)(priv->fb + y * priv->line_length + x * bpix / 8); + ret = video_sync_copy(dev, start, fb); + if (ret) + return log_ret(ret); + video_sync(dev, false); return 0; diff --git a/include/bootstage.h b/include/bootstage.h index f507271375..00c85fb86a 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -338,7 +338,7 @@ int bootstage_stash(void *base, int size); * @param base Base address of memory buffer * @param size Size of memory buffer (-1 if unknown) * @return 0 if unstashed ok, -ENOENT if bootstage info not found, -ENOSPC if - * there is not space for read the stacked data, or other error if + * there is not space for read the stashed data, or other error if * something else went wrong */ int bootstage_unstash(const void *base, int size); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1cb62ae849..4b40129197 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -43,11 +43,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index b4e5e3b3e2..429dae19af 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -45,11 +45,6 @@ #define CONFIG_ENABLE_36BIT_PHYS 1 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - /* * Config the L2 Cache as L2 SRAM */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index a7f02aef29..1560b61387 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -19,7 +19,6 @@ /* High Level Configuration Options */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#define CONFIG_ADDR_MAP 1 /* Use addr map */ /* * default CCSRBAR is at 0xff700000 @@ -47,7 +46,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ #define CONFIG_ALTIVEC 1 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 8f709a6cac..fc74d57497 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -196,11 +196,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - /* DDR Setup */ #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 94cbe10dd3..c6a64ee479 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -70,11 +70,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index f5d9657444..efd9b6b5e1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -17,11 +17,6 @@ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 4237dfcd6c..8f9de56f07 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -186,9 +186,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index c54f7f53e5..f32e6680b3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -26,11 +26,6 @@ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 70eafc3e28..e666e4f4a4 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -20,11 +20,6 @@ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9832f85405..ebe7a9cf92 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -80,9 +80,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 823586cc09..512d8e16ee 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -41,11 +41,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - #define CONFIG_L2_CACHE #define CONFIG_BTB diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a49f9056c5..d7812bd886 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -84,11 +84,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 052e6018a3..b587cb8d77 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -70,11 +70,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - /* test POST memory test */ #undef CONFIG_POST diff --git a/include/configs/helios4.h b/include/configs/helios4.h index 31e2e78b62..2f4b67025c 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -6,7 +6,6 @@ #ifndef _CONFIG_HELIOS4_H #define _CONFIG_HELIOS4_H -#include <linux/sizes.h> #include <linux/stringify.h> /* @@ -30,26 +29,30 @@ #define CONFIG_ENV_MIN_ENTRIES 128 +/* Environment in MMC */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* - * SATA/SCSI/AHCI configuration + * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC + * boot image starts @ LBA-0. + * As result in MMC/eMMC case it will be a 1 sector gap between u-boot + * image and environment */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 2 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI -/* Environment in SPI NOR flash */ -#endif +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -/* Environment in MMC */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -/* stay within first 1M */ +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW #endif -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ +/* SATA support */ +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ @@ -57,22 +60,6 @@ "initrd_high=0x10000000\0" /* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH -#endif -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD -#endif /* Defines for SPL */ #define CONFIG_SPL_SIZE (140 << 10) @@ -88,11 +75,10 @@ #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) +/* SPL related SPI defines */ #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS -#endif - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD +#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) /* SPL related MMC defines */ #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS @@ -100,6 +86,7 @@ #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #endif #endif + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -121,16 +108,46 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif -#ifdef CONFIG_SATA -#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0) +#ifndef CONFIG_SCSI +#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) +#else +/* + * With SCSI enabled, M.2 SATA is always located on bus 0 + */ +#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) func(SCSI, scsi, 0) + +/* + * Either one or both mPCIe slots may be configured as mSATA interfaces. The + * SCSI bus ids are assigned based on sequence of hardware present, not always + * tied to hardware slot ids. As such, use second SCSI bus if either slot is + * set for SATA, and only use third SCSI bus if both slots are SATA enabled. + */ +#if defined (CONFIG_HELIOS4_CON2_SATA) || defined (CONFIG_HELIOS4_CON3_SATA) +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) func(SCSI, scsi, 1) +#else +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) +#endif + +#if defined (CONFIG_HELIOS4_CON2_SATA) && defined (CONFIG_HELIOS4_CON3_SATA) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) func(SCSI, scsi, 2) #else -#define BOOT_TARGET_DEVICES_SATA(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) #endif +#endif /* CONFIG_SCSI */ + +/* + * The SCSI buses are attempted in increasing bus order, there is no current + * mechanism to alter the default bus priority order for booting. + */ #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_USB(func) \ - BOOT_TARGET_DEVICES_SATA(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS0(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS1(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS2(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index e43b2f7513..6cd77edf70 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -64,9 +64,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ /* diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 5bb0255a74..031bc995e3 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -83,18 +83,17 @@ /* * SATA Driver configuration */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET + +#ifdef CONFIG_SATA +#define CONFIG_SYS_64BIT_LBA +#define CONFIG_LBA48 #if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ defined(CONFIG_NET2BIG_V2) -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 #else -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_SATA_MAX_DEVICE 1 #endif -#endif /* CONFIG_MVSATA_IDE */ +#endif /* CONFIG_SATA */ /* * Enable GPI0 support @@ -144,8 +143,8 @@ "set stdin $stdin,nc; " \ "set stdout $stdout,nc; " \ "set stderr $stderr,nc;\0" \ - "diskload=ide reset && " \ - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "diskload=sata init && " \ + "ext2load sata 0:1 $loadaddr /boot/$bootfile\0" \ "usbload=usb start && " \ "fatload usb 0:1 $loadaddr /boot/$bootfile\0" diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 6b57be912a..a33f2f30ca 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -233,11 +233,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 03b08968f6..b3ec43073c 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -21,9 +21,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ - /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 3da7ee7b3a..1f6ae462ae 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -42,9 +42,6 @@ #define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/console.h b/include/console.h index 74afe22b7e..4c6b8f2614 100644 --- a/include/console.h +++ b/include/console.h @@ -7,6 +7,8 @@ #ifndef __CONSOLE_H #define __CONSOLE_H +#include <stdbool.h> + extern char console_buffer[]; /* common/console.c */ @@ -72,6 +74,17 @@ int console_record_avail(void); */ int console_announce_r(void); +/** + * console_puts_select_stderr() - Output a string to selected console devices + * + * This writes to stderr only. It is useful for outputting errors + * + * @serial_only: true to output only to serial, false to output to everything + * else + * @s: String to output + */ +void console_puts_select_stderr(bool serial_only, const char *s); + /* * CONSOLE multiplexing. */ diff --git a/include/dm/test.h b/include/dm/test.h index f0f36624ce..d39686cde2 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -159,7 +159,19 @@ enum { /* Declare a new driver model test */ #define DM_TEST(_name, _flags) UNIT_TEST(_name, _flags, dm_test) -/* This platform data is needed in tests, so declare it here */ +/* + * struct sandbox_sdl_plat - Platform data for the SDL video driver + * + * This platform data is needed in tests, so declare it here + * + * @xres: Width of display in pixels + * @yres: Height of display in pixels + * @bpix: Log2 of bits per pixel (enum video_log2_bpp) + * @rot: Console rotation (0=normal orientation, 1=90 degrees clockwise, + * 2=upside down, 3=90 degree counterclockwise) + * @vidconsole_drv_name: Name of video console driver (set by tests) + * @font_size: Console font size to select (set by tests) + */ struct sandbox_sdl_plat { int xres; int yres; diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h index 3a2da738c4..d109ed3119 100644 --- a/include/linux/kconfig.h +++ b/include/linux/kconfig.h @@ -23,54 +23,30 @@ #define ___config_enabled(__ignored, val, ...) val /* - * IS_ENABLED(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y' or 'm', + * IS_ENABLED(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y', * 0 otherwise. * */ #define IS_ENABLED(option) \ - (config_enabled(option) || config_enabled(option##_MODULE)) - -/* - * IS_BUILTIN(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y', 0 - * otherwise. For boolean options, this is equivalent to - * IS_ENABLED(CONFIG_FOO). - */ -#define IS_BUILTIN(option) config_enabled(option) - -/* - * IS_MODULE(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'm', 0 - * otherwise. - */ -#define IS_MODULE(option) config_enabled(option##_MODULE) + (config_enabled(option)) /* * U-Boot add-on: Helper macros to reference to different macros * (CONFIG_ or CONFIG_SPL_ prefixed), depending on the build context. */ -#ifdef CONFIG_SPL_BUILD -#define _IS_SPL 1 -#endif - -#ifdef CONFIG_TPL_BUILD -#define _IS_TPL 1 -#endif #if defined(CONFIG_TPL_BUILD) -#define config_val(cfg) _config_val(_IS_TPL, cfg) -#define _config_val(x, cfg) __config_val(x, cfg) -#define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) -#define ___config_val(arg1_or_junk, cfg) \ - ____config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg) -#define ____config_val(__ignored, val, ...) val +#define _CONFIG_PREFIX TPL_ +#elif defined(CONFIG_SPL_BUILD) +#define _CONFIG_PREFIX SPL_ #else -#define config_val(cfg) _config_val(_IS_SPL, cfg) -#define _config_val(x, cfg) __config_val(x, cfg) -#define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) -#define ___config_val(arg1_or_junk, cfg) \ - ____config_val(arg1_or_junk CONFIG_SPL_##cfg, CONFIG_##cfg) -#define ____config_val(__ignored, val, ...) val +#define _CONFIG_PREFIX #endif +#define config_val(cfg) _config_val(_CONFIG_PREFIX, cfg) +#define _config_val(pfx, cfg) __config_val(pfx, cfg) +#define __config_val(pfx, cfg) CONFIG_ ## pfx ## cfg + /* * CONFIG_VAL(FOO) evaluates to the value of * CONFIG_FOO if CONFIG_SPL_BUILD is undefined, @@ -80,30 +56,55 @@ #define CONFIG_VAL(option) config_val(option) /* - * CONFIG_IS_ENABLED(FOO) evaluates to - * 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y' or 'm', - * 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y' or 'm', - * 1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y' or 'm', - * 0 otherwise. + * Count number of arguments to a variadic macro. Currently only need + * it for 1, 2 or 3 arguments. */ -#define CONFIG_IS_ENABLED(option) \ - (config_enabled(CONFIG_VAL(option)) || \ - config_enabled(CONFIG_VAL(option##_MODULE))) +#define __arg6(a1, a2, a3, a4, a5, a6, ...) a6 +#define __count_args(...) __arg6(dummy, ##__VA_ARGS__, 4, 3, 2, 1, 0) + +#define __concat(a, b) ___concat(a, b) +#define ___concat(a, b) a ## b + +#define __unwrap(...) __VA_ARGS__ +#define __unwrap1(case1, case0) __unwrap case1 +#define __unwrap0(case1, case0) __unwrap case0 + +#define __CONFIG_IS_ENABLED_1(option) __CONFIG_IS_ENABLED_3(option, (1), (0)) +#define __CONFIG_IS_ENABLED_2(option, case1) __CONFIG_IS_ENABLED_3(option, case1, ()) +#define __CONFIG_IS_ENABLED_3(option, case1, case0) \ + __concat(__unwrap, config_enabled(CONFIG_VAL(option))) (case1, case0) /* - * CONFIG_IS_BUILTIN(FOO) evaluates to + * CONFIG_IS_ENABLED(FOO) expands to * 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', * 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', + * 1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', * 0 otherwise. + * + * CONFIG_IS_ENABLED(FOO, (abc)) expands to + * abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', + * abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', + * abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', + * nothing otherwise. + * + * CONFIG_IS_ENABLED(FOO, (abc), (def)) expands to + * abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', + * abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', + * abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', + * def otherwise. + * + * The optional second and third arguments must be parenthesized; that + * allows one to include a trailing comma, e.g. for use in + * + * CONFIG_IS_ENABLED(ACME, ({.compatible = "acme,frobnozzle"},)) + * + * which adds an entry to the array being defined if CONFIG_ACME (or + * CONFIG_SPL_ACME/CONFIG_TPL_ACME, depending on build context) is + * set, and nothing otherwise. */ -#define CONFIG_IS_BUILTIN(option) config_enabled(CONFIG_VAL(option)) -/* - * CONFIG_IS_MODULE(FOO) evaluates to - * 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'm', - * 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'm', - * 0 otherwise. - */ -#define CONFIG_IS_MODULE(option) config_enabled(CONFIG_VAL(option##_MODULE)) +#define CONFIG_IS_ENABLED(option, ...) \ + __concat(__CONFIG_IS_ENABLED_, __count_args(option, ##__VA_ARGS__)) (option, ##__VA_ARGS__) + #endif /* __LINUX_KCONFIG_H */ diff --git a/include/rtc.h b/include/rtc.h index 8aabfc1162..1efc0db3de 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -56,6 +56,30 @@ struct rtc_ops { int (*reset)(struct udevice *dev); /** + * read() - Read multiple 8-bit registers + * + * @dev: Device to read from + * @reg: First register to read + * @buf: Output buffer + * @len: Number of registers to read + * @return 0 if OK, -ve on error + */ + int (*read)(struct udevice *dev, unsigned int reg, + u8 *buf, unsigned int len); + + /** + * write() - Write multiple 8-bit registers + * + * @dev: Device to write to + * @reg: First register to write + * @buf: Input buffer + * @len: Number of registers to write + * @return 0 if OK, -ve on error + */ + int (*write)(struct udevice *dev, unsigned int reg, + const u8 *buf, unsigned int len); + + /** * read8() - Read an 8-bit register * * @dev: Device to read from @@ -110,6 +134,29 @@ int dm_rtc_set(struct udevice *dev, struct rtc_time *time); int dm_rtc_reset(struct udevice *dev); /** + * dm_rtc_read() - Read multiple 8-bit registers + * + * @dev: Device to read from + * @reg: First register to read + * @buf: Output buffer + * @len: Number of registers to read + * @return 0 if OK, -ve on error + */ +int dm_rtc_read(struct udevice *dev, unsigned int reg, u8 *buf, unsigned int len); + +/** + * dm_rtc_write() - Write multiple 8-bit registers + * + * @dev: Device to write to + * @reg: First register to write + * @buf: Input buffer + * @len: Number of registers to write + * @return 0 if OK, -ve on error + */ +int dm_rtc_write(struct udevice *dev, unsigned int reg, + const u8 *buf, unsigned int len); + +/** * rtc_read8() - Read an 8-bit register * * @dev: Device to read from diff --git a/include/spi.h b/include/spi.h index 9b4fb8dc0b..a37900b2fd 100644 --- a/include/spi.h +++ b/include/spi.h @@ -39,7 +39,6 @@ #define SPI_DEFAULT_WORDLEN 8 -#if CONFIG_IS_ENABLED(DM_SPI) /* TODO(sjg@chromium.org): Remove this and use max_hz from struct spi_slave */ struct dm_spi_bus { uint max_hz; @@ -65,8 +64,6 @@ struct dm_spi_slave_platdata { uint mode; }; -#endif /* CONFIG_DM_SPI */ - /** * enum spi_clock_phase - indicates the clock phase to use for SPI (CPHA) * @@ -317,6 +314,11 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len); */ int spi_cs_is_valid(unsigned int bus, unsigned int cs); +/* + * These names are used in several drivers and these declarations will be + * removed soon as part of the SPI DM migration. Drop them if driver model is + * enabled for SPI. + */ #if !CONFIG_IS_ENABLED(DM_SPI) /** * Activate a SPI chipselect. @@ -335,6 +337,7 @@ void spi_cs_activate(struct spi_slave *slave); * select to the device identified by "slave". */ void spi_cs_deactivate(struct spi_slave *slave); +#endif /** * Set transfer speed. @@ -343,7 +346,6 @@ void spi_cs_deactivate(struct spi_slave *slave); * @hz: The transfer speed */ void spi_set_speed(struct spi_slave *slave, uint hz); -#endif /** * Write 8 bits, then read 8 bits. @@ -367,8 +369,6 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) return ret < 0 ? ret : din[1]; } -#if CONFIG_IS_ENABLED(DM_SPI) - /** * struct spi_cs_info - Information about a bus chip select * @@ -717,6 +717,5 @@ int dm_spi_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep, /* Access the operations for a SPI device */ #define spi_get_ops(dev) ((struct dm_spi_ops *)(dev)->driver->ops) #define spi_emul_get_ops(dev) ((struct dm_spi_emul_ops *)(dev)->driver->ops) -#endif /* CONFIG_DM_SPI */ #endif /* _SPI_H_ */ diff --git a/include/video.h b/include/video.h index e7c58e86cb..1a0ffd8037 100644 --- a/include/video.h +++ b/include/video.h @@ -19,10 +19,25 @@ struct udevice; +/** + * struct video_uc_platdata - uclass platform data for a video device + * + * This holds information that the uclass needs to know about each device. It + * is accessed using dev_get_uclass_platdata(dev). See 'Theory of operation' at + * the top of video-uclass.c for details on how this information is set. + * + * @align: Frame-buffer alignment, indicating the memory boundary the frame + * buffer should start on. If 0, 1MB is assumed + * @size: Frame-buffer size, in bytes + * @base: Base address of frame buffer, 0 if not yet known + * @copy_base: Base address of a hardware copy of the frame buffer. See + * CONFIG_VIDEO_COPY. + */ struct video_uc_platdata { uint align; uint size; ulong base; + ulong copy_base; }; enum video_polarity { @@ -63,6 +78,8 @@ enum video_log2_bpp { * @font_size: Font size in pixels (0 to use a default value) * @fb: Frame buffer * @fb_size: Frame buffer size + * @copy_fb: Copy of the frame buffer to keep up to date; see struct + * video_uc_platdata * @line_length: Length of each frame buffer line, in bytes. This can be * set by the driver, but if not, the uclass will set it after * probing @@ -89,6 +106,7 @@ struct video_priv { */ void *fb; int fb_size; + void *copy_fb; int line_length; u32 colour_fg; u32 colour_bg; @@ -202,6 +220,29 @@ void video_set_flush_dcache(struct udevice *dev, bool flush); */ void video_set_default_colors(struct udevice *dev, bool invert); +#ifdef CONFIG_VIDEO_COPY +/** + * vidconsole_sync_copy() - Sync back to the copy framebuffer + * + * This ensures that the copy framebuffer has the same data as the framebuffer + * for a particular region. It should be called after the framebuffer is updated + * + * @from and @to can be in either order. The region between them is synced. + * + * @dev: Vidconsole device being updated + * @from: Start/end address within the framebuffer (->fb) + * @to: Other address within the frame buffer + * @return 0 if OK, -EFAULT if the start address is before the start of the + * frame buffer start + */ +int video_sync_copy(struct udevice *dev, void *from, void *to); +#else +static inline int video_sync_copy(struct udevice *dev, void *from, void *to) +{ + return 0; +} +#endif + #endif /* CONFIG_DM_VIDEO */ #ifndef CONFIG_DM_VIDEO diff --git a/include/video_console.h b/include/video_console.h index 0936ceaaf1..06b798ef10 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -8,6 +8,8 @@ #include <video.h> +struct video_priv; + #define VID_FRAC_DIV 256 #define VID_TO_PIXEL(x) ((x) / VID_FRAC_DIV) @@ -241,8 +243,6 @@ int vidconsole_put_string(struct udevice *dev, const char *str); void vidconsole_position_cursor(struct udevice *dev, unsigned col, unsigned row); -#ifdef CONFIG_DM_VIDEO - /** * vid_console_color() - convert a color code to a pixel's internal * representation @@ -256,6 +256,53 @@ void vidconsole_position_cursor(struct udevice *dev, unsigned col, */ u32 vid_console_color(struct video_priv *priv, unsigned int idx); +#ifdef CONFIG_VIDEO_COPY +/** + * vidconsole_sync_copy() - Sync back to the copy framebuffer + * + * This ensures that the copy framebuffer has the same data as the framebuffer + * for a particular region. It should be called after the framebuffer is updated + * + * @from and @to can be in either order. The region between them is synced. + * + * @dev: Vidconsole device being updated + * @from: Start/end address within the framebuffer (->fb) + * @to: Other address within the frame buffer + * @return 0 if OK, -EFAULT if the start address is before the start of the + * frame buffer start + */ +int vidconsole_sync_copy(struct udevice *dev, void *from, void *to); + +/** + * vidconsole_memmove() - Perform a memmove() within the frame buffer + * + * This handles a memmove(), e.g. for scrolling. It also updates the copy + * framebuffer. + * + * @dev: Vidconsole device being updated + * @dst: Destination address within the framebuffer (->fb) + * @src: Source address within the framebuffer (->fb) + * @size: Number of bytes to transfer + * @return 0 if OK, -EFAULT if the start address is before the start of the + * frame buffer start + */ +int vidconsole_memmove(struct udevice *dev, void *dst, const void *src, + int size); +#else +static inline int vidconsole_sync_copy(struct udevice *dev, void *from, + void *to) +{ + return 0; +} + +static inline int vidconsole_memmove(struct udevice *dev, void *dst, + const void *src, int size) +{ + memmove(dst, src, size); + + return 0; +} + #endif #endif diff --git a/lib/Kconfig b/lib/Kconfig index fc7d68487b..2142bd06e6 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1,5 +1,18 @@ menu "Library routines" +config ADDR_MAP + bool "Enable support for non-identity virtual-physical mappings" + help + Enables helper code for implementing non-identity virtual-physical + memory mappings for 32bit CPUs. + +config SYS_NUM_ADDR_MAP + int "Size of the address-map table" + depends on ADDR_MAP + default 16 + help + Sets the number of entries in the virtual-physical mapping table. + config BCH bool "Enable Software based BCH ECC" help diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 747583089b..0547e22af6 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -15,7 +15,6 @@ CONFIG_ACX517AKN CONFIG_ACX544AKN CONFIG_ADDRESS CONFIG_ADDR_AUTO_INCR_BIT -CONFIG_ADDR_MAP CONFIG_ADNPESC1 CONFIG_AEABI CONFIG_AEMIF_CNTRL_BASE @@ -873,9 +872,7 @@ CONFIG_IRAM_SIZE CONFIG_IRAM_STACK CONFIG_IRAM_TOP CONFIG_IRDA_BASE -CONFIG_IS_BUILTIN CONFIG_IS_ENABLED -CONFIG_IS_MODULE CONFIG_JFFS2_CMDLINE CONFIG_JFFS2_DEV CONFIG_JFFS2_LZO @@ -3268,7 +3265,6 @@ CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL -CONFIG_SYS_NUM_ADDR_MAP CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_FM1_10GEC CONFIG_SYS_NUM_FM1_DTSEC diff --git a/test/dm/rtc.c b/test/dm/rtc.c index 88f86581cc..dd037a6e17 100644 --- a/test/dm/rtc.c +++ b/test/dm/rtc.c @@ -5,11 +5,13 @@ */ #include <common.h> +#include <console.h> #include <dm.h> #include <i2c.h> #include <log.h> #include <rtc.h> #include <asm/io.h> +#include <asm/rtc.h> #include <asm/test.h> #include <dm/test.h> #include <test/ut.h> @@ -70,7 +72,20 @@ static int dm_test_rtc_set_get(struct unit_test_state *uts) old_base_time = sandbox_i2c_rtc_get_set_base_time(emul, -1); memset(&time, '\0', sizeof(time)); - time.tm_mday = 25; + time.tm_mday = 3; + time.tm_mon = 6; + time.tm_year = 2004; + time.tm_sec = 0; + time.tm_min = 18; + time.tm_hour = 18; + ut_assertok(dm_rtc_set(dev, &time)); + + memset(&cmp, '\0', sizeof(cmp)); + ut_assertok(dm_rtc_get(dev, &cmp)); + ut_assertok(cmp_times(&time, &cmp, true)); + + memset(&time, '\0', sizeof(time)); + time.tm_mday = 31; time.tm_mon = 8; time.tm_year = 2004; time.tm_sec = 0; @@ -117,6 +132,107 @@ static int dm_test_rtc_set_get(struct unit_test_state *uts) } DM_TEST(dm_test_rtc_set_get, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); +static int dm_test_rtc_read_write(struct unit_test_state *uts) +{ + struct rtc_time time; + struct udevice *dev, *emul; + long old_offset; + u8 buf[4], reg; + + ut_assertok(uclass_get_device(UCLASS_RTC, 0, &dev)); + + memcpy(buf, "car", 4); + ut_assertok(dm_rtc_write(dev, REG_AUX0, buf, 4)); + memset(buf, '\0', sizeof(buf)); + ut_assertok(dm_rtc_read(dev, REG_AUX0, buf, 4)); + ut_asserteq(memcmp(buf, "car", 4), 0); + + reg = 'b'; + ut_assertok(dm_rtc_write(dev, REG_AUX0, ®, 1)); + memset(buf, '\0', sizeof(buf)); + ut_assertok(dm_rtc_read(dev, REG_AUX0, buf, 4)); + ut_asserteq(memcmp(buf, "bar", 4), 0); + + reg = 't'; + ut_assertok(dm_rtc_write(dev, REG_AUX2, ®, 1)); + memset(buf, '\0', sizeof(buf)); + ut_assertok(dm_rtc_read(dev, REG_AUX1, buf, 3)); + ut_asserteq(memcmp(buf, "at", 3), 0); + + ut_assertok(i2c_emul_find(dev, &emul)); + ut_assert(emul != NULL); + + old_offset = sandbox_i2c_rtc_set_offset(emul, false, 0); + ut_assertok(dm_rtc_get(dev, &time)); + + ut_assertok(dm_rtc_read(dev, REG_SEC, ®, 1)); + ut_asserteq(time.tm_sec, reg); + ut_assertok(dm_rtc_read(dev, REG_MDAY, ®, 1)); + ut_asserteq(time.tm_mday, reg); + + sandbox_i2c_rtc_set_offset(emul, true, old_offset); + + return 0; +} +DM_TEST(dm_test_rtc_read_write, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test 'rtc list' command */ +static int dm_test_rtc_cmd_list(struct unit_test_state *uts) +{ + console_record_reset(); + + run_command("rtc list", 0); + ut_assert_nextline("RTC #0 - rtc@43"); + ut_assert_nextline("RTC #1 - rtc@61"); + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_rtc_cmd_list, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test 'rtc read' and 'rtc write' commands */ +static int dm_test_rtc_cmd_rw(struct unit_test_state *uts) +{ + console_record_reset(); + + run_command("rtc dev 0", 0); + ut_assert_nextline("RTC #0 - rtc@43"); + ut_assert_console_end(); + + run_command("rtc write 0x30 aabb", 0); + ut_assert_console_end(); + + run_command("rtc read 0x30 2", 0); + ut_assert_nextline("00000030: aa bb .."); + ut_assert_console_end(); + + run_command("rtc dev 1", 0); + ut_assert_nextline("RTC #1 - rtc@61"); + ut_assert_console_end(); + + run_command("rtc write 0x30 ccdd", 0); + ut_assert_console_end(); + + run_command("rtc read 0x30 2", 0); + ut_assert_nextline("00000030: cc dd .."); + ut_assert_console_end(); + + /* + * Switch back to device #0, check that its aux registers + * still have the same values. + */ + run_command("rtc dev 0", 0); + ut_assert_nextline("RTC #0 - rtc@43"); + ut_assert_console_end(); + + run_command("rtc read 0x30 2", 0); + ut_assert_nextline("00000030: aa bb .."); + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_rtc_cmd_rw, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + /* Reset the time */ static int dm_test_rtc_reset(struct unit_test_state *uts) { diff --git a/test/dm/video.c b/test/dm/video.c index 0664e3f22b..19f78b6239 100644 --- a/test/dm/video.c +++ b/test/dm/video.c @@ -51,12 +51,18 @@ DM_TEST(dm_test_video_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); * size of the compressed data. This provides a pretty good level of * certainty and the resulting tests need only check a single value. * + * If the copy framebuffer is enabled, this compares it to the main framebuffer + * too. + * + * @uts: Test state * @dev: Video device * @return compressed size of the frame buffer, or -ve on error */ -static int compress_frame_buffer(struct udevice *dev) +static int compress_frame_buffer(struct unit_test_state *uts, + struct udevice *dev) { struct video_priv *priv = dev_get_uclass_priv(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); uint destlen; void *dest; int ret; @@ -72,6 +78,13 @@ static int compress_frame_buffer(struct udevice *dev) if (ret) return ret; + /* Check here that the copy frame buffer is working correctly */ + if (IS_ENABLED(CONFIG_VIDEO_COPY)) { + ut_assertf(!memcmp(uc_priv->fb, uc_priv->copy_fb, + uc_priv->fb_size), + "Copy framebuffer does not match fb"); + } + return destlen; } @@ -110,25 +123,25 @@ static int dm_test_video_text(struct unit_test_state *uts) ut_assertok(select_vidconsole(uts, "vidconsole0")); ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); - ut_asserteq(46, compress_frame_buffer(dev)); + ut_asserteq(46, compress_frame_buffer(uts, dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); vidconsole_putc_xy(con, 0, 0, 'a'); - ut_asserteq(79, compress_frame_buffer(dev)); + ut_asserteq(79, compress_frame_buffer(uts, dev)); vidconsole_putc_xy(con, 0, 0, ' '); - ut_asserteq(46, compress_frame_buffer(dev)); + ut_asserteq(46, compress_frame_buffer(uts, dev)); for (i = 0; i < 20; i++) vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i); - ut_asserteq(273, compress_frame_buffer(dev)); + ut_asserteq(273, compress_frame_buffer(uts, dev)); vidconsole_set_row(con, 0, WHITE); - ut_asserteq(46, compress_frame_buffer(dev)); + ut_asserteq(46, compress_frame_buffer(uts, dev)); for (i = 0; i < 20; i++) vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i); - ut_asserteq(273, compress_frame_buffer(dev)); + ut_asserteq(273, compress_frame_buffer(uts, dev)); return 0; } @@ -144,7 +157,7 @@ static int dm_test_video_chars(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); vidconsole_put_string(con, test_string); - ut_asserteq(466, compress_frame_buffer(dev)); + ut_asserteq(466, compress_frame_buffer(uts, dev)); return 0; } @@ -164,20 +177,20 @@ static int dm_test_video_ansi(struct unit_test_state *uts) /* reference clear: */ video_clear(con->parent); video_sync(con->parent, false); - ut_asserteq(46, compress_frame_buffer(dev)); + ut_asserteq(46, compress_frame_buffer(uts, dev)); /* test clear escape sequence: [2J */ vidconsole_put_string(con, "A\tB\tC"ANSI_ESC"[2J"); - ut_asserteq(46, compress_frame_buffer(dev)); + ut_asserteq(46, compress_frame_buffer(uts, dev)); /* test set-cursor: [%d;%df */ vidconsole_put_string(con, "abc"ANSI_ESC"[2;2fab"ANSI_ESC"[4;4fcd"); - ut_asserteq(143, compress_frame_buffer(dev)); + ut_asserteq(143, compress_frame_buffer(uts, dev)); /* test colors (30-37 fg color, 40-47 bg color) */ vidconsole_put_string(con, ANSI_ESC"[30;41mfoo"); /* black on red */ vidconsole_put_string(con, ANSI_ESC"[33;44mbar"); /* yellow on blue */ - ut_asserteq(272, compress_frame_buffer(dev)); + ut_asserteq(272, compress_frame_buffer(uts, dev)); return 0; } @@ -188,7 +201,8 @@ DM_TEST(dm_test_video_ansi, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); * check_vidconsole_output() - Run a text console test * * @uts: Test state - * @rot: Console rotation (0, 90, 180, 270) + * @rot: Console rotation (0=normal orientation, 1=90 degrees clockwise, + * 2=upside down, 3=90 degree counterclockwise) * @wrap_size: Expected size of compressed frame buffer for the wrap test * @scroll_size: Same for the scroll test * @return 0 on success @@ -207,24 +221,24 @@ static int check_vidconsole_output(struct unit_test_state *uts, int rot, ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); - ut_asserteq(46, compress_frame_buffer(dev)); + ut_asserteq(46, compress_frame_buffer(uts, dev)); /* Check display wrap */ for (i = 0; i < 120; i++) vidconsole_put_char(con, 'A' + i % 50); - ut_asserteq(wrap_size, compress_frame_buffer(dev)); + ut_asserteq(wrap_size, compress_frame_buffer(uts, dev)); /* Check display scrolling */ for (i = 0; i < SCROLL_LINES; i++) { vidconsole_put_char(con, 'A' + i % 50); vidconsole_put_char(con, '\n'); } - ut_asserteq(scroll_size, compress_frame_buffer(dev)); + ut_asserteq(scroll_size, compress_frame_buffer(uts, dev)); /* If we scroll enough, the screen becomes blank again */ for (i = 0; i < SCROLL_LINES; i++) vidconsole_put_char(con, '\n'); - ut_asserteq(46, compress_frame_buffer(dev)); + ut_asserteq(46, compress_frame_buffer(uts, dev)); return 0; } @@ -251,7 +265,7 @@ DM_TEST(dm_test_video_rotation1, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); /* Test rotated text output through the console uclass */ static int dm_test_video_rotation2(struct unit_test_state *uts) { - ut_assertok(check_vidconsole_output(uts, 2, 785, 446)); + ut_assertok(check_vidconsole_output(uts, 2, 783, 445)); return 0; } @@ -298,7 +312,7 @@ static int dm_test_video_bmp(struct unit_test_state *uts) ut_assertok(read_file(uts, "tools/logos/denx.bmp", &addr)); ut_assertok(video_bmp_display(dev, addr, 0, 0, false)); - ut_asserteq(1368, compress_frame_buffer(dev)); + ut_asserteq(1368, compress_frame_buffer(uts, dev)); return 0; } @@ -314,7 +328,7 @@ static int dm_test_video_bmp_comp(struct unit_test_state *uts) ut_assertok(read_file(uts, "tools/logos/denx-comp.bmp", &addr)); ut_assertok(video_bmp_display(dev, addr, 0, 0, false)); - ut_asserteq(1368, compress_frame_buffer(dev)); + ut_asserteq(1368, compress_frame_buffer(uts, dev)); return 0; } @@ -329,7 +343,7 @@ static int dm_test_video_truetype(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); vidconsole_put_string(con, test_string); - ut_asserteq(12237, compress_frame_buffer(dev)); + ut_asserteq(12237, compress_frame_buffer(uts, dev)); return 0; } @@ -350,7 +364,7 @@ static int dm_test_video_truetype_scroll(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); vidconsole_put_string(con, test_string); - ut_asserteq(35030, compress_frame_buffer(dev)); + ut_asserteq(35030, compress_frame_buffer(uts, dev)); return 0; } @@ -371,7 +385,7 @@ static int dm_test_video_truetype_bs(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); vidconsole_put_string(con, test_string); - ut_asserteq(29018, compress_frame_buffer(dev)); + ut_asserteq(29018, compress_frame_buffer(uts, dev)); return 0; } |