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-rw-r--r--arch/riscv/cpu/c9xx/cpu.c4
-rw-r--r--arch/riscv/cpu/mtrap.S2
-rw-r--r--arch/riscv/dts/Makefile2
-rw-r--r--arch/riscv/dts/light-a-ref.dts482
-rw-r--r--arch/riscv/dts/light-a-val.dts6
-rw-r--r--arch/riscv/dts/light-ant-ref.dts (renamed from arch/riscv/dts/light-ant-evt.dts)0
-rw-r--r--arch/riscv/dts/light-b-power.dts478
-rw-r--r--arch/riscv/dts/light-b-product.dts7
-rw-r--r--arch/riscv/dts/light-b-ref.dts485
-rw-r--r--arch/riscv/dts/light-beagle.dts488
-rw-r--r--arch/riscv/include/asm/arch-thead/light-plic.h51
-rw-r--r--arch/riscv/include/asm/csr.h2
-rw-r--r--arch/riscv/include/asm/dma-mapping.h2
-rw-r--r--arch/riscv/include/asm/global_data.h2
-rw-r--r--arch/riscv/lib/Makefile1
-rw-r--r--arch/riscv/lib/interrupts.c10
-rw-r--r--arch/riscv/lib/thead_plic.c155
17 files changed, 2167 insertions, 10 deletions
diff --git a/arch/riscv/cpu/c9xx/cpu.c b/arch/riscv/cpu/c9xx/cpu.c
index a7f9b3ea..ba370cfb 100644
--- a/arch/riscv/cpu/c9xx/cpu.c
+++ b/arch/riscv/cpu/c9xx/cpu.c
@@ -122,6 +122,7 @@ void invalid_dcache_range(unsigned long start, unsigned long end)
void icache_enable(void)
{
+#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_RISCV_MMODE
#ifdef CONFIG_TARGET_LIGHT_C910
asm volatile (
@@ -131,10 +132,12 @@ void icache_enable(void)
);
#endif
#endif
+#endif
}
void dcache_enable(void)
{
+#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_RISCV_MMODE
#ifdef CONFIG_TARGET_LIGHT_C910
asm volatile (
@@ -143,4 +146,5 @@ void dcache_enable(void)
);
#endif
#endif
+#endif
}
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index 93a73012..5b7ab92d 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -30,7 +30,9 @@
.align 2
.global trap_entry
trap_entry:
+#ifndef CONFIG_THEAD_PLIC
ebreak
+#endif
addi sp, sp, -32 * REGBYTES
SREG x1, 1 * REGBYTES(sp)
SREG x2, 2 * REGBYTES(sp)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 1bc93f69..67b3777d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
-dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-evt.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/light-a-ref.dts b/arch/riscv/dts/light-a-ref.dts
new file mode 100644
index 00000000..bbc0f27f
--- /dev/null
+++ b/arch/riscv/dts/light-a-ref.dts
@@ -0,0 +1,482 @@
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcal6408ahk_a: gpio@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "okay";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
+ lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
diff --git a/arch/riscv/dts/light-a-val.dts b/arch/riscv/dts/light-a-val.dts
index bbc0f27f..227f5a29 100644
--- a/arch/riscv/dts/light-a-val.dts
+++ b/arch/riscv/dts/light-a-val.dts
@@ -39,6 +39,12 @@
ranges;
u-boot,dm-pre-reloc;
+ intc: interrupt-controller@ffd8000000 {
+ compatible = "riscv,plic0";
+ reg = <0xff 0xd8000000 0x0 0x04000000>;
+ status = "disabled";
+ };
+
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
diff --git a/arch/riscv/dts/light-ant-evt.dts b/arch/riscv/dts/light-ant-ref.dts
index 65e56cf5..65e56cf5 100644
--- a/arch/riscv/dts/light-ant-evt.dts
+++ b/arch/riscv/dts/light-ant-ref.dts
diff --git a/arch/riscv/dts/light-b-power.dts b/arch/riscv/dts/light-b-power.dts
new file mode 100644
index 00000000..134ade96
--- /dev/null
+++ b/arch/riscv/dts/light-b-power.dts
@@ -0,0 +1,478 @@
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "disabled";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
+ lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
diff --git a/arch/riscv/dts/light-b-product.dts b/arch/riscv/dts/light-b-product.dts
index 65e56cf5..134ade96 100644
--- a/arch/riscv/dts/light-b-product.dts
+++ b/arch/riscv/dts/light-b-product.dts
@@ -151,13 +151,6 @@
#address-cells = <1>;
#size-cells = <0>;
-
- pcal6408ahk_a: gpio@20 {
- compatible = "nxp,pca9554";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
};
i2c5: i2c@fff7f2c000{
diff --git a/arch/riscv/dts/light-b-ref.dts b/arch/riscv/dts/light-b-ref.dts
new file mode 100644
index 00000000..65e56cf5
--- /dev/null
+++ b/arch/riscv/dts/light-b-ref.dts
@@ -0,0 +1,485 @@
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcal6408ahk_a: gpio@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "disabled";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
+ lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
diff --git a/arch/riscv/dts/light-beagle.dts b/arch/riscv/dts/light-beagle.dts
new file mode 100644
index 00000000..227f5a29
--- /dev/null
+++ b/arch/riscv/dts/light-beagle.dts
@@ -0,0 +1,488 @@
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ intc: interrupt-controller@ffd8000000 {
+ compatible = "riscv,plic0";
+ reg = <0xff 0xd8000000 0x0 0x04000000>;
+ status = "disabled";
+ };
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcal6408ahk_a: gpio@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "okay";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
+ lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
diff --git a/arch/riscv/include/asm/arch-thead/light-plic.h b/arch/riscv/include/asm/arch-thead/light-plic.h
new file mode 100644
index 00000000..a7c0fa48
--- /dev/null
+++ b/arch/riscv/include/asm/arch-thead/light-plic.h
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Liuw <lw312886@alibaba-inc.com>
+ *
+ * U-Boot syscon driver for Thead's Platform Level Interrupt Controller (PLIC)
+ */
+
+#ifndef _LIGHT_PLIC_H
+#define _LIGHT_PLIC_H
+
+/*
+ * M-mode
+ * hart id: 0, 2, 4, 6
+ * S-mode
+ * hart id: 1, 3, 5, 7
+ */
+
+/* interrupt priority register */
+#define PLIC_PRIO_REG(base, id) ((void __iomem *)(base) + 0x00 + (id) * 4)
+
+/* enable register */
+#define PLIC_ENABLE_REG(base, hart) ((void __iomem *)(base) + 0x2000 + (hart) * 0x80)
+
+/* pending registr */
+#define PLIC_PENDING_REG(base, hart) ((void __iomem *)(base) + 0x1000 + ((hart) / 4) * 4)
+
+/* threshold register */
+#define PLIC_THRESHOLD_REG(base, hart) ((void __iomem *)(base) + 0x200000 + (hart) * 0x1000 + 0x00)
+
+/* claim/complete register */
+#define PLIC_CLAIM_REG(base, hart) ((void __iomem *)(base) + 0x200000 + (hart) * 0x1000 + 0x04)
+
+#define MAX_IRQ_NUM 256
+typedef void (*irq_handler_t)(void);
+
+
+int irq_handler_register(int irq, irq_handler_t handler);
+
+void arch_local_irq_enable(void);
+
+void arch_local_irq_disable(void);
+
+void irq_enable(int hwirq);
+
+void irq_disable(int hwirq);
+
+void irq_priority_set(int prio);
+
+int plic_init(void);
+
+#endif
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index a524ffff..dd5601b0 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -12,6 +12,7 @@
#include <linux/const.h>
/* Status register flags */
+#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
@@ -71,6 +72,7 @@
/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
+#define MIE_MEIE (_AC(0x1, UL) << IRQ_M_EXT)
#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
diff --git a/arch/riscv/include/asm/dma-mapping.h b/arch/riscv/include/asm/dma-mapping.h
index 3d930c90..39b2c06c 100644
--- a/arch/riscv/include/asm/dma-mapping.h
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -15,7 +15,7 @@
static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
- *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
return (void *)*handle;
}
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index b74bd7e7..963bb9e1 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,7 +18,7 @@ struct arch_global_data {
#ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint; /* clint base address */
#endif
-#ifdef CONFIG_ANDES_PLIC
+#if (defined CONFIG_ANDES_PLIC) || (defined CONFIG_THEAD_PLIC)
void __iomem *plic; /* plic base address */
#endif
#ifdef CONFIG_ANDES_PLMT
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 58c7607c..b4444eef 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
obj-$(CONFIG_THEAD_IPI) += thead_ipi.o
+obj-$(CONFIG_THEAD_PLIC) += thead_plic.o
else
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
endif
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 3b25c5b7..1122aaf6 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -13,6 +13,11 @@
#include <asm/system.h>
#include <asm/encoding.h>
+__attribute__((weak)) int plic_init(void)
+{
+ return 0;
+}
+
static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
{
static const char * const exception_code[] = {
@@ -47,6 +52,8 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
int interrupt_init(void)
{
+ debug("[%s,%d]Initialize the plic\n", __func__, __LINE__);
+ plic_init();
return 0;
}
@@ -72,10 +79,12 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
is_irq = (cause & MCAUSE_INT);
irq = (cause & ~MCAUSE_INT);
+ debug("[%s,%d]\n", __func__, __LINE__);
if (is_irq) {
switch (irq) {
case IRQ_M_EXT:
case IRQ_S_EXT:
+ debug("[%s,%d]\n", __func__, __LINE__);
external_interrupt(0); /* handle external interrupt */
break;
case IRQ_M_TIMER:
@@ -90,6 +99,7 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
_exit_trap(cause, epc, regs);
}
+ debug("[%s,%d]\n", __func__, __LINE__);
return epc;
}
diff --git a/arch/riscv/lib/thead_plic.c b/arch/riscv/lib/thead_plic.c
new file mode 100644
index 00000000..87f6206b
--- /dev/null
+++ b/arch/riscv/lib/thead_plic.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Liuw <lw312886@alibaba-inc.com>
+ *
+ * U-Boot syscon driver for Thead's Platform Level Interrupt Controller (PLIC)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/csr.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+#include <asm/global_data.h>
+#include <cpu.h>
+#include <linux/err.h>
+#include <asm/arch-thead/light-plic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLIC_BASE_GET(void) \
+ do { \
+ long *ret; \
+ \
+ if (!gd->arch.plic) { \
+ ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
+ gd->arch.plic = ret; \
+ } \
+ } while (0)
+
+irq_handler_t irq_table[MAX_IRQ_NUM];
+
+void __iomem *plic_base = NULL;
+
+void external_interrupt(struct pt_regs *regs)
+{
+ void __iomem *claim;
+ irq_handler_t handler;
+ u32 irq_num;
+
+ debug("[%s,%d]\n", __func__, __LINE__);
+ if (!plic_base)
+ return;
+
+ debug("[%s,%d]\n", __func__, __LINE__);
+ claim = PLIC_CLAIM_REG(plic_base, 0);
+
+ while ((irq_num = readl(claim))) {
+ if (irq_num >= MAX_IRQ_NUM)
+ debug("Cannot find irq:%d\n", irq_num);
+ else {
+ handler = irq_table[irq_num];
+ if (handler)
+ handler();
+ writel(irq_num, claim);
+ }
+ }
+ debug("[%s,%d]\n", __func__, __LINE__);
+}
+
+static void plic_toggle(void __iomem *enable_base, int hwirq, int enable)
+{
+ u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
+ u32 hwirq_mask = 1 << (hwirq % 32);
+
+ if (enable)
+ writel(readl(reg) | hwirq_mask, reg);
+ else
+ writel(readl(reg) & ~hwirq_mask, reg);
+
+ debug("[%s,%d][0x%lx] = 0x%x\n", __func__, __LINE__,
+ (unsigned long)reg, readl(reg));
+}
+
+static void plic_set_threshold(void __iomem *thre_base, u32 threshold)
+{
+ writel(threshold, thre_base);
+ debug("[%s,%d][0x%lx] = 0x%x\n", __func__, __LINE__,
+ (unsigned long)thre_base, readl(thre_base));
+}
+
+static void plic_set_irq_priority(void __iomem *prio_base, int prio)
+{
+ writel(prio, prio_base);
+}
+
+int irq_handler_register(int irq, irq_handler_t handler)
+{
+ if (irq < 0 || irq >= MAX_IRQ_NUM) {
+ debug("invalid irq number to register\n");
+ return -EINVAL;
+ }
+
+ irq_table[irq] = handler;
+
+ return 0;
+}
+
+void arch_local_irq_enable(void)
+{
+ csr_set(CSR_MIE, MIE_MEIE);
+ csr_set(CSR_MSTATUS, SR_MIE);
+}
+
+void arch_local_irq_disable(void)
+{
+ csr_clear(CSR_MIE, MIE_MEIE);
+ csr_clear(CSR_MSTATUS, SR_MIE);
+}
+
+void irq_priority_set(int irq_id)
+{
+ plic_set_irq_priority(PLIC_PRIO_REG(gd->arch.plic, irq_id), 4);
+}
+
+void irq_enable(int hwirq)
+{
+ plic_toggle(PLIC_ENABLE_REG(gd->arch.plic, 0), hwirq, 1);
+}
+
+void irq_disable(int hwirq)
+{
+ plic_toggle(PLIC_ENABLE_REG(gd->arch.plic, 0), hwirq, 0);
+}
+
+int plic_init()
+{
+ PLIC_BASE_GET();
+ if (IS_ERR(gd->arch.plic))
+ return PTR_ERR(gd->arch.plic);
+
+ plic_base = gd->arch.plic;
+ debug("THEAD PLIC BASE: 0x%lx\n", (unsigned long)gd->arch.plic);
+
+ plic_set_threshold(PLIC_THRESHOLD_REG(gd->arch.plic, 0), 0);
+
+ arch_local_irq_enable(); //enale the global interrupt
+
+ return 0;
+}
+
+static const struct udevice_id thead_plic_ids[] = {
+ { .compatible = "riscv,plic0", .data = RISCV_SYSCON_PLIC},
+ { }
+};
+
+U_BOOT_DRIVER(thead_plic) = {
+ .name = "thead_light_plic",
+ .id = UCLASS_SYSCON,
+ .of_match = thead_plic_ids,
+};
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 12:55:51 +0000