diff options
| author | thead_admin <occ_thead@service.alibaba.com> | 2022-11-22 15:50:04 +0800 |
|---|---|---|
| committer | thead_admin <occ_thead@service.alibaba.com> | 2022-11-22 15:50:04 +0800 |
| commit | 0c8e009c3a52c6a29b00cf70d368d5c082639197 (patch) | |
| tree | a4389b0f036807156e36409123b58cbf3c78e656 /board/thead/light-c910/sys_clk.c | |
| parent | 43db9e00d5837c100c0b2fbbee64a08ab807d1e0 (diff) | |
Linux_SDK_V1.0.2Linux_SDK_V1.0.2
Diffstat (limited to 'board/thead/light-c910/sys_clk.c')
| -rw-r--r-- | board/thead/light-c910/sys_clk.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/board/thead/light-c910/sys_clk.c b/board/thead/light-c910/sys_clk.c index 167f9eea..641d8bdf 100644 --- a/board/thead/light-c910/sys_clk.c +++ b/board/thead/light-c910/sys_clk.c @@ -18,6 +18,8 @@ #define LIGHT_DSP_SUBSYS_ADDRBASE 0xffff041000 #define LIGHT_AUDIO_SUBSYS_ADDRBASE 0xffcb000000 #define LIGHT_APSYS_RSTGEN_ADDRBASE 0xffff015000 +#define LIGHT_DPU_CLOCK_GATING_CTRL0 0xffef601A28 +#define LIGHT_DPU_CLOCK_GATING_CTRL1 0xffef601A2C void show_sys_clk(void) { @@ -285,6 +287,52 @@ void sys_clk_config(void) tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8); tmp |= 0x30; writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8); + + /* The boards other than the LightA board perform the bus down-speed operation */ + +#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) + /* axi_sram_clk: 812.8512MHz -> 688.128MHz */ + tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104); + tmp |= 0x2000; + writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104); + + /* visys_aclk_m decrease frequency 792MHZ->594MHZ */ + tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1d0); + tmp &= ~0x00100000; + writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0); + + tmp &= ~0x000f0000; + tmp |= 0x00140000; + writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0); + /* vosys_aclk_m：792MHz->594MHz */ + tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1dc); + tmp &= ~0x00000020; + writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc); + + tmp &= ~0x0000000f; + tmp |= 0x00000024; + writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc); + + /* vpsys_axi_aclk：792MHz->594MHz */ + tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1e0); + tmp &= ~0x00001000; + writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0); + + tmp &= ~0x00000f00; + tmp |= 0x00001400; + writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0); + + /* npu_cclk：1000MHz->792MHz */ + tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8); + tmp |= 0x00000040; + writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8); + + + /* Enable dpu auto clock gating */ + writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL0); + writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL1); +#endif + #endif } |